Synchronous rectification control system and power supply system

Abstract

The embodiment of the utility model discloses a synchronous rectification control system and a power supply system, which are applied to the technical field of electronic information processing, and the synchronous rectification control system comprises a control module and a first side time sequence control module, and can be correspondingly used for performing time sequence control on a switching tube in a synchronous rectification system of a switching power supply. The first side time sequence control module can generate time sequence control signals according to midpoint voltage signals of two first bridge arms in the synchronous rectification system so as to drive corresponding full-bridge switch tubes, so that signal conversion for driving the full-bridge switch tubes is consistent with conversion of the midpoint voltage signals, and therefore, frequency conversion of the full-bridge switch tubes along with frequency conversion of input voltage cannot occur. The condition that the phase of the input voltage and the phase of the current are increased is avoided, so that the optimal turn-on time of synchronous rectification is realized, and the efficiency is maximized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic information processing, in particular to a control system for synchronous rectification and a power supply system. BACKGROUND

[0002] Synchronous rectification is a technology that uses a special power MOSFET with extremely low on-state resistance to replace a rectifier diode to reduce rectification loss, which can greatly improve the efficiency of a DC / DC converter and does not exist dead zone voltage caused by Schottky barrier voltage.

[0003] Synchronous rectification technology can significantly improve the conversion efficiency of a switching power supply under the condition of large current output, and is widely used in unidirectional switching power supplies, in which the current in the synchronous rectification switching tube is unidirectional. In recent years, the rise of the energy storage industry has made the demand for bidirectional power supplies more and more, and since the current of the switching tube is bidirectional, the traditional synchronous rectification technology cannot meet the demand of bidirectional. SUMMARY

[0004] The present application provides a control system for synchronous rectification and a power supply system, which realizes optimal synchronous rectification turn-on time.

[0005] The present application provides a control system for synchronous rectification, which is used for timing control of a synchronous rectification system, and the synchronous rectification system comprises a first side full-bridge circuit, the first side full-bridge circuit comprising two first bridge arms, and the control system for synchronous rectification comprises:

[0006] a control module for generating a first control signal;

[0007] a first side timing control module for detecting first midpoint voltage signals respectively corresponding to the two first bridge arms in the first side full-bridge circuit, and driving first full-bridge switching tubes in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that the phase shift time of synchronous rectification of the first full-bridge switching tubes is a second phase shift time, and the second phase shift time is a voltage conversion to position time of the first midpoint voltage signal.

[0008] The present application provides a power supply system, which comprises a synchronous rectification system and a control system for synchronous rectification, wherein:

[0009] the synchronous rectification system comprises a first side full-bridge circuit, a resonant network, an isolation transformer and a second side full-bridge circuit, and the first side full-bridge circuit and the second side full-bridge circuit each comprises two bridge arms;

[0010] The control system of the synchronous rectification is the control system of the synchronous rectification as described in one aspect of the embodiments of the present application.

[0011] It can be seen that the control system of the synchronous rectification in the embodiments of the present application includes the control module and the first side timing control module, and can perform timing control on the switching tube in the synchronous rectification system applied to the switching power supply. The first side timing control module can generate the timing control signal according to the midpoint voltage signal of the two first bridge arms in the synchronous rectification system to drive the corresponding full-bridge switching tube, so that the signal transformation of the full-bridge switching tube is consistent with the transformation of the midpoint voltage signal. Thus, the situation that the phase of the input voltage and the current phase increase with the frequency transformation of the input voltage is avoided, and the optimal turn-on time of the synchronous rectification is achieved, thereby maximizing the efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1a is a structural schematic diagram of a synchronous rectification system in the embodiments of the present application;

[0014] Figure 1b is a structural schematic diagram of another synchronous rectification system in the embodiments of the present application;

[0015] Figure 2a is a structural schematic diagram of a control system of the synchronous rectification provided by the embodiments of the present application;

[0016] Figure 2b is a structural schematic diagram of another control system of the synchronous rectification provided by the embodiments of the present application;

[0017] Figure 3a is a structural schematic diagram of a first side timing control module provided by the embodiments of the present application;

[0018] Figure 3b is a structural schematic diagram of a second side timing control module provided by the embodiments of the present application;

[0019] Figure 4 is a structural schematic diagram of a synchronous rectification system in the specific embodiments of the present application;

[0020] Figure 5 is a structural schematic diagram of a control module in the control system of the synchronous rectification in the specific embodiments of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0022] The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0023] The embodiments of the present application provide a control system of a synchronous rectification, mainly for timing control of a synchronous rectification system, such as Figure 1a As shown in FIG. 1, a synchronous rectification system can include a first side full-bridge circuit 10, specifically:

[0024] The first side full-bridge circuit 10 includes two first bridge arms, each of which can include two first full-bridge switching tubes 110, wherein each full-bridge switching tube can be a synchronous rectification tube, such as a MOSFET. The first side full-bridge circuit 10 can input a power supply, which is a unidirectional switching current system.

[0025] As shown in FIG. 2, another synchronous rectification system can include a first side full-bridge circuit 10, a resonant network 11, an isolation transformer 12 and a second side full-bridge circuit 13, specifically: Figure 1b The first side full-bridge circuit 10 includes two first bridge arms, each of which can include two first full-bridge switching tubes 110; the second side full-bridge circuit 13 includes two second bridge arms, each of which can include two second full-bridge switching tubes 113, wherein each full-bridge switching tube can be a synchronous rectification tube, such as a MOSFET. One side full-bridge circuit of the two side full-bridge circuits can input a high-voltage power supply, and the other side full-bridge circuit inputs a low-voltage power supply, which is a bidirectional switching current system.

[0026]

[0027] ​The resonant network 11 can specifically include two inductors and one capacitor, and is a DC-DC resonant network, which can form an LLC resonant circuit or an LC resonant circuit.

[0028] The resonant network 11 and the isolation transformer 12 are connected between the first-side full-bridge circuit 10 and the second-side full-bridge circuit 13.

[0029] If the first-side full-bridge circuit 10 is a high-voltage side full-bridge circuit, and the second-side full-bridge circuit 13 is a low-voltage side full-bridge circuit, the synchronous rectification system can include two working modes, i.e., a step-down mode and a step-up mode, and specifically:

[0030] In the step-down mode, the two inductors and the one capacitor in the resonant network 11 form an LLC resonant circuit, the switching frequency of the full-bridge switch tube in the first-side full-bridge circuit 10 is changed to input a high-voltage power supply, and the high-voltage power supply is converted into a low-voltage output through the isolation transformer 12, and at this time, the full-bridge switch tube in the second-side full-bridge circuit 13 is a synchronous rectification tube.

[0031] In the step-up mode, one inductor and one capacitor in the resonant network 11 form an LC resonant circuit, and the other inductor does not participate in the resonance, the switching frequency of the full-bridge switch tube in the second-side full-bridge circuit 13 is changed to input a low-voltage power supply, and the low-voltage power supply is converted into a high-voltage output through the isolation transformer 12, and at this time, the full-bridge switch tube in the first-side full-bridge circuit 10 is a synchronous rectification tube.

[0032] In a specific embodiment, as shown in FIG. 1, the synchronous rectification control system of the embodiment includes: Figure 1a

[0033] The control module 20 is configured to generate a first control signal.

[0034] The first-side timing control module 21 is configured to detect first midpoint voltage signals respectively corresponding to two first bridge arms in the first-side full-bridge circuit 10, and drive first full-bridge switch tubes 110 in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that a phase shift time of synchronous rectification of the first full-bridge switch tubes 110 is a second phase shift time, and the second phase shift time is a voltage transformation to position time of the first midpoint voltage signals. The voltage transformation to position of the first midpoint voltage signals means that one of the two first midpoint voltage signals is low, and the other is high.

[0035] ​In this way, when the first side timing control module 21 can generate timing control signals according to the midpoint voltage signals of the two first bridge arms in the synchronous rectification system, to drive the corresponding full-bridge switching tubes, so that the signal driving the full-bridge switching tube is transformed in accordance with the transformation of the midpoint voltage signal, so that the case of increasing between the phase of the input voltage and the current phase with the frequency transformation of the input voltage does not occur, and a better synchronous rectification turn-on time is achieved, thereby maximizing the efficiency.

[0036] In another embodiment, in the case of a synchronous rectification system such as Figure 1b as shown, including a first side full-bridge circuit 10, a resonant network 11, an isolation transformer 12, and a second side full-bridge circuit 13, the control system of the synchronous rectification of the embodiment includes:

[0037] The control module 20, the first side timing control module 21 and the second side timing control module 22, as shown in detail in Figure 2a

[0038] The control module 20 is used to generate a first control signal, a first enable signal, a second control signal and a second enable signal, the first enable signal is used to control the first side timing control module 21 to be in active mode, and the second enable signal controls the second side timing control module 22 to be in synchronous rectification mode.

[0039] The first side timing control module 21 is used to drive the first full-bridge switching tube 110 in the two first bridge arms according to the first control signal.

[0040] The second side timing control module 22 is used to detect the second midpoint voltage signal corresponding to the two second bridge arms in the second side full-bridge circuit 13 respectively, and drive the second full-bridge switching tube 113 in the two second bridge arms according to the second midpoint voltage signal and the second control signal, so that the phase shift time of the synchronous rectification of the second full-bridge switching tube is the first phase shift time, and the first phase shift time is the voltage transformation to position time of the second midpoint voltage signal. Here, the second midpoint voltage signal is the voltage signal between the two second full-bridge switching tubes 113 in any second bridge arm, and the voltage transformation to position of the second midpoint voltage signal means that one of the two second midpoint voltage signals is low, and the other is high.

[0041] ​Specifically, the second side timing control module 22 obtains a second comparison signal by combining the two second midpoint voltage signals, the control module 20 determines a first phase shift time according to the second comparison signal, and generates the second control signal according to the first phase shift time and outputs the second control signal to the second side timing control module 22, and the second side timing control module 22 drives the second full-bridge switch tube 113 to follow the second control signal. The first phase shift time can be the time difference between the starting time and the rising edge time of the second comparison signal, so that the transformation of the generated second control signal can be consistent with the transformation of the second midpoint voltage signal. In this way, by driving the first full-bridge switch tube 110 and the second full-bridge switch tube 113 through the first control signal and the second control signal respectively, the phase shift time between the second full-bridge switch tube 113 and the first full-bridge switch tube 110 can be the first phase shift time.

[0042] Here, the second comparison signal can be a signal indicating the difference between the two second midpoint voltage signals, for example, the second comparison signal can be a signal obtained by performing XOR operation on the two second midpoint voltage signals. When the two second midpoint voltage signals are both high or low, the obtained second comparison signal is low, and vice versa, the obtained second comparison signal is high.

[0043] In actual application, in order to ensure that the transformation of the generated second control signal is consistent with the transformation of the second midpoint voltage signal, the second control signal can be modified. Specifically, when driving the second full-bridge switch tube 113, the second side timing control module 22 can modify the second control signal according to the second midpoint voltage signal to obtain a second modified signal, so that the transformation of the second modified signal is consistent with the transformation of the second midpoint voltage signal, and then drive the second full-bridge switch tube 113 to follow the second modified signal.

[0044] It can be understood that if the first side full-bridge circuit 10 inputs a high-voltage power supply and the second side full-bridge circuit 13 inputs a low-voltage power supply, the first side timing control module 21 and the second side timing control module 22 mainly perform timing control when the synchronous rectification system is in the step-down mode. In other embodiments, the first side timing control module 21 and the second side timing control module 22 can also perform timing control when the synchronous rectification system is in the step-up mode, as shown in Figure 2b

[0045] The first enable signal generated by the control module 20 is also used to control the first side timing control module 21 to be in the synchronous rectification mode, and the second enable signal is also used to control the second side timing control module 22 to be in the active working mode.

[0046] ​The first side timing control module 21 is further configured to detect two first midpoint voltage signals respectively corresponding to two first bridge arms of the first side full-bridge circuit 10, and drive the first full-bridge switch tube 110 in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that the phase shift time of the synchronous rectification of the first full-bridge switch tube 110 is the second phase shift time, and the second phase shift time is the voltage transformation to position time of the first midpoint voltage signals. The voltage transformation to position of the first midpoint voltage signals means that one of the two first midpoint voltage signals is low voltage and the other is high voltage.

[0047] Specifically, the first side timing control module 21 obtains a first comparison signal by combining the two first midpoint voltage signals, the control module 20 determines the second phase shift time according to the first comparison signal, and generates the first control signal according to the second phase shift time and outputs the first control signal to the first side timing control module 21, and the first side timing control module 21 drives the first full-bridge switch tube 110 to follow the first control signal. The second phase shift time can be the time difference between the starting time and the rising edge time of the first comparison signal, so that the transformation of the generated first control signal can be consistent with the transformation of the first midpoint voltage signal. In this way, by driving the first full-bridge switch tube 110 and the second full-bridge switch tube 113 with the first control signal and the second control signal respectively, the phase shift time between the first full-bridge switch tube 110 and the second full-bridge switch tube 113 can be the second phase shift time.

[0048] Here, the first comparison signal can be a signal indicating the difference between the two first midpoint voltage signals. For example, the first comparison signal can be a signal obtained by performing XOR operation on the two first midpoint voltage signals. When the two first midpoint voltage signals are both high or low, the obtained first comparison signal is low, and vice versa.

[0049] In actual application, in order to ensure that the transformation of the generated first control signal is consistent with the transformation of the first midpoint voltage signal, the first control signal can be modified. Specifically, when driving the first full-bridge switch tube 110, the first side timing control module 21 can modify the first control signal according to the first midpoint voltage signal to obtain a first modified signal, so that the transformation of the first modified signal is consistent with the transformation of the first midpoint voltage signal, and then drive the first full-bridge switch tube 110 to follow the first modified signal.

[0050] The second side timing control module 22 is further configured to drive the second full-bridge switch tube 113 in the two second bridge arms according to the second control signal.

[0051] In a specific embodiment, the first side timing control module 21 and the second side timing control module 22 in the control system of the synchronous rectification can have the same structure, wherein the first side timing control module 21 can include, as shown in the figure, a drive generation circuit 211 composed of an XOR gate U1, two first AND gates U2 and U2', two OR gates U3 and U3', and two second AND gates U4 and U4', and can further include a first midpoint sampling conversion circuit 221 and a first output drive circuit 231, specifically: Figure 3a

[0052] The first midpoint voltage signals HV-VS1 and HV-VS2 are connected to the inputs of the XOR gate U1 and to the inputs of each of the first AND gates U2 and U2', and the output of the XOR gate U1 is connected to the inputs of each of the first AND gates U2 and U2'; the outputs of the two first AND gates U2 and U2' are connected to the inputs of the two OR gates U3 and U3', and the first enable signal HV-SYN-EN is connected to each of the OR gates U3 and U3'; the outputs of the two OR gates U3 and U3' are connected to the two second AND gates U4 and U4', and the two first control sub-signals PWM1 and PWM2 are connected to the two second AND gates U4 and U4', and the outputs of the two second AND gates U4 and U4' are connected to the drive ends of the first full-bridge switch tube 110.

[0053] In the specific implementation process, when connecting the first midpoint voltage signal to the drive generation circuit 211, a first midpoint sampling conversion circuit 221 can be used to convert the first midpoint voltage signals HV-VS1 and HV-VS2 and connect the converted first midpoint voltage signals VS1 and VS2 to the inputs of the XOR gate U1.

[0054] When driving the first full-bridge switch tube 110, the first output drive circuit 231 (denoted as U5 and U5') can be used to directly output drive signals to the first full-bridge switch tube 110, and the first output drive circuit 231 is used to convert the signals output by the two second AND gates U4 and U4' into drive signals HV-G1A, HV-G2B, HV-G2A and HV-G1B, and connect the drive signals to the drive ends of the first full-bridge switch tube 110.

[0055] ​In this way, the XOR gate U1 can perform XOR calculation on the signals VS1 and VS2 obtained by level conversion of the first midpoint voltage signals HV-VS1 and HV-VS2, to obtain the first comparison signal In0, which can ensure that when the potentials of the converted first midpoint voltage signals VS1 and VS2 are changed to positions, it can be reflected through the first comparison signal In0, such as when the converted first midpoint voltage signals VS1 and VS2 are both high or low, the first comparison signal In0 is low, and when the converted first midpoint voltage signals VS1 and VS2 are different, the first comparison signal In0 is high.

[0056] Further, the two first AND gates U2 and U2' are combined with the first comparison signal In0, and output the synchronous rectification signals In1 and In1', respectively, which reflect the changes of the converted first midpoint voltage signals VS1 and VS2, and can also reflect the changes of the first midpoint voltage signals HV-VS1 and HV-VS2. Then, the two OR gates U3 and U3' are combined with the first enable signal, which can make the synchronous rectification signals be ignored when the first side timing control module 21 is in the active working mode, and output the synchronous rectification signals In2 and In2', respectively, when the first side timing control module 21 is in the synchronous rectification mode. Finally, in the synchronous rectification mode, the two second AND gates U4 and U4' can modify the two first control sub-signals PWM1 and PWM2, respectively, that is, modify them through the synchronous rectification signals In2 and In2', respectively, and the modification time is the first phase shift time, so that the changes of the obtained first modified signals are consistent with the changes of the first midpoint voltage signals.

[0057] In this process, the output of the XOR gate U1 is connected to the control module 20, so that the control module 20 generates the first control signal according to the first comparison signal In0 output by the XOR gate U1.

[0058] Further, the second side timing control module 22 can include, as shown in Figure 3b , a drive generation circuit 212 composed of an XOR gate U6, two first AND gates U7 and U7', two OR gates U8 and U8', and two second AND gates U9 and U9', and can also include a second midpoint sampling conversion circuit 222 and a second output drive circuit 232, specifically:

[0059] The second midpoint voltage signals LV-VS1 and LV-VS2 are connected to the input of the XOR gate U6, and are connected to the input of each first AND gate U7 and U7' respectively, and the output of the XOR gate U6 is connected to the input of each first AND gate U7 and U7' respectively; the outputs of the two first AND gates U7 and U7' are connected to the input of two OR gates U8 and U8' respectively, and the second enable signal LV-SYN-EN is connected to each OR gate U8 and U8' respectively; the outputs of the two OR gates U8 and U8' are connected to two second AND gates U9 and U9' respectively, and the two second control signals PWM3 and PWM4 are connected to the two second AND gates U9 and U9' respectively, and the outputs of the two second AND gates U9 and U9' are connected to the driving end of the second full-bridge switch tube 130. The output of the XOR gate U6 is connected to the control module 20.

[0060] In the specific implementation process, when the second midpoint voltage signal is connected to the drive generation circuit 212, a second midpoint sampling conversion circuit 222 can be used to convert the second midpoint voltage signals LV-VS1 and LV-VS2, and connect the converted second midpoint voltage signals VS3 and VS4 to the input of the XOR gate U6.

[0061] When the second full-bridge switch tube 113 is driven, a second output drive circuit 232 (denoted as U10 and U10') can be used to directly output a drive signal to the second full-bridge switch tube 113, and the second output drive circuit 232 is used to convert the signals output by the two second AND gates U9 and U9' into drive signals LV-G3A, LV-G4B, LV-G4A and LV-G3B, and connect the drive signals to the driving end of the second full-bridge switch tube 130.

[0062] Specifically, the XOR gate U6 can perform XOR calculation on the signals VS3 and VS4 obtained by level conversion of the second midpoint voltage signals LV-VS1 and LV-VS2, to obtain the second comparison signal In0', which can ensure that when the potentials of the two converted second midpoint voltage signals VS3 and VS4 are changed to bits, it can be reflected through the second comparison signal In0'. For example, when the converted second midpoint voltage signals VS3 and VS4 are both high or low, the second comparison signal In0' is low, and when the converted second midpoint voltage signals VS3 and VS4 are different, the second comparison signal In0' is high.

[0063] Further, both the first AND gates U7 and U7' combine the second comparison signal In0', and output the synchronous rectification signals In3 and In3', respectively, which represent the transformation of the converted second midpoint voltage signals VS3 and VS4, and also represent the transformation of the second midpoint voltage signals LV-VS1 and LV-VS2. Then, the two OR gates U8 and U8' combine the second enable signal, which can make the synchronous rectification signals be ignored when the second side timing control module 22 is in the active working mode, and output the synchronous rectification signals In4 and In4', respectively, when the second side timing control module 22 is in the synchronous rectification mode. Finally, in the synchronous rectification mode, the two second AND gates U9 and U9' can modify the two second control sub-signals PWM3 and PWM4, respectively, by the synchronous rectification signals In4 and In4', respectively, and the modification time is the second phase shift time, so that the transformation of the obtained second modified signals is consistent with the transformation of the second midpoint voltage signals.

[0064] In this process, the output of the XOR gate U6 is connected to the control module 20, so that the control module 20 generates the second control signal according to the second comparison signal In0' output by the XOR gate U6.

[0065] It can be seen that the control system of the synchronous rectification in the embodiment includes the control module 20, the first side timing control module 21 and the second side timing control module 22, which can perform timing control on the switching tubes in the synchronous rectification system applied to the bidirectional switching power supply, and when the side timing control module in the synchronous rectification mode can generate the timing control signal according to the midpoint voltage signals of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switching tube, so that the transformation of the signal driving the full-bridge switching tube is consistent with the transformation of the midpoint voltage signals, so that the situation that the phase difference between the input voltage and the current of the resonant inductor after the resonant network increases with the frequency transformation of the input voltage of the active working mode side does not occur, the optimal synchronous rectification turn-on time is achieved, and the efficiency is maximized.

[0066] One specific embodiment of the present application provides a control system of synchronous rectification, which mainly performs timing control on a synchronous rectification system. In the embodiment, the synchronous rectification system can be as shown in Figure 4 , wherein:

[0067] The first side full-bridge circuit 10 is specifically a high-voltage side full-bridge circuit, and a high-voltage power supply HVDC is input. The first full-bridge switch tubes included in the high-voltage side full-bridge circuit are Q1A, Q2A, Q1B, and Q2B. The signals for driving these full-bridge switch tubes are HV-G1A, HV-G2A, HV-G1B, and HV-G2B, respectively. The first midpoint voltage signals of the two first bridge arms are HV-VS1 and HV-VS2, respectively. The second side full-bridge circuit 13 is specifically a low-voltage side full-bridge circuit, and a low-voltage power supply LVDC is input. The second full-bridge switch tubes included in the low-voltage side full-bridge circuit are Q3A, Q4A, Q3B, and Q4B. The signals for driving these full-bridge switch tubes are LV-G3A, LV-G4A, LV-G3B, and LV-G4B, respectively. The second midpoint voltage signals of the two second bridge arms are LV-VS1 and LV-VS2, respectively.

[0068] The resonant network 11 is specifically a DC-DC resonant network, and includes an inductor Lr, an inductor Lm, and a capacitor Cr. The isolation transformer 12 is T1.

[0069] The first side timing control module 21 and the second side timing control module 22 in the control system of the synchronous rectification can be specifically as shown in the above Figure 3a and Figure 3b The control module 20 in the control system is specifically a controller U0 as shown in the above Figure 5 , which can generate the first enable signal HV-SYN-EN, the second enable signal LV-SYN-EN, two first control sub-signals PWM1 and PWM2 in the first control signal, and two second control sub-signals PWM3 and PWM4 in the second control signal.

[0070] In this way, in the embodiment, the control system of the synchronous rectification can perform timing control on the synchronous rectification system in the following two modes of the synchronous rectification system:

[0071] I. The synchronous rectification system is in a step-down mode

[0072] When the synchronous rectification system is in the step-down mode, the Lr, Cr, and Lm in the resonant network 11 form an LLC resonant circuit. The switching frequency of the first full-bridge switch tubes Q1A, Q1B, Q2A, and Q2B in the high-voltage side full-bridge circuit is changed to convert the high-voltage input voltage HVDC into a low-voltage output voltage LVDC through the isolation transformer T1. The second full-bridge switch tubes Q3A, Q3B, Q4A, and Q4B in the low-voltage side full-bridge circuit are synchronous rectification tubes. In this case, in the control system of the synchronous rectification:

[0073] (1) When the synchronous rectification system is in the step-down mode, the controller U0 generates a first enable signal HV_SYN_EN which is low, controls the first side timing control module 21 to be in the active mode, and generates two first control sub-signals PWM1 and PWM2. The two first control sub-signals have a certain dead zone, an approximately 50% duty cycle and a high-low complement, and are frequency-variable square waves.

[0074] (2) The first midpoint sampling conversion circuit 221 in the first side timing control module 21 collects the first midpoint voltage signals HV-VS1 and HV-VS2 of the two bridge arms of the high-voltage side full-bridge circuit in the synchronous rectification system, obtains the converted signals VS1 and VS2, and outputs the converted signals VS1 and VS2 to the two first AND gates U2 and U2' respectively, and also connects the converted signals VS1 and VS2 to the inputs of the XOR gate U1 respectively, so that the XOR gate U1 outputs a signal In0 according to the two converted signals VS1 and VS2.

[0075] The first AND gate U2 outputs a signal In1 according to the converted signal VS1 and the signal In0, and the first AND gate U2' outputs a signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs a signal In2 according to the signal In1 and the first enable signal HV_SYN_EN, and the OR gate U3' outputs a signal In2' according to the signal In1' and the first enable signal HV_SYN_EN. The signals In2 and In2' are high. The second AND gate U4 outputs a signal following the first control sub-signal PWM1 according to the signal In2 and the first control sub-signal PWM1, and the second AND gate U4' outputs a signal following the first control sub-signal PWM2 according to the signal In2' and the first control sub-signal PWM2.

[0076] The outputs of the second AND gates U4 and U4' are connected to the two first output drive circuits 231 (denoted as U5 and U5') to output drive signals, which drive the first full-bridge switching tubes Q1A and Q2B and Q2A and Q1B respectively.

[0077] (3) The second midpoint sampling conversion circuit 222 in the second side timing control module 22 collects the second midpoint voltage signals LV-VS1 and LV-VS2 of the two bridge arms of the low-voltage side full-bridge circuit in the synchronous rectification system, obtains the converted signals VS3 and VS4, and outputs the converted signals VS3 and VS4 to the two first AND gates U7 and U7' respectively, and also connects the converted signals VS3 and VS4 to the inputs of the XOR gate U6 respectively, so that the XOR gate U6 outputs a signal In0' according to the two converted signals VS3 and VS4.

[0078] The first AND gate U7 outputs a signal In3 according to the converted signal VS3 and the signal In0', and the first AND gate U7' outputs a signal In3' according to the converted signal VS4 and the signal In0'. The OR gate U8 outputs a signal In4 according to the signal In3 and a second enable signal LV_SYN_EN, and the OR gate U8' outputs a signal In4' according to the signal In3' and the second enable signal LV_SYN_EN. The second enable signal LV_SYN_EN is always low, and thus the signals In4 and In4' follow the signals In3 and In3', respectively. The second AND gate U9 outputs a signal to the second output drive circuit 232 (denoted as U10) according to the signal In4 and a second control sub-signal PWM3, and the second AND gate U9' outputs a signal to the second output drive circuit 232 (denoted as U10') according to the signal In4' and another second control sub-signal PWM4.

[0079] The second output drive circuit 232 outputs a drive signal to drive the second full-bridge switch Q3A and Q4B and the Q4A and Q3B, respectively.

[0080] In this process, the controller U0 can calculate a first phase shift time of the synchronous rectification (relative to the rising edge signal of In0) according to the rising edge signal of the signal In0', and set the starting point of the high level signals of the two second control sub-signals PWM3 and PWM4 based on the first phase shift time. The falling edges of the two second control sub-signals PWM3 and PWM4 are moved backward by the first phase shift time based on the falling edges of the two first control sub-signals PWM1 and PWM2, to set the ending point of the high level signals of the two second control sub-signals PWM3 and PWM4.

[0081] In this process, the controller U0 can calculate a first phase shift time of the synchronous rectification (relative to the rising edge signal of In0) according to the rising edge signal of the signal In0', and set the starting point of the high level signals of the two second control sub-signals PWM3 and PWM4 based on the first phase shift time. The falling edges of the two second control sub-signals PWM3 and PWM4 are moved backward by the first phase shift time based on the falling edges of the two first control sub-signals PWM1 and PWM2, to set the ending point of the high level signals of the two second control sub-signals PWM3 and PWM4.

[0082] In addition, the signals for driving the first full-bridge switch 110 follow the first control sub-signals PWM1 and PWM2, and the signals for driving the second full-bridge switch 113 follow the second control sub-signals PWM3 and PWM4, so that the phase shift between the second full-bridge switch 113 and the first full-bridge switch 110 is the first phase shift time.

[0083] (4) When the synchronous rectification system is in the step-down mode, the XOR gate U6 in the second side timing control module 22 is an interlocking circuit. When the converted signals VS3 and VS4 pass through the high or low level, the signal In0' is low, and thus the synchronous rectification signals In4 and In4' are low, and the synchronous rectification drive is closed.

[0084] The functions of the two first AND gates U7 and U7' are to insert the signal In0' into the converted signals VS3 and VS4, and then output the synchronous rectification signals In4 and In4'. The functions of the two OR gates U8 and U8' are to output the synchronous rectification signals In4 and In4' under the condition of the step-down mode. The functions of the two second AND gates U9 and U9' are to increase the synchronous rectification signals In4 and In4' respectively by the second control sub-signals PWM3 and PWM4, and improve the reliability.

[0085] II. The synchronous rectification system is in the step-up mode

[0086] When the synchronous rectification system is in the step-up mode, the Lr and Cr in the resonant network 11 form an LC resonant circuit, and the change of the switching frequency of the second full-bridge switches Q3A, Q3B, Q4A and Q4B in the low-voltage side full-bridge circuit converts the low-voltage input voltage LVDC into a high-voltage output voltage HVDC through the isolation transformer T1, and the first full-bridge switches Q1A, Q1B, Q2A and Q2B in the high-voltage side full-bridge circuit are synchronous rectification tubes. In this case, the control system of the synchronous rectification is:

[0087] (1) When the synchronous rectification system is in the step-up mode, the second enable signal LV_SYN_EN generated by the controller U0 is low, and the second side timing control module 22 is in the active working mode; and two second control sub-signals PWM3 and PWM4 are generated, which have a certain dead zone, an approximately 50% duty cycle and a high-low complement, and are frequency-variable square waves.

[0088] (2) The second midpoint sampling and conversion circuit 222 in the second side timing control module 22 collects the second midpoint voltage signals LV-VS1 and LV-VS2 of the two bridge arms of the low-voltage side full-bridge circuit in the synchronous rectification system, and obtains the converted signals VS3 and VS4, which are respectively output to the two first AND gates U7 and U7', and are also respectively connected to the inputs of the XOR gate U6. In this way, the XOR gate U6 outputs the signal In0' according to the two converted signals VS3 and VS4.

[0089] The first AND gate U7 outputs a signal In3 according to the converted signal VS3 and the signal In0', and the first AND gate U7' outputs a signal In3' according to the converted signal VS4 and the signal In0'. The OR gate U8 outputs a signal In4 according to the signal In4 and a second enable signal LV_SYN_EN, and the OR gate U8' outputs a signal In4' according to the signal In3' and the second enable signal LV_SYN_EN. The signals In4 and In4' are high. The second AND gate U9 outputs a signal following a second control sub-signal PWM3 according to the signal In4 and the second control sub-signal PWM3, and the second AND gate U9' outputs a signal following a second control sub-signal PWM4 according to the signal In4' and the second control sub-signal PWM4.

[0090] The outputs of the second AND gates U9 and U9' are respectively connected to two second output drive circuits 232 (denoted as U10 and U10') to output drive signals for driving the second full-bridge switching tubes Q3A and Q4B and Q4A and Q3B respectively, following the second control sub-signals.

[0091] (3) The first midpoint sampling and converting circuit 221 in the first side timing control module 21 collects the first midpoint voltage signals HV-VS1 and HV-VS2 of the two bridge arms of the high-voltage side full-bridge circuit in the synchronous rectification system, and obtains converted signals VS1 and VS2 which are respectively output to the two first AND gates U2 and U2', and are also respectively connected to the inputs of the XOR gate U1. Thus, the XOR gate U1 outputs a signal In0 according to the two converted signals VS1 and VS2.

[0092] The first AND gate U2 outputs a signal In1 according to the converted signal VS1 and the signal In0, and the first AND gate U2' outputs a signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs a signal In2 according to the signal In1 and a first enable signal HV_SYN_EN, and the OR gate U3' outputs a signal In2' according to the signal In1' and the first enable signal HV_SYN_EN. The first enable signal HV_SYN_EN is constant at a low level, so the signals In2 and In2' respectively follow the signals In1 and In1'. The second AND gate U4 outputs a signal to the first output drive circuit 231 (denoted as U5) according to the signal In2 and a first control sub-signal PWM1, and the second AND gate U4' outputs a signal to the first output drive circuit 231 (denoted as U5') according to the signal In2' and another first control sub-signal PWM2.

[0093] The first output drive circuit 231 outputs drive signals for driving the first full-bridge switching tubes Q1A and Q2B and Q2A and Q1B respectively.

[0094] In this process, the controller U0 can calculate the second phase shift time of the synchronous rectification (relative to the rising edge signal of In0') according to the rising edge signal of the signal In0, and set the starting point of the high level signal of the two first control sub-signals PWM1 and PWM2 based on the second phase shift time, while the falling edge of the two first control sub-signals PWM1 and PWM2 is moved backward by the second phase shift time based on the falling edge of the two second control sub-signals PWM3 and PWM4 to set the ending point of the high level signal of the two first control sub-signals PWM1 and PWM2.

[0095] In this process, the controller U0 can calculate the second phase shift time of the synchronous rectification (relative to the rising edge signal of In0') according to the rising edge signal of the signal In0, and set the starting point of the high level signal of the two first control sub-signals PWM1 and PWM2 based on the second phase shift time, while the falling edge of the two first control sub-signals PWM1 and PWM2 is moved backward by the second phase shift time based on the falling edge of the two second control sub-signals PWM3 and PWM4 to set the ending point of the high level signal of the two first control sub-signals PWM1 and PWM2.

[0096] In addition, since the signal driving the second full-bridge switch tube 113 follows the second control sub-signals PWM3 and PWM4, and the signal driving the first full-bridge switch tube 110 follows the first control sub-signals PWM1 and PWM2, the phase shift between the first full-bridge switch tube 110 and the second full-bridge switch tube 113 is the second phase shift time.

[0097] (4) When the synchronous rectification system is in the boost mode, the XOR gate U1 in the first side timing control module 21 is an interlocking circuit, when the converted signals VS1 and VS2 pass through the high or low level, the output signal In0 is low, and then the synchronous rectification signals In2 and In2' are low, and the synchronous rectification drive is closed.

[0098] The functions of the two first AND gates U2 and U2' are to insert the synchronous rectification signals of the converted signals VS1 and VS2 into the signal In0, and then output the synchronous rectification signals In2 and In2'. The functions of the two OR gates U3 and U3' are to output the synchronous rectification signals In2 and In2' under the condition of the boost mode. The functions of the two second AND gates U4 and U4' are to increase the synchronous rectification signals In2 and In2' respectively under the condition of the first control sub-signals PWM1 and PWM2, and to improve the reliability.

[0099] The embodiment of the present application also provides a power supply system, which is a bidirectional switching power supply, mainly applying the synchronous rectification system as shown in the above Figure 1b or Figure 4 The synchronous rectification system can include: a first side full-bridge circuit, a resonant network, an isolation transformer and a second side full-bridge circuit, and the first side full-bridge circuit and the second side full-bridge circuit each include two bridge arms; and the control system of the synchronous rectification is the control system of the synchronous rectification as shown in the above Figure 2a or Figure 2b The control system of the synchronous rectification is not described herein.

[0100] The application further provides a power supply system, which is a unidirectional switching power supply, mainly applying the synchronous rectification system as shown in the above Figure 1a The synchronous rectification system can include a first side full-bridge circuit including two first bridge arms, and a control system of the synchronous rectification is the control system of the synchronous rectification as shown in the above embodiment, which will not be repeated here. Figure 1a

[0101] Those skilled in the art can understand that all or part of the steps in the above-mentioned various methods of the embodiments can be completed by a program instructing the related hardware, and the program can be stored in a computer readable storage medium, which can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0102] The above describes in detail the control system of the synchronous rectification and the power supply system provided by the embodiments of the application. The principles and implementation manners of the application are described by applying specific examples. The above embodiment is only used to help understand the method of the application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation manner and application range will be changed. In conclusion, the content of the specification should not be understood as a limitation of the application.​

Claims

1. A control system for synchronous rectification, characterized by, The application relates to a timing control system for a synchronous rectification system, the synchronous rectification system comprising: a first side full-bridge circuit comprising two first bridge arms, the synchronous rectification control system comprising: a control module for generating a first control signal; a first side timing control module for detecting first midpoint voltage signals corresponding to the two first bridge arms of the first side full-bridge circuit respectively, and driving first full-bridge switch tubes in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that the phase shift time of the synchronous rectification of the first full-bridge switch tubes is a second phase shift time, the second phase shift time being a voltage transformation to position time of the first midpoint voltage signals.

2. The system of claim 1, wherein, The synchronous rectification system further comprises a resonance network, an isolation transformer and a second side full-bridge circuit comprising two second bridge arms; The control module is further configured to generate a first enable signal, a second control signal and a second enable signal, the first enable signal being used to control the first side timing control module to be in a synchronous rectification mode, and the second enable signal being used to control a second side timing control module to be in an active operation mode; The synchronous rectification control system further comprises: The second side timing control module is further configured to drive second full-bridge switch tubes in the two second bridge arms according to the second control signal.

3. The system of claim 2, wherein: The first enable signal generated by the control module is further used to control the first side timing control module to be in an active operation mode, and the second enable signal generated by the control module is further used to control the second side timing control module to be in a synchronous rectification mode; The first side timing control module is further configured to drive the first full-bridge switch tubes in the two first bridge arms according to the first control signal; The second side timing control module is further configured to detect second midpoint voltage signals corresponding to the two second bridge arms of the second side full-bridge circuit respectively, and drive the second full-bridge switch tubes in the two second bridge arms according to the second midpoint voltage signals and the second control signal, so that the phase shift time of the synchronous rectification of the second full-bridge switch tubes is a first phase shift time, the first phase shift time being a voltage transformation to position time of the second midpoint voltage signals.

4. The system of claim 3, wherein, The first side timing control module comprises an XOR gate, two first AND gates, two OR gates and two second AND gates; The first midpoint voltage signals are connected to the inputs of the XOR gate and the inputs of each first AND gate, and the outputs of the XOR gate are connected to the inputs of each first AND gate; The outputs of the two first AND gates are connected to the inputs of the two OR gates, and the first enable signal is connected to each OR gate; The outputs of the two OR gates are connected to the two second AND gates, two first control sub-signals in the first control signal are connected to the two second AND gates, and the outputs of the two second AND gates are connected to the driving ends of the first full-bridge switch tubes.

5. The system of claim 4, wherein, The output of the XOR gate in the first side timing control module is connected to the control module, and the control module is configured to generate a first control signal according to a first comparison signal output by the XOR gate.

6. The system of claim 4, wherein, The first side timing control module further comprises a first midpoint sampling conversion circuit and a first output driving circuit, wherein: The first midpoint sampling conversion circuit is configured to convert the first midpoint voltage signal and connect the converted first midpoint voltage signal to the input of the XOR gate. The first output driving circuit is configured to convert the signals output by the two second AND gates into driving signals and connect the driving signals to the driving ends of the first full-bridge switching tubes.

7. The system of claim 4, wherein, The second side timing control module comprises an XOR gate, two first AND gates, two OR gates and two second AND gates. The second midpoint voltage signal is connected to the input of the XOR gate and the input of each of the first AND gates, and the output of the XOR gate is connected to the input of each of the first AND gates. The outputs of the two first AND gates are connected to the inputs of the two OR gates, and the second enable signal is connected to each of the OR gates. The outputs of the two OR gates are connected to the two second AND gates, two second control sub-signals in the second control signal are connected to the two second AND gates, and the outputs of the two second AND gates are connected to the driving ends of the second full-bridge switching tubes.

8. The system of claim 7, wherein, The output of the XOR gate in the second side timing control module is connected to the control module, and the control module is configured to generate a second control signal according to a second comparison signal output by the XOR gate.

9. The system of claim 7, wherein, The second side timing control module further comprises a second midpoint sampling conversion circuit and a second output driving circuit, wherein: The second midpoint sampling conversion circuit is configured to convert the second midpoint voltage signal and connect the converted second midpoint voltage signal to the input of the XOR gate in the second side timing control module. The second output driving circuit is configured to convert the signals output by the second AND gates in the two second side timing control modules into driving signals and connect the driving signals to the driving ends of the second full-bridge switching tubes.

10. A power supply system characterized by comprising: It comprises: A synchronous rectification system and a control system of the synchronous rectification, wherein: The synchronous rectification system comprises a first side full-bridge circuit, a resonant network, an isolation transformer and a second side full-bridge circuit, and the first side full-bridge circuit and the second side full-bridge circuit each comprises two bridge arms. The control system of the synchronous rectification is the control system of the synchronous rectification according to any one of claims 1 to 9.

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