Novel balun circuit

Abstract

The utility model discloses a novel balun circuit. The novel balun circuit comprises a first sub-circuit and a second sub-circuit, the grid electrode of the first MOS tube is in coupling connection with the signal input end, the first pole is connected with the grid electrode of the second MOS tube, the second pole is connected with the grid electrode of the third MOS tube, the first pole of the second MOS tube is connected with the positive electrode of the second voltage source, and the second pole is grounded; the first pole of the third MOS tube is connected with the positive pole of the second voltage source, the second pole of the third MOS tube is grounded, and a radio frequency signal received by the signal input end is transmitted to the first MOS tube and generates a first differential signal and a second differential signal; the first differential signal is transmitted to the second MOS tube and generates a first amplification differential signal, and the second differential signal is transmitted to the third MOS tube and generates a second amplification differential signal. The novel balun circuit provided by the utility model is simple in structure, and the amplitude and phase matching degree of output differential signals is high, so that the signal conversion is more efficient and reliable, and the performance is excellent.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit technical field especially relates to a novel balun circuit. BACKGROUND

[0002] With the rapid development of communication technology, especially the popularity of mobile communication and wireless networks, the demand for signal interference and noise suppression is increasingly high. A differential signal is composed of two signals with equal amplitude but opposite phase. Differential signals can effectively suppress common-mode noise, common-mode interference, common-mode signals and odd harmonics, are conducive to maintaining the integrity of the signal, and have a virtual potential ground, and are widely used in radio frequency and analog integrated circuit design.

[0003] Converting a single-ended signal to a differential signal can effectively suppress the influence of noise and facilitate the subsequent radio frequency link to further extract differential mode signals and common mode signals. A balun is an electronic functional unit that realizes the transition of a single-ended signal to a differential signal, and is divided into active and passive categories. Passive baluns generally have no power consumption, high linearity, and simple structure, and have no special requirements for semiconductor process, but the inherent 3dB insertion loss is the fatal weakness of passive baluns, especially before low-noise amplification. Although active baluns have power consumption and limited dynamic range in linear operation, they have strong practicality in providing signal gain within a certain bandwidth. Active balun circuits are simple, have extremely small integrated areas, and active baluns have certain advantages in bandwidth compared to passive baluns.

[0004] The design and application of balun circuits are also evolving. Today's balun circuits are not only used in wireless communication systems, but also widely used in high-speed digital communication systems, radio frequency identification (RFID) systems, medical devices and other fields.

[0005] The demand for wideband signal transmission in communication systems is increasing. Ultra-wideband balun circuits can better meet the demand for such wideband communication. Using ultra-wideband balun can help achieve fast switching and transmission between different frequency bands, making the integration of radio frequency systems more flexible and adapting to different frequency requirements. It lays the foundation for future technology applications, such as millimeter wave communication, 6G technology, etc. These new technologies usually require higher frequency bands and wider bandwidths for transmission.

[0006] A common active balun is based on a MOS transistor "source coupled pair" to realize the conversion from asymmetric line to symmetric line. But its structure has inherent defects, resulting in narrow bandwidth and low balance degree of the balun. The port one and the port two of the balun are not equal in line implementation. When there is an RF input signal, especially when the input signal is strong, the potentials of the port one and the port two will be different, thus causing the difference in amplitude of the signals at the two output ends.

[0007] Another method to overcome the above-mentioned inherent defects is to separate the coupling of the "source coupled pair", load the RF input signal on the two MOS transistors at the same time, and realize the 180-degree phase difference of the differential signal by using the phase difference between the common-gate configuration (CG) and the common-source configuration (CS). But this structure is relatively complex, and due to the large difference between the common-gate configuration (CG) and the common-source configuration (CS) in DC and RF characteristics, it is difficult to realize the differential matching of phase and amplitude in a wide band range, and it is sensitive to process (Process), voltage (Voltage) and temperature (Temperature) changes, which is not conducive to tape-out.

[0008] As can be seen, the existing balun has the problems of uneven frequency response, narrow bandwidth and low balance degree. Content of the utility model

[0009] The utility model provides a novel balun circuit, and the amplification circuit composed of the second subcircuit is used as the basis, the source impedance of the first MOS transistor in the first subcircuit is continuously increased, the difference between the drain and source impedance of the first MOS transistor approaches zero, thus the circuit design of the balun line can be realized by a single transistor, the current (including DC and RF AC) of the source impedance and the drain impedance of the single transistor is basically same in any case, the high matching or even absolute matching of the two output differential signals is guaranteed from the structure, the possibility of ultra-wideband operation is provided from the line structure, and the signal conversion is more efficient, reliable and excellent in performance.

[0010] According to the first aspect of the utility model, a novel balun circuit is provided, which comprises a first subcircuit and a second subcircuit, the first subcircuit comprises a first MOS transistor and a first voltage source, the second subcircuit comprises a second MOS transistor, a third MOS transistor and a second voltage source.

[0011] The gate of the first MOS tube is coupled with a signal input end, the first pole of the first MOS tube is connected with the gate of the second MOS tube, the second pole of the first MOS tube is connected with the gate of the third MOS tube, the positive pole of the first voltage source is connected with the gate of the first MOS tube, and the negative pole of the first voltage source is grounded.

[0012] The first pole of the second MOS tube is connected with the positive pole of the second voltage source, and the second pole of the second MOS tube is grounded; the first pole of the third MOS tube is connected with the positive pole of the second voltage source, and the second pole of the third MOS tube is grounded, and the negative pole of the second voltage source is grounded.

[0013] The radio frequency signal received by the signal input end is transmitted to the first MOS tube and generates a first differential signal and a second differential signal; the first differential signal is transmitted to the second MOS tube and generates a first amplified differential signal, and the second differential signal is transmitted to the third MOS tube and generates a second amplified differential signal, wherein the amplitudes of the first differential signal and the second differential signal are equal, and the phases are opposite.

[0014] Optionally, the first sub-circuit further comprises a first capacitor and a first resistor.

[0015] The first end of the first capacitor is connected with the signal input end, and the second end of the first capacitor is connected with the gate of the first MOS tube.

[0016] The first end of the first resistor is connected with the gate of the first MOS tube, and the second end of the first resistor is connected with the positive pole of the first voltage source.

[0017] Optionally, the first sub-circuit further comprises a second resistor and a third resistor.

[0018] The first end of the second resistor is connected with the second pole of the first MOS tube, and the second end of the second resistor is grounded.

[0019] The first end of the third resistor is grounded, and the second end of the third resistor is connected with the first pole of the first MOS tube; wherein the resistance values of the second resistor and the third resistor are equal.

[0020] Optionally, the second sub-circuit further comprises a fourth resistor, a second capacitor, a fifth resistor and a third capacitor.

[0021] The first end of the fourth resistor is grounded, and the second end of the fourth resistor is connected with the gate of the second MOS tube.

[0022] The first end of the second capacitor is connected with the first pole of the first MOS tube, and the second end of the second capacitor is connected with the gate of the second MOS tube.

[0023] a first end of the fifth resistor is connected with the gate of the third MOS tube, and a second end of the fifth resistor is grounded;

[0024] a first end of the third capacitor is connected with the second pole of the first MOS tube, and a second end of the third capacitor is connected with the gate of the third MOS tube.

[0025] Optionally, the second sub-circuit further comprises a fourth MOS tube, a third voltage source and a sixth resistor;

[0026] a gate of the fourth MOS tube is connected with the second pole of the first MOS tube, a first pole of the fourth MOS tube is connected with the second pole of the second MOS tube and the second pole of the third MOS tube, and a second pole of the fourth MOS tube is grounded;

[0027] a positive pole of the third voltage source is connected with the gate of the fourth MOS tube, and a negative pole of the third voltage source is grounded;

[0028] a first end of the sixth resistor is connected with the second pole of the fourth MOS tube, and a second end of the sixth resistor is grounded.

[0029] Optionally, the second sub-circuit further comprises a fourth capacitor and a seventh resistor;

[0030] a first end of the fourth capacitor is connected with the second voltage source, and a second end of the fourth capacitor is grounded;

[0031] a first end of the seventh resistor is connected with the second voltage source, and a second end of the seventh resistor is connected with the first pole of the second MOS tube.

[0032] Optionally, the second sub-circuit further comprises a fifth capacitor and an eighth resistor;

[0033] a first end of the fifth capacitor is connected with the first pole of the third MOS tube, and a second end of the fifth capacitor is grounded;

[0034] a first end of the eighth resistor is connected with the second voltage source, and a second end of the eighth resistor is connected with the first pole of the third MOS tube.

[0035] Optionally, substrates of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are grounded.

[0036] Optionally, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are N-type MOS tubes or P-type MOS tubes.

[0037] Optionally, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are manufactured by the same bipolar complementary metal oxide semiconductor process.

[0038] The utility model discloses a novel balun circuit, include: first subcircuit and second subcircuit, first subcircuit includes first MOS transistor and first voltage source, second subcircuit includes second MOS transistor, third MOS transistor and second voltage source, the gate of first MOS transistor is coupled with signal input end, the first pole of first MOS transistor is connected with the gate of second MOS transistor, the second pole of first MOS transistor is connected with the gate of third MOS transistor, the anode of first voltage source is connected with the gate of first MOS transistor, and the cathode of first voltage source is grounded, the first pole of second MOS transistor is connected with the anode of second voltage source, and the second pole of second MOS transistor is grounded, the first pole of third MOS transistor is connected with the anode of second voltage source, and the second pole of third MOS transistor is grounded, and the cathode of second voltage source is grounded, the radio frequency signal that signal input end receives is transmitted to first MOS transistor and generates difference signal, after difference signal transmission to second MOS transistor, generate first difference signal, after difference signal transmission to third MOS transistor, generate second difference signal, wherein, the amplitude of first difference signal and second difference signal is equal, and the phase is opposite, the utility model provides a novel balun circuit, and the amplification circuit of the second subcircuit is based, when the source impedance of first MOS transistor in first subcircuit is continuously increased, the difference of drain and source impedance of first MOS transistor approaches zero, thereby cleverly using single transistor can realize the circuit design of balun line, and single transistor can pass through the current (including direct current and radio frequency alternating current) of source impedance and drain impedance and is basically same in any case, and it is guaranteed from the structure that two output difference signals are highly matched or even absolutely matched, from the possibility of wideband operation that the line structure provides, make signal conversion more efficient, reliable and excellent performance.

[0039] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the utility model, nor is it used to limit the scope of the utility model. Other features of the utility model will become easy to understand through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical scheme in the embodiments of the utility model, the drawings needed to be used in the embodiment description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained by those skilled in the art without creative labor on the premise of the drawings.

[0041] Figure 1 It is the novel balun circuit design principle diagram provided by the utility model embodiment,

[0042] Figure 2 is a design idea diagram of a novel balun circuit provided by the embodiment of the present application;

[0043] Figure 3 is a balun circuit diagram provided by the embodiment of the present application;

[0044] Figure 4 is a network block diagram of a balun circuit provided by the embodiment of the present application;

[0045] Figure 5 is a time domain simulation waveform diagram of a balun circuit provided by the embodiment of the present application;

[0046] Figure 6 is a gain parameter diagram of a balun circuit provided by the embodiment of the present application;

[0047] Figure 7 is an output signal diagram of a balun circuit provided by the embodiment of the present application;

[0048] Figure 8 is an output signal phase unflatness waveform diagram of a balun circuit provided by the embodiment of the present application;

[0049] Figure 9 is an impedance characteristic curve diagram of a balun circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0051] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 1 This is a schematic diagram of a novel balun circuit design provided by an embodiment of the present invention. The principle of the novel balun circuit provided by an embodiment of the present invention is as follows: Figure 1 As shown, taking MOS transistor M0 as an example, when the source impedance Zs is small, the drain impedance Z d When the value is large, the output signal is not linear enough, but the phase of the output signal is basically opposite to that of the input signal (e.g., Figure 1 As shown in (a) and (b), when the source impedance is continuously increased, the source impedance Z... d and drain impedance Z d The phases of the signal on the drain and the signal on the gate (i.e., the input signal) are approximately equal, meaning their phases are basically opposite and their amplitudes are basically the same (e.g., ...). Figure 1 As shown in (c)).

[0053] That is, utilizing the source impedance Zs and drain impedance Z in a single MOSFET. d Under similar conditions, the principle of equal and opposite output signals at the source and drain allows a balun circuit to be cleverly implemented using a single transistor. Both amplitude and phase are controlled by the source impedance Zs and drain impedance Zs. d The current (including DC and RF AC) is essentially the same under all circumstances, which structurally guarantees a high degree of matching or even absolute matching of the two output differential signals (e.g., Figure 1 (c)) provides the possibility of ultra-wideband operation from the perspective of line construction.

[0054] Figure 2 This is a design concept diagram of a novel balun circuit provided in this embodiment of the present invention, for reference. Figure 2 After passing through the antenna and low noise amplifier (LNA) structure, the radio frequency signal is transmitted to the first MOS transistor (which may be an NMOS transistor) in the novel balun circuit provided in this embodiment of the utility model. The source impedance of the first MOS transistor is set to be similar to the drain impedance, and the signals output from the source and drain are equal in magnitude and out of phase. The signals output from the drain and source flow to the next stage mixer circuit (i.e., the Mixer circuit module) after passing through the source coupling pair (i.e., the second sub-circuit).

[0055] It should be noted that, in the balun circuit, due to the significant degradation effect caused by the source impedance Zs, the signal gain of the balun is limited to a certain extent, therefore, it is necessary to add a buffer amplifier after it, for this purpose, the source coupled pair proposes a complete new type of balun circuit, the source coupled pair is used in the traditional balun structure, but they are essentially different. In the new structure proposed in the scheme, the balun function is realized in the first single transistor, and the source coupled pair only plays an amplification function. In the traditional balun structure, the balun function is completely realized by the two transistors coupled together at the source. After further amplification by the source coupled pair at the back end, the input is transmitted to the next stage.

[0056] Figure 3 It is a balun circuit diagram provided by the embodiment of the utility model, reference Figure 3 The embodiment of the utility model provides a new type of balun circuit (as shown in Figure 3 ), including: first subcircuit A and second subcircuit B;First subcircuit A includes first MOS tube M1 and first voltage source V1;Second subcircuit B includes second MOS tube M2, third MOS tube M3 and second voltage source V2;The gate of first MOS tube M1 is coupled with signal input end PORT1, the first pole of first MOS tube M1 is connected with the gate of second MOS tube M2, the second pole of first MOS tube M1 is connected with the gate of third MOS tube M3, the anode of first voltage source V1 is connected with the gate of first MOS tube M1, and the cathode of first voltage source V1 is grounded;The first pole of second MOS tube M2 is connected with the anode of second voltage source V2, and the second pole of second MOS tube M2 is grounded;The first pole of third MOS tube M3 is connected with the anode of second voltage source V2, and the second pole of third MOS tube M3 is grounded, and the cathode of second voltage source V2 is grounded;The radio frequency signal received by signal input end PORT1 is transmitted to first MOS tube M1 and generates first differential signal and second differential signal;First differential signal is transmitted to second MOS tube M2 and generates first amplified differential signal, and second differential signal is transmitted to third MOS tube M3 and generates second amplified differential signal, wherein the amplitude of first differential signal and second differential signal is equal, and the phase is opposite.

[0057] Specifically, reference Figure 3The utility model embodiment provides a balun circuit which comprises a first subcircuit A and a second subcircuit B, the first subcircuit A comprises a first MOS tube M1 and a first voltage source V1, the gate of the first MOS tube M1 is coupled with a signal input end PORT1, receives the radio frequency signal of the signal input end PORT1, the first pole (can be the drain electrode) of the first MOS tube M1 is connected with the gate of the second MOS tube M2, the second pole (can be the source electrode) of the first MOS tube M1 is connected with the gate of the third MOS tube M3, the anode of the first voltage source V1 is connected with the gate of the first MOS tube M1, and the cathode of the first voltage source V1 is grounded.

[0058] The second subcircuit B comprises a second MOS tube M2, a third MOS tube M3 and a second voltage source V2, the first pole (can be the drain electrode) of the second MOS tube M2 is connected with the anode of the second voltage source V2, the second pole (can be the source electrode) of the second MOS tube M2 is grounded, the first pole (can be the drain electrode) of the third MOS tube M3 is connected with the anode of the second voltage source V2, the second pole (can be the source electrode) of the third MOS tube M3 is grounded, the cathode of the second voltage source V2 is grounded, the second MOS tube M2 and the third MOS tube M3 in the second subcircuit B jointly constitute a differential amplifier circuit, amplify the signal output by the first pole and the second pole of the first MOS tube M1, and simultaneously suppress common-mode signals (the common-mode suppression is relatively high), which can improve the signal-to-noise ratio of the system, make the operation of the balun circuit more stable, the amplification performance is better, and the influence of noise is reduced; the radio frequency signal received by the signal input end PORT1 is transmitted to the first MOS tube M1 and generates a first differential signal and a second differential signal; the first differential signal is transmitted to the second MOS tube M2 and generates a first amplified differential signal, and the second differential signal is transmitted to the third MOS tube M3 and generates a second amplified differential signal, in the utility model embodiment, the radio frequency signal of the signal input end PORT1 has been transmitted to the first MOS tube M1 after being amplified by a low noise amplifier (LNA) in advance, so that the differential amplifier circuit composed of the second MOS tube M2 and the third MOS tube M3 is used for amplifying again (this time is twice amplification) and then outputting into the next mixer circuit (namely, the mixer circuit module).

[0059] The novel balun circuit provided by the embodiment of the utility model is based on the amplification circuit composed of the second sub-circuit, the source impedance of the first MOS tube in the first sub-circuit is continuously increased, the difference between the drain and source impedance of the first MOS tube tends to be zero, thus the circuit design of the balun line can be realized by a single transistor, the current (including direct current and radio frequency alternating current) of the source impedance and the drain impedance of the single transistor is basically the same in any case, the high matching or even absolute matching of the two output differential signals is ensured from the structure, the possibility of ultra-wideband operation is provided from the line structure, and the signal conversion is more efficient, reliable and excellent in performance.

[0060] Figure 4 It is the network block diagram of the balun circuit provided by the embodiment of the utility model, referring to Figure 3 and Figure 4 Optionally, the first sub-circuit A further comprises a first capacitor C1 and a first resistor R1.

[0061] The first end of the first capacitor C1 is connected with the signal input end PORT1, and the second end of the first capacitor C1 is connected with the gate of the first MOS tube M1.

[0062] The first end of the first resistor R1 is connected with the gate of the first MOS tube M1, and the second end of the first resistor R1 is connected with the positive pole of the first voltage source V1.

[0063] Specifically, the first sub-circuit A further comprises the first capacitor C1 and the first resistor R1, the first capacitor C1 and the first resistor R1 constitute an input impedance matching network d, and the input impedance matching network d has the following effects: the optimal noise impedance matching is near 50 ohms, and the impedance matching of the input port is improved. The capacitor can ensure that the direct current voltage is added to the gate of the first MOS tube M1, ensure the work of the transistor, and obtain the maximum gain while ensuring the impedance matching.

[0064] Figure 5 It is the time domain simulation waveform diagram of the balun circuit provided by the embodiment of the utility model, referring to Figure 3 、 4 and 5, optionally, the first sub-circuit A further comprises a second resistor R2 and a third resistor R3.

[0065] The first end of the second resistor R2 is connected with the second pole of the first MOS tube M1, and the second end of the second resistor R2 is grounded.

[0066] The first end of the third resistor R3 is grounded, and the second end of the third resistor R3 is connected with the first pole of the first MOS tube M1, wherein the resistance values of the second resistor R2 and the third resistor R3 are equal.

[0067] Specifically, the second resistor R2 and the third resistor R3 respectively form a source impedance matching network f and a drain impedance matching network e, the second resistor R2 and the third resistor R3 are set to be equal, so as to ensure that the output signals between the source and the drain are equal and opposite, and Figure 5 As shown in the figure, the dashed line is an input signal, and the solid line is a first differential signal and a second differential signal, it can be seen that at a high frequency (5 GHz), the differential signal shows good phase balance and amplitude matching characteristics and an equal and opposite waveform, and the waveform integrity.

[0068] Table 1 is a simulation bandwidth result diagram of the balun circuit provided by the embodiment of the utility model; see Table 1.

[0069]

[0070] Table 1

[0071] Optionally, the second sub-circuit B further comprises a fourth resistor R4, a second capacitor C2, a fifth resistor R5 and a third capacitor C3.

[0072] The first end of the fourth resistor R4 is grounded, and the second end of the fourth resistor R4 is connected with the gate of the second MOS transistor M2.

[0073] The first end of the second capacitor C2 is connected with the first pole of the first MOS transistor M1, and the second end of the second capacitor C2 is connected with the gate of the second MOS transistor M2.

[0074] The first end of the fifth resistor R5 is connected with the gate of the third MOS transistor M3, and the second end of the fifth resistor R5 is grounded.

[0075] The first end of the third capacitor C3 is connected with the second pole of the first MOS transistor M1, and the second end of the third capacitor C3 is connected with the gate of the third MOS transistor M3.

[0076] Specifically, the fourth resistor R4 and the second capacitor C2 form a first-stage interval DC isolation network g, and the fifth resistor R5 and the third capacitor C3 form a second-stage interval DC isolation network h, which not only can isolate the DC signal transmission in the circuit, optimize the signal transmission efficiency, reduce the signal attenuation, but also can ensure that there is no large power loss and signal distortion during signal transmission between different levels. The capacitor can ensure that the DC voltage is added to the gate of the first MOS transistor M1, which ensures the operation of the transistor, and also obtains the maximum gain while ensuring impedance matching.

[0077] Optionally, referring to Figure 3 and Figure 4 , the second sub-circuit B further comprises a fourth MOS transistor M4, a third voltage source V3 and a sixth resistor R6.

[0078] The gate of the fourth MOS transistor M4 is connected with the second pole of the first MOS transistor M1, the first pole of the fourth MOS transistor M4 is commonly connected with the second pole of the second MOS transistor M2 and the second pole of the third MOS transistor M3, and the second pole of the fourth MOS transistor M4 is grounded;

[0079] The positive pole of the third voltage source V3 is connected with the gate of the fourth MOS transistor M4, and the negative pole of the third voltage source V3 is grounded.

[0080] The first end of the sixth resistance R6 is connected with the second pole of the fourth MOS transistor M4, and the second end of the sixth resistance R6 is grounded.

[0081] Specifically, the direct current bias network n is composed of the fourth MOS transistor M4, the third voltage source V3 and the sixth resistance R6, which can provide a suitable direct current working point for the circuit, reduce the influence of the power voltage or temperature variation on the circuit, ensure the working point in a stable state, avoid too large or too small current through the amplifier, and thus avoid saturation distortion and cutoff distortion to the greatest extent.

[0082] Optionally, the second sub-circuit B further comprises a fourth capacitor C4 and a seventh resistance R7.

[0083] The first end of the fourth capacitor C4 is connected with the second voltage source V2, and the second end of the fourth capacitor C4 is grounded.

[0084] The first end of the seventh resistance R7 is connected with the second voltage source V2, and the second end of the seventh resistance R7 is connected with the first pole of the second MOS transistor M2.

[0085] Specifically, the first end of the fourth capacitor C4 is connected with the second voltage source V2, and the second end of the fourth capacitor C4 is connected with the load Load1.

[0086] Optionally, the second sub-circuit B further comprises a fifth capacitor C5 and an eighth resistance R8.

[0087] The first end of the fifth capacitor C5 is connected with the first pole of the third MOS transistor M3, and the second end of the fifth capacitor C5 is grounded.

[0088] The first end of the eighth resistance R8 is connected with the second voltage source V2, and the second end of the eighth resistance R8 is connected with the first pole of the third MOS transistor M3.

[0089] Specifically, the first end of the fifth capacitor C5 is connected with the first pole of the third MOS transistor M3, and the second end of the fifth capacitor C5 is connected with the load Load2.

[0090] The first output matching network j is composed of the fourth capacitor C4 and the seventh resistor R7, and the second output matching network k is composed of the fifth capacitor C5 and the eighth resistor R8, so that the signal can be effectively transmitted.

[0091] Reference Figure 3 and Figure 4 The positive-phase radio frequency signal Rfin passes through the first MOS tube M1, the gate of the first MOS tube M1 is positive, the drain of the first MOS tube is negative, and the source of the first MOS tube is positive, and the positive-phase signal is output on the source of the first MOS tube M1. The first differential signal and the second differential signal pass through the differential amplification circuit composed of the second MOS tube M2 and the third MOS tube M3, at this time, the gate of the second MOS tube M2 is negative, the drain of the second MOS tube is positive, and RFout1 outputs the positive-phase signal, the gate of the third MOS tube M3 is positive, the drain of the third MOS tube M3 is negative, and RFout2 outputs the negative-phase signal.

[0092] Figure 6 is the gain parameter diagram of the balun circuit provided by the embodiment of the utility model, reference Figure 6 , wherein, the red line is S21 gain parameter, the yellow line is S31 gain parameter, and it can be seen that under 40GHZ, good gain characteristics are shown (since the balun has power division function, 0dB here actually corresponds to the gain of passive balun+3dB).

[0093] Figure 7 is the output signal diagram of the balun circuit provided by the embodiment of the utility model, reference Figure 7 , it can be seen that under less than 36GHZ, the amplitude imbalance is below 0.5dB, and good amplitude balance degree is shown under the ultra-high bandwidth.

[0094] Figure 8 is the output signal phase imbalance waveform diagram of the balun circuit provided by the embodiment of the utility model, reference Figure 8 , it can be seen that within 50GHZ, the phase difference is within 5°, and good phase balance characteristics are shown.

[0095] Figure 9 is the impedance characteristic curve diagram of the balun circuit provided by the embodiment of the utility model, reference Figure 9 , it can be seen that the return loss S11 (such as Figure 9 red line in the middle), S22 (such as Figure 9 yellow line in the middle), S33 (such as Figure 9The input impedance and the output impedance of the novel balun circuit are all below -10dB, and good input / output impedance matching is achieved.

[0096] Optionally, the substrates of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are grounded. Figure 3

[0097] Specifically, the substrates of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are grounded, which can prevent current leakage, eliminate substrate bias effect and improve working stability.

[0098] Optionally, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are N-type MOS transistors or P-type MOS transistors.

[0099] Optionally, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are manufactured by the same bipolar complementary metal oxide semiconductor process.

[0100] Specifically, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are manufactured based on a 45nm bipolar complementary metal oxide semiconductor (BiCMOS) process technology, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are all in a common-source amplification state, an alternating current signal is input through the signal input end PORT1, and the resistance is 50 ohms.

[0101] The novel balun circuit provided in the embodiment of the utility model can realize the following technical effects:

[0102] 1. Innovative design idea: by fully understanding signal characteristics and circuit principles, an innovative circuit topology structure is proposed, so that signal conversion is more efficient, reliable and excellent in performance.

[0103] 2. High integration: the active integrated circuit is used to realize the balun function, and high integration is emphasized, so that the balun circuit can be integrated to the chip level, and the size of the circuit is much smaller than that of the passive balun.

[0104] 3. Excellent performance: through strict simulation verification, it is proved that the novel balun circuit has good performance in signal conversion, impedance matching and gain, especially in bandwidth, and it shows the potential of ultra-wideband application.

[0105] ​The specific embodiments described above do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A novel balun circuit, characterized by, The application relates to a circuit for generating differential signals. The circuit comprises a first sub-circuit and a second sub-circuit; the first sub-circuit comprises a first MOS transistor and a first voltage source; the second sub-circuit comprises a second MOS transistor, a third MOS transistor and a second voltage source. The gate of the first MOS transistor is coupled to a signal input end; the first pole of the first MOS transistor is connected to the gate of the second MOS transistor; the second pole of the first MOS transistor is connected to the gate of the third MOS transistor; the positive pole of the first voltage source is connected to the gate of the first MOS transistor; and the negative pole of the first voltage source is grounded. The first pole of the second MOS transistor is connected to the positive pole of the second voltage source; the second pole of the second MOS transistor is grounded; the first pole of the third MOS transistor is connected to the positive pole of the second voltage source; the second pole of the third MOS transistor is grounded; and the negative pole of the second voltage source is grounded. The radio frequency signal received by the signal input end is transmitted to the first MOS transistor and generates a first differential signal and a second differential signal. The first differential signal is transmitted to the second MOS transistor and generates a first amplified differential signal; the second differential signal is transmitted to the third MOS transistor and generates a second amplified differential signal; the amplitudes of the first differential signal and the second differential signal are equal; and the phases of the first differential signal and the second differential signal are opposite.

2. The novel balun circuit according to claim 1, characterized by The first sub-circuit further comprises a first capacitor and a first resistor. The first end of the first capacitor is connected to the signal input end; and the second end of the first capacitor is connected to the gate of the first MOS transistor. The first end of the first resistor is connected to the gate of the first MOS transistor; and the second end of the first resistor is connected to the positive pole of the first voltage source.

3. The novel balun circuit according to claim 2, characterized by The first sub-circuit further comprises a second resistor and a third resistor. The first end of the second resistor is connected to the second pole of the first MOS transistor; and the second end of the second resistor is grounded. The first end of the third resistor is grounded; and the second end of the third resistor is connected to the first pole of the first MOS transistor; wherein the resistance values of the second resistor and the third resistor are equal.

4. The novel balun circuit according to claim 1, characterized by The second sub-circuit further comprises a fourth resistor, a second capacitor, a fifth resistor and a third capacitor. The first end of the fourth resistor is grounded; and the second end of the fourth resistor is connected to the gate of the second MOS transistor. The first end of the second capacitor is connected to the first pole of the first MOS transistor; and the second end of the second capacitor is connected to the gate of the second MOS transistor. The first end of the fifth resistor is connected to the gate of the third MOS transistor; and the second end of the fifth resistor is grounded. The first end of the third capacitor is connected to the second pole of the first MOS transistor; and the second end of the third capacitor is connected to the gate of the third MOS transistor.

5. The novel balun circuit according to claim 4, characterized by The second sub-circuit further comprises a fourth MOS transistor, a third voltage source and a sixth resistor. The gate of the fourth MOS transistor is connected to the second pole of the first MOS transistor; the first pole of the fourth MOS transistor is connected to the second pole of the second MOS transistor and the second pole of the third MOS transistor; and the second pole of the fourth MOS transistor is grounded. A positive pole of the third voltage source is connected with a gate of the fourth MOS tube, and a negative pole of the third voltage source is grounded. A first end of the sixth resistor is connected with a second pole of the fourth MOS tube, and a second end of the sixth resistor is grounded.

6. The novel balun circuit according to claim 1, characterized by The second sub-circuit further comprises a fourth capacitor and a seventh resistor; A first end of the fourth capacitor is connected with the second voltage source, and a second end of the fourth capacitor is grounded. A first end of the seventh resistor is connected with the second voltage source, and a second end of the seventh resistor is connected with a first pole of the second MOS tube.

7. The novel balun circuit according to claim 6, characterized by The second sub-circuit further comprises a fifth capacitor and an eighth resistor; A first end of the fifth capacitor is connected with a first pole of the third MOS tube, and a second end of the fifth capacitor is grounded. A first end of the eighth resistor is connected with the second voltage source, and a second end of the eighth resistor is connected with the first pole of the third MOS tube.

8. The novel balun circuit according to claim 5, characterized by Substrates of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are grounded.

9. The novel balun circuit according to claim 5, characterized by The first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are N-type MOS tubes or P-type MOS tubes.

10. The novel balun circuit according to claim 5, characterized by The first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are manufactured by the same bipolar complementary metal oxide semiconductor process.

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