Step-shaped groove Schottky barrier diode with heat dissipation channel in groove

Abstract

The utility model discloses a step-shaped groove Schottky barrier diode with a heat dissipation channel in a groove. Heat dissipation channels are arranged in a groove in the diode and are continuously distributed in the cross section of an epitaxial layer to form communicated snakelike arrangement; the openings of the grooves on the vertical surface of the surface of the epitaxial layer are designed in a segmented manner, the overall structure is of a stepped structure with a small upper part and a large lower part, the small openings at the upper part reduce the chip area occupied by a non-conductive structure, and the conductive semiconductor area during forward conduction is increased; the lower opening is large, so that the point discharge effect possibly deteriorated due to small curvature radius of the bottom of the groove when the device is reversely biased is avoided; meanwhile, the segmented design is favorable for forming continuously distributed holes in the conductive polycrystalline silicon filled in the communicated snakelike grooves, and cooling liquid or gas is introduced into the continuous holes to form a heat dissipation channel, so that the heat dissipation capability of the chip is enhanced, the junction temperature of the chip during working is reduced, and the working power and reliability of the chip are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor device, especially to a trench Schottky barrier diode of semiconductor discrete device. BACKGROUND

[0002] Rectifier devices are required to have unidirectional conduction characteristics, i.e. low forward turn-on voltage and low forward conduction resistance, and high reverse blocking voltage and low reverse leakage current. Schottky barrier diodes have been used as rectifier devices for decades in power supply applications. They are very suitable for use in switching power supplies and high frequency applications due to their low forward turn-on voltage and fast switching speed.

[0003] Schottky barrier diodes are made using the principle of metal-semiconductor junctions formed by the contact between metal and semiconductor. Conventional planar Schottky barrier diode devices are generally composed of a low-doped N － epitaxial layer and a metal layer deposited on the top surface to form a Schottky barrier contact. The difference between the work functions of the metal and the N-type monocrystalline silicon forms the barrier, and the height of the barrier determines the characteristics of the Schottky barrier diode. A lower barrier can reduce the forward turn-on voltage, but will increase the reverse leakage current and reduce the reverse blocking voltage. Conversely, a higher barrier will increase the forward turn-on voltage, while reducing the reverse leakage current and enhancing the reverse blocking capability. However, conventional planar Schottky barrier diodes generally have high reverse leakage current and low reverse blocking voltage. In view of the above problems, trench Schottky barrier diodes have been invented, which have low forward turn-on voltage and overcome the shortcomings of the above-mentioned planar Schottky diodes.

[0004] The trench Schottky barrier diode has the remarkable feature that a number of trenches extending into the N － epitaxial layer are present in the N － epitaxial layer, an oxide layer covering the surface of the trenches, and a conductive material filling the trenches. For example, US Patent No. 5,365,102 discloses a trench Schottky barrier diode, in which the device structure of one embodiment is shown in the attached Figure 1 diagram. This is a commonly used trench Schottky barrier diode structure in the prior art. As can be seen from the diagram, the silicon wafer used to make the diode is composed of a highly doped N + substrate 301 and a lower-doped N － epitaxial layer 302, a series of trenches 303 are prepared in the N － epitaxial layer 302, the N-type monocrystalline silicon mesa structure 304 between the trenches 303, a silicon dioxide layer 305 grown on the sidewalls of the trenches 303, and a metal layer 306 covering the upper surface of the entire structure and contacting the top surface of the N-type monocrystalline silicon mesa structure 304 to form a Schottky barrier contact; and the N +A cathode metal layer 307 is deposited on the bottom surface of the substrate 301. Due to the existence of the composite structure of the trench 303, the silicon dioxide layer 305 and the conductive material 306 in the trench, the electric field distribution is changed when the device is reversely biased, the electric field intensity at the bottom region of the trench is peaked, the free carriers in the mesa structure 304 are completely depleted, and the electric field intensity reaching the Schottky barrier is reduced, thereby enhancing the voltage reverse blocking capability of the device and reducing the reverse leakage current.

[0005] However, the trench Schottky barrier diode structure in the prior art still has some problems, and the main problems exposed include: 1) when forward conducting, the area of the trench structure cannot conduct current, causing current crowding in the semiconductor of the mesa, so that the forward conducting voltage drop of the trench Schottky diode is large; 2) when reversely biased, the electric field intensity at the bottom region of the trench is maximum, the curvature radius of the bottom structure is small, or the thickness of the oxide layer at the bottom of the trench is thin or uneven due to the limitation of the step coverage capability, which can all cause uneven electric field intensity distribution and excessively high local electric field intensity; resulting in the decrease of the reverse voltage drop blocking capability of the device, and the decrease of the reliability and service life of the device; 3) when reversely biased, complete depletion in the mesa is required to obtain the required reverse leakage current and the reliability and service life of the device.

[0006] As can be seen from the above, the existing trench Schottky barrier diode structure still has certain defects, and the performance needs to be further optimized, the reliability of the device needs to be improved, and the manufacturing method of the device needs to be simplified to reduce the cost. SUMMARY

[0007] In view of the defects of the prior art, the purpose of the present application is to provide a stepped trench Schottky barrier diode with a heat dissipation channel in the trench, which aims to improve the above-mentioned deficiencies of the existing trench Schottky barrier diode, and improve the performance and reliability of the device by improving the heat dissipation of the trench Schottky barrier diode.

[0008] To achieve the above-mentioned purpose, the present application adopts the following technical solutions.

[0009] The present application provides a stepped trench Schottky barrier diode with a heat dissipation channel in the trench, comprising:

[0010] A first conductive type heavily doped semiconductor substrate;

[0011] A first conductive type lightly doped semiconductor epitaxial layer located on the upper surface of the substrate;

[0012] A trench located in the epitaxial layer and opening on the upper surface of the epitaxial layer and extending into the epitaxial layer, and the trench is a continuous distribution of serpentine openings in the same cross section of the epitaxial layer; wherein the epitaxial layer region outside the extension region of the trench forms a mesa structure;

[0013] a first conductive type heavily doped conductive polysilicon filled in the trench; the conductive polysilicon contains a continuous cavity extending along the same direction as the lateral direction of the trench; during the operation of the Schottky barrier diode in the trench, cooling gas or liquid is introduced into the continuous cavity for heat dissipation of the diode and reduction of the junction temperature during chip operation; the continuous cavity for introducing cooling gas or liquid is the heat dissipation channel;

[0014] a first isolation medium layer covering the inner wall of the trench and separating the conductive polysilicon and the epitaxial layer;

[0015] a Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region;

[0016] an ohmic contact metal layer covering the upper surface of the conductive polysilicon;

[0017] a second isolation medium layer formed by upward extension of the first isolation medium layer and separating the Schottky barrier metal layer and the ohmic contact metal layer;

[0018] an anode metal layer covering the upper surface of the Schottky barrier diode;

[0019] and a cathode metal layer located on the lower surface of the substrate, which forms an ohmic contact with the cathode metal layer.

[0020] Further, the epitaxial layer region at the bottom of the trench has a second conductive type ion implantation region.

[0021] In an embodiment of the present application, the trench has a stepped structure with a small upper lateral opening and a large lower lateral opening, and the upper and lower openings are connected, in the vertical direction of the upper surface of the epitaxial layer (hereinafter referred to as "vertical plane" for simplicity). In this embodiment, the first isolation medium layer formed on the inner wall of the upper and lower openings of the trench has a uniform thickness. In this embodiment, during the manufacturing process, after the formation of the isolation medium layer, the conductive polysilicon is filled in the trench. At this time, the trench still has a structure with a larger lower opening than upper opening in the vertical plane, and a continuous cavity extending along the lateral direction of the trench is formed in the conductive polysilicon during filling, thereby achieving the purpose of providing a heat dissipation channel in the trench.

[0022] Further, in the above embodiment, the lateral opening size of the upper opening of the trench is 0.1-0.5 microns, and the lateral opening size of the lower opening of the trench is 0.2-2 microns, and the lateral opening size of the lower opening is larger than that of the upper opening, and the difference between the two is greater than or equal to 0.1 microns.

[0023] Further, in the above embodiment, the first isolation medium layer has a thickness of 0.05-0.25 microns.

[0024] In another embodiment of the present application, the trench has a transverse opening size in three sections, upper, middle and lower, with a step formed between the two adjacent sections. In this embodiment, the transverse opening size of the lower section is greater than that of the upper section, and the transverse opening size of the upper section is greater than that of the middle section.

[0025] Further, in the above embodiment, the transverse opening size of the upper section of the trench is 0.15-1.2 microns, the transverse opening size of the middle section of the trench is 0.1-0.6 microns, the transverse opening size of the lower section of the trench is 0.2-2 microns, the transverse opening size of the lower section of the trench is greater than that of the middle section, and the difference between the two is greater than or equal to 0.1 microns, and the transverse opening size of the upper section of the trench is greater than that of the middle section, and the difference between the two is greater than or equal to 0.01 microns.

[0026] Further, in the above embodiment, the first isolation medium layer is composed of a first upper isolation medium layer, a first middle isolation medium layer and a first lower isolation medium layer, wherein the first lower isolation medium layer covers the inner wall of the lower section of the trench, the first upper isolation medium layer covers the side wall of the upper section of the trench, and the first middle isolation medium layer covers the inner wall of the middle section of the trench. Further, the thickness of the first middle isolation medium layer is the smallest among the first upper isolation medium layer and the first lower isolation medium layer. Further, the thickness of the first upper isolation medium layer and the first lower isolation medium layer is uniform.

[0027] Further, in the above embodiment, the thickness of the first middle isolation medium layer is 0.05-0.15 microns, the thickness of the first upper isolation medium layer and the first lower isolation medium layer is 0.1-0.6 microns, and the thickness of the first middle isolation medium layer is at least 0.01 microns smaller than that of the other two first isolation medium layers.

[0028] In another embodiment, the formation of the heat dissipation channel in the Schottky barrier diode can be achieved during the manufacturing process after the formation of the isolation medium layer, by filling the conductive polysilicon in the trench, due to the three-stage design of the trench lateral opening size as described above, and the different settings of the segmented thickness of the first isolation medium layer, at this time, the trench to be filled area still presents the state of the lower opening being larger than the upper opening in the vertical plane, and a continuous cavity along the lateral direction of the trench will be formed in the conductive polysilicon filling process, thereby achieving the purpose of the structure of the heat dissipation channel in the trench of the present application.

[0029] Further, the isolation medium layer is an oxide layer.

[0030] Further, the first conductive type is N type, and the second conductive type is P type.

[0031] The beneficial effects of the present application are as follows:

[0032] Due to the use of the above technical scheme, the present application has the following advantages and technical effects compared with the prior art:

[0033] 1) The continuously arranged trenches in the diode present a stepped structure design with the upper opening being smaller than the lower opening in the overall structure, the lateral opening size above the trench is smaller than the lateral opening size below the trench in the overall structure, the area of the non-conductive structure is reduced, the area of the conductive semiconductor during forward conduction is increased, the current density during forward conduction is reduced, the forward conduction voltage drop is reduced, the junction temperature during forward conduction is reduced, and the forward conduction performance, device reliability and service life of the device are improved.

[0034] 2) The lateral opening size below the trench is large, which avoids the possible deterioration of the sharp tip discharge effect of the trench bottom due to the small curvature radius during reverse bias of the device, thereby improving the reverse blocking performance, device reliability and service life of the device.

[0035] 3) In one of the schemes, the isolation medium layer in the trench is three-section type, the upper, middle and lower three sections have different thicknesses, and the partition adjuster adjusts the forward and reverse performance of the device. Since the isolation medium layer covering the inner wall of the lowermost part of the trench is relatively thick, the pressure drop borne by the isolation medium layer increases when reverse bias is applied, thereby improving the reverse blocking capability of the device. The isolation medium layer covering the inner wall of the middle part of the trench is relatively thin, which is beneficial to the formation of a depletion pinch in the epitaxial layer of the mesa when reverse bias is applied, thereby improving the reverse blocking performance, reliability and service life of the device. The isolation medium layer covering the uppermost part of the side wall of the trench is relatively thick, and a small amount of polysilicon can be used to fill the cylindrical hole, thereby reducing the manufacturing period and cost of the device. Moreover, the relatively thick isolation medium layer on the upper part can increase the distance between the conductive polysilicon on the upper surface of the device and the epitaxial layer, weaken the diffusion of the doped impurities in the conductive polysilicon to the epitaxial layer through the Schottky barrier metal in the process of forming the Schottky barrier alloy, and improve the leakage current, reliability and service life of the device when reverse blocking.

[0036] 4) The trenches in the diode are continuously distributed to form a connected snake-shaped arrangement, and a continuously distributed hollow structure is formed in the conductive polysilicon filled in the trenches. The hollow structure is used to pass cooling liquid or gas to form a heat dissipation channel, thereby enhancing the heat dissipation capability of the chip, reducing the junction temperature of the chip when the chip is working, and improving the working power, reliability and other benefits of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a schematic diagram of the structure of a trench Schottky barrier diode disclosed in US 5,365,102, which is also a commonly used trench Schottky barrier diode in the prior art.

[0038] wherein, Figure 1 N-type substrate, 301 is N + epitaxial layer, 302 is N － epitaxial layer, 303 is a trench, 304 is an N-type single crystal silicon mesa structure, 305 is a silicon dioxide layer, 306 is a metal layer, and 307 is a cathode metal layer.

[0039] Figure 2 is a schematic diagram of the top view structure of a Schottky barrier diode with a heat dissipation channel in the trench according to an embodiment of the present application.

[0040] Figure 3 is a schematic diagram of the cross-sectional structure of the Schottky barrier diode according to Embodiment 1 of the present application at the A1-A2 position. Figure 2

[0041] Figure 4 is a schematic diagram of the cross-sectional structure of the device formed after step S4 in Embodiment 1 of the present application.

[0042] Figure 5 ​is a cross-sectional schematic view of the device structure formed after step S8 in embodiment 1 of the utility model.

[0043] Figure 6 is a cross-sectional schematic view of the device structure formed after step S11 in embodiment 1 of the utility model.

[0044] Figure 7 is a cross-sectional schematic view of the device structure formed after step S13 in embodiment 1 of the utility model.

[0045] Figure 8 is a cross-sectional schematic view of the Schottky barrier diode in embodiment 2 of the utility model at A1-A2 position. Figure 2

[0046] wherein, Figures 2-8 in the figure: 10 is a cathode metal layer, 20 is a first conductive type heavily doped substrate, 30 is a first conductive type lightly doped epitaxial layer, 30a is a mesa structure, 31 is a groove, 31a is an upper opening of the groove, 31b is a lower opening of the groove, 31d is a middle opening of the groove, 32 is a conductive polysilicon, 33 is an isolation oxide layer, 33a is a first upper isolation dielectric layer, 33d is a first middle isolation dielectric layer, 33b is a first lower isolation dielectric layer, 33c is a second isolation dielectric layer, 34 is a continuous cavity, 35 is an ion implantation region, 35a is a second conductive type doped impurity, 40 is a functional metal layer, 40a is a Schottky barrier metal layer, 40b is an ohmic contact metal layer, 50 is an anode metal layer; 61 is a first dielectric layer, and 62 is a second dielectric layer. d1 is a transverse opening size of the upper opening 31a of the groove, d2 is a transverse opening size of the lower opening 31b of the groove, and d3 is a transverse opening size of the middle opening 31b of the groove. DETAILED DESCRIPTION

[0047] In order to more clearly illustrate the technical scheme of the utility model and the purpose of the invention, the utility model will be further described in detail below in combination with the drawings and specific embodiments.

[0048] As Figure 2 is a top view structural schematic diagram of a Schottky barrier diode with a heat dissipation channel in a groove made according to each embodiment of the utility model, and from the figure, it can be seen that the groove of the Schottky barrier diode is in a continuous distributed snake shape in the same cross section of the epitaxial layer. The snake distributed shape is only one of the distributed shapes of the groove of the utility model, and the distributed shape of the groove of the utility model can form a continuous distribution in the same cross section of the epitaxial layer to achieve the purpose of the utility model, including, for example, Figure 2 distributed shapes but does not limit it to be the shape, and changes and modifications similar in nature to the shape still belong to the protection range of the technical scheme of the utility model. ​

[0049] Example 1

[0050] This embodiment provides a Schottky barrier diode with a heat dissipation channel within the trench. The Schottky barrier diode has a heat dissipation channel within the trench. Figure 2 A partial schematic diagram of the cross-sectional structure at position A1-A2 is shown below. Figure 3 As shown. From Figures 2-3 As can be seen, the Schottky barrier diode of this invention comprises, from bottom to top, a cathode metal layer 10, a heavily doped substrate 20 of the first conductivity type of semiconductor, a lightly doped epitaxial layer 30 of the first conductivity type of semiconductor, a functional metal layer 40, and an anode metal layer 50 covering the top layer of the entire Schottky barrier diode structure; it also includes continuously distributed serpentine trenches 31 located in the epitaxial layer 30, the trenches 31 opening on the upper surface of the epitaxial layer 30 and extending into the epitaxial layer 30, and the trenches 31 having a stepped shape on the vertical plane of the epitaxial layer surface. Figure 3 As can be seen, the step of the groove 31 on the vertical plane is formed by the connection of the upper opening 31a and the lower opening 31b of the groove, and the lateral opening size of the upper opening 31a (e.g.) Figure 3 The lateral opening size of the middle d1 is smaller than that of the lower opening 31b (e.g., Figure 3 In the trench d2), a first conductivity type heavily doped conductive polysilicon 32 is filled in the trench. An isolation oxide layer 33 is covered on the inner wall of the stepped trench 31 as a first isolation dielectric layer to isolate the conductive polysilicon 32 and the epitaxial layer that constitutes the inner wall of the trench. Inside the conductive polysilicon 32 located in the lower opening of the trench, there is a cavity that extends continuously in the same direction as the lateral extension direction of the trench. This continuous cavity 34 serves as a heat dissipation channel when the diode chip is working. In the epitaxial layer near the bottom of the trench 31, there is a second conductivity type ion implantation region 35. In this structure, the epitaxial layer region outside the trench extension region forms a mesa structure 30a, and the functional metal layer 40 covering the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier metal layer 40a with the epitaxial layer; while the functional metal layer 40 covering the upper surface of the conductive polysilicon 32 is an ohmic contact metal layer 40b that forms an ohmic contact with the heavily doped conductive polysilicon; the isolation oxide layer 33 extends upward between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b, forming a second isolation dielectric layer to isolate the two.

[0051] In this invention, the inventors fabricated the Schottky barrier diode with a heat dissipation channel within the trench provided in this embodiment using the following method. In this embodiment, a heavily doped substrate of N₂ is selected. + Single-crystal silicon wafer, with the epitaxial layer grown on N-type silicon. + Lightly doped N on a single-crystal silicon wafer -The silicon epitaxial layer, the ion implantation region is a P-type ion implantation region, and the silicon oxide layer is used as an isolation oxide layer. The upper opening of the trench has a lateral opening size of 0.25 microns, the lower opening has a lateral opening size of 0.5 microns, and the isolation oxide layer has a thickness of 0.1 microns.

[0052] The specific manufacturing process is as follows:

[0053] S1. Prepare a semiconductor first-conductivity-type heavily doped substrate N + Monocrystalline silicon wafer, grow a first-conductivity-type lightly doped epitaxial layer N on the substrate 20 - Silicon epitaxial layer 30.

[0054] S2. Form a first dielectric layer 61 on the upper surface of the epitaxial layer, perform photolithography on the first dielectric layer to define the upper opening 31a pattern of the trench, selectively remove the first dielectric layer not protected by the photoresist to expose the epitaxial layer corresponding to the upper opening pattern, and then remove the photoresist on the first dielectric layer; use the first dielectric layer remaining after the photoresist is removed as a first dielectric hard mask.

[0055] S3. Use the first dielectric hard mask as protection, and selectively etch the exposed epitaxial layer 30 using a dry etching method to form the upper opening 31a in the trench 31 in the epitaxial layer, thereby forming a mesa structure 30a in the epitaxial layer outside the upper opening. At this time, the upper surface of the mesa structure 30a is still covered with the first dielectric hard mask.

[0056] S4. Form a second dielectric layer 62 on the entire structure surface formed after step S3, and obtain a structure cross-sectional view as shown in Figure 4 .

[0057] S5. Selectively etch the second dielectric layer 62 using a dry etching method to expose the epitaxial layer at the bottom of the upper opening 31a, and at the same time, the second dielectric layer 62 above the first dielectric layer 61 is also removed synchronously; at this time, the upper surface of the mesa structure 30a is still covered with the first dielectric layer 61, i.e., the first dielectric hard mask, and at this time, the second dielectric layer 62 covering the sidewall of the upper opening 31a is used as a second dielectric hard mask.

[0058] S6. Use the first dielectric hard mask and the second dielectric hard mask as protection, and selectively etch the exposed epitaxial layer using a dry etching method.

[0059] S7. Continue to use the first dielectric hard mask and the second dielectric hard mask as protection, and selectively etch the exposed epitaxial layer using a xenon difluoride dry etching method to form the lower opening 31b of the trench 31, wherein the lateral size of the opening is larger than the lateral opening size of the upper opening formed in step S3.

[0060] S8. Continue to protect with the first dielectric hard mask and the second dielectric hard mask, and implant the second conductive type doping impurities 35a into the exposed epitaxial layer by ion implantation. At this time, the structure cross-sectional view is as shown in Fig. 8. Figure 5

[0061] S9. Remove the second dielectric layer 62 and the first dielectric layer 61 by wet etching.

[0062] S10. Grow the isolation oxide layer 33 on the surface of the entire structure formed after step S9. At this time, the isolation oxide layer grown on the inner wall of the trench constitutes the first isolation dielectric layer. Meanwhile, the second conductive type doping impurities 35a are diffused to form the ion implantation region 35 during the heat process of the growth of the isolation oxide layer.

[0063] S11. Deposit the conductive polysilicon 32 on the surface of the entire structure formed after step S10. Then, remove the conductive polysilicon outside the trench by dry etching, and make the upper surface of the conductive polysilicon 32 filled in the trench flush with the upper surface of the epitaxial layer of the mesa structure 30a. Due to the fact that the lateral opening size of the lower opening of the trench is larger than that of the upper opening, a continuous cavity 34 will be formed in the conductive polysilicon inside the lower opening during the deposition of the polysilicon. At this time, the structure cross-sectional view is as shown in Fig. 11. Figure 6

[0064] S12. Remove the isolation oxide layer on the surface of the mesa structure 30a by dry etching, and retain the isolation oxide layer extending upward from the first isolation dielectric layer and surrounding the upper opening of the trench, i.e. retain the isolation oxide layer 33 constituting the second isolation dielectric layer, for isolating the Schottky barrier metal layer and the ohmic contact metal layer to be formed in the following steps.

[0065] S13. Deposit a metal layer on the surface of the entire structure formed after step S12. After alloying, the metal layer forms the functional metal layer 40. The part of the functional metal layer 40 in contact with the upper surface of the epitaxial layer of the mesa structure 30a forms the Schottky barrier metal layer 40a, and the part of the functional metal layer 40 in contact with the upper surface of the conductive polysilicon filled in the trench forms the ohmic contact metal layer 40b. At this time, the structure cross-sectional view is as shown in Fig. 13. Figure 7

[0066] S14. Deposit the anode metal layer 50 on the surface of the entire structure formed after step S13.

[0067] ​​​S15. The substrate is thinned by a method of grinding and etching the lower surface of the substrate, and then a cathode metal layer 10 is deposited on the lower surface of the substrate. The fabrication of the Schottky barrier diode with heat dissipation channels in the trench of the embodiment is completed, and the overall structure of the diode is shown in Figure 2 the top view and Figure 3 the cross-sectional schematic view in .

[0068] Embodiment 2

[0069] The Schottky barrier diode with heat dissipation channels in the trench provided by the embodiment has a top view as shown in Figure 2 , and a partial schematic view of the cross-sectional structure at the positions of A1-A2 in the figure is shown in Figure 8 . As can be seen from Figure 2 and Figure 8 , the Schottky barrier diode of the embodiment includes, from bottom to top, a cathode metal layer 10, a semiconductor first-conductivity-type heavily doped substrate 20, a semiconductor first-conductivity-type lightly doped epitaxial layer 30, a functional metal layer 40, and an anode metal layer 50 covering the top layer of the overall Schottky barrier diode structure; and further includes a continuously distributed serpentine trench 31 in the epitaxial layer 30, the trench 31 is open on the upper surface of the epitaxial layer 30 and extends into the epitaxial layer 30, and the trench 31 is in step shape on the vertical surface of the epitaxial layer surface. As can be seen from Figure 8 , the step of the trench 31 on the vertical surface is composed of the upper opening 31a and the middle opening 31d of the trench, and the middle opening 31d and the lower opening 31b are connected, wherein the transverse opening size of the middle opening 31d is smaller than the transverse opening sizes of the upper opening 31a and the lower opening 31b, and the transverse opening size of the lower opening is the largest. In the embodiment, as shown in Figure 8 , d1 is the transverse opening size of the upper opening 31a, the transverse opening size of the lower opening 31b is d2 as shown in Figure 8 , and the transverse opening size of the middle opening 31b is d3 as shown in Figure 8d3, and d2>d1>d3. The trench is filled with a first conductive type heavily doped conductive polysilicon 32. The inner wall of the trench 31 is covered with an oxide layer as a first middle isolation medium layer 33d, a first upper isolation medium layer 33a and a first lower isolation medium layer 33b, which are used to isolate the conductive polysilicon 32 and the epitaxial layer constituting the inner wall of the trench, wherein the first lower isolation medium layer 33b covers the inner wall of the lower opening 31b of the trench, the first middle isolation medium layer 33d covers the inner wall of the middle opening 31d of the trench, and the first upper isolation medium layer 33a covers the sidewall of the upper opening 31a of the trench. The conductive polysilicon 32 in the lower opening of the trench contains a continuous cavity extending in the same direction as the lateral extension direction of the trench, which is a heat dissipation channel when the diode chip is working. In the epitaxial layer near the bottom of the trench 31, there is a second conductive type ion implantation region 35. The epitaxial layer area outside the extension area of the trench forms a mesa structure 30a. The functional metal layer 40 covering the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier metal layer 40a in Schottky barrier contact with the epitaxial layer. The functional metal layer 40 covering the upper surface of the conductive polysilicon 32 forms an ohmic contact metal layer 40b in ohmic contact with the heavily doped conductive polysilicon. The isolation oxide layer 33 extends upward between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b to form a second isolation medium layer 33c for isolating the two.

[0070] The manufacturing process of the Schottky barrier diode with a heat dissipation channel in the trench provided by the embodiment will not be described here. Those skilled in the art can think of how to realize the manufacturing of the Schottky barrier diode of the embodiment through existing chip manufacturing technology after seeing the structural diagram of the embodiment. Figure 2 and Figure 8 The manufacturing process of the Schottky barrier diode with a heat dissipation channel in the trench provided by the embodiment will not be described here. Those skilled in the art can think of how to realize the manufacturing of the Schottky barrier diode of the embodiment through existing chip manufacturing technology after seeing the structural diagram of the embodiment.

[0071] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any skilled person in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application, and achieve the above effects. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solution of the present application, still belongs to the scope of protection of the technical solution of the present application.

Claims

1. A stepped trench Schottky barrier diode having heat dissipation channels in the trench, characterized by, The trench Schottky barrier diode comprises: a semiconductor substrate of a first conductivity type and heavy doping; a semiconductor epitaxial layer of a first conductivity type and light doping on the upper surface of the substrate; a trench in the epitaxial layer, opening on the upper surface of the epitaxial layer and extending into the epitaxial layer, and the trench is a continuous and serpentine opening in the same cross section of the epitaxial layer, and the opening of the trench on the vertical surface of the upper surface of the epitaxial layer presents a stepped structure; wherein the epitaxial layer region outside the extension region of the trench forms a mesa structure; a conductive polysilicon of a first conductivity type and heavy doping filled in the trench; a continuous cavity in the conductive polysilicon extending in the same direction as the lateral extension direction of the trench; when the trench Schottky barrier diode is working, cooling gas or liquid is introduced into the continuous cavity for heat dissipation and reducing the junction temperature during chip working, and the continuous cavity is the heat dissipation channel; a first isolation medium layer covering the inner wall of the trench and separating the conductive polysilicon and the epitaxial layer; a Schottky barrier metal layer covering the upper surface of the mesa structure region of the epitaxial layer; an ohmic contact metal layer covering the upper surface of the conductive polysilicon; a second isolation medium layer extending upward from the first isolation medium layer and separating the Schottky barrier metal layer and the ohmic contact metal layer; an anode metal layer covering the upper surface of the Schottky barrier diode; and a cathode metal layer on the lower surface of the substrate, and the lower surface of the substrate forms an ohmic contact with the cathode metal layer.

2. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 1, wherein, The trench Schottky barrier diode further comprises a second conductivity type ion implantation region in the epitaxial layer region at the bottom of the trench.

3. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 1, wherein: The trench presents a stepped structure with a small lateral opening size of the upper opening and a large lateral opening size of the lower opening on the vertical surface of the upper surface of the epitaxial layer, and the upper opening and the lower opening are connected.

4. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 3, characterized in that: The first isolation medium layer has a uniform thickness formed on the inner wall of the upper opening and the lower opening of the trench.

5. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 3, wherein: The lateral opening size of the upper opening of the trench is 0.1-0.5 microns, and the lateral opening size of the lower opening of the trench is 0.2-2 microns, and the lateral opening size of the lower opening is larger than that of the upper opening, and the difference between them is greater than or equal to 0.1 micron.

6. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 5, wherein: The thickness of the first isolation medium layer is 0.05-0.25 microns.

7. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 1, wherein: The lateral opening size of the trench presents a three-section structure on the vertical surface of the upper surface of the epitaxial layer, and a stepped structure is formed between two adjacent sections; and the lateral opening size of the lower opening > the lateral opening size of the upper opening > the lateral opening size of the middle opening.

8. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 7, wherein: The first isolation medium layer is composed of a first upper isolation medium layer, a first middle isolation medium layer and a first lower isolation medium layer, wherein the first lower isolation medium layer covers the inner wall of the lower opening of the trench, the first upper isolation medium layer covers the sidewall of the upper opening of the trench, and the first middle isolation medium layer covers the inner wall of the middle opening of the trench.

9. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 8, wherein: Compared with the first upper isolation medium layer and the first lower isolation medium layer, the thickness of the first middle isolation medium layer is the smallest.

10. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 9, wherein: The first upper isolation dielectric layer and the first lower isolation dielectric layer have the same thickness.

11. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 8, wherein: The upper portion of the trench has a lateral opening size of 0.15-1.2 microns, the middle portion of the trench has a lateral opening size of 0.1-0.6 microns, the lower portion of the trench has a lateral opening size of 0.2-2 microns, the lateral opening size of the lower portion of the trench is greater than that of the middle portion of the trench, and the difference between the two is greater than or equal to 0.1 microns, and the lateral opening size of the upper portion of the trench is greater than that of the middle portion of the trench, and the difference between the two is greater than or equal to 0.01 microns.

12. The stepped trench Schottky barrier diode with heat dissipation trenches in the trenches according to claim 11, wherein: The first middle isolation dielectric layer has a thickness of 0.05-0.15 microns, the first upper isolation dielectric layer and the first lower isolation dielectric layer have a thickness of 0.1-0.6 microns, and the first middle isolation dielectric layer is at least 0.01 microns thinner than the other two first isolation dielectric layers.

Images