Chip stacking structure

Abstract

The utility model discloses a chip stacking structure which comprises a first chip structure and a second chip structure which are connected in a bonding mode, the size of the first chip structure is larger than that of the second chip structure, the first chip structure is provided with a second face used for being connected with the second chip structure in a bonding mode, and the second face is provided with a second face used for being connected with the second chip structure in a bonding mode. The chip stacking structure comprises a supporting structure and a filling layer, the supporting structure is connected to the second surface in a bonding manner, the filling layer is arranged between the second chip structure and the supporting structure, and the supporting structure is arranged outside the second chip structure in a surrounding manner; the supporting structure can be used for improving the warping phenomenon of the chip stacking structure during plastic package filling.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor package test especially relates to a chip stack structure. BACKGROUND

[0002] In the chip application field, for example, the display or image acquisition field of large area array, limited to the size of single chip, multiple chips need to be repeatedly arranged to form a matrix array to achieve the effect of large area array. At the same time, the display or image acquisition chip needs to match the operation module, such as the analog-digital conversion module, which needs to be placed on the back of the chip.

[0003] One of the common practices in the industry is to use wafer-level bonding to stack and interconnect two wafers of sensors and operation to achieve this effect. However, this method requires that the two chips of sensors and operation have the same size and interface to be bonded at the wafer level. Another approach is to use a substrate as a adapter board, and mount two chips of sensors and operation on the upper and lower surfaces, which will result in a long signal transmission path and affect performance. Another approach is to mount small size chips to a large wafer for plastic encapsulation and filling, and then cut, and the support structure formed after plastic encapsulation warps severely. SUMMARY

[0004] One of the purposes of the utility model is to provide a chip stack structure to at least solve the warping problem during plastic encapsulation and filling between the chip and the wafer in the prior art.

[0005] To achieve one of the purposes of the utility model, an embodiment of the utility model provides a chip stack structure including a first chip structure and a second chip structure bonded together, the size of the first chip structure is larger than that of the second chip structure, the first chip structure has a second surface for bonding with the second chip structure, the chip stack structure includes a support structure bonded to the second surface and a filling layer arranged between the second chip structure and the support structure, and the support structure surrounds the second chip structure.

[0006] As a further improvement of the embodiment of the utility model, the outer wall surface of the support structure and the outer wall surface of the first chip structure are located in the same plane.

[0007] As a further improvement of the embodiment of the utility model, the first chip structure includes a first soldering area, the second chip structure includes a second soldering area, and the first soldering area is bonded to the second soldering area.

[0008] As a further improvement of the embodiment of the utility model, the support structure includes a third soldering area arranged on the surface facing the first chip structure, and the third soldering area is connected to the first soldering area.

[0009] As a further improvement of the embodiment of the present application, the support structure comprises a third through silicon via arranged on the surface away from the first chip structure and a third interconnection structure arranged on the third through silicon via, the third interconnection structure being used to connect the third soldering area and the external circuit.

[0010] As a further improvement of the embodiment of the present application, the chip stack structure comprises a first metal bump arranged on the second soldering area, the first metal bump connecting the first soldering area.

[0011] As a further improvement of the embodiment of the present application, the first metal bump corresponds to the middle region of the first chip structure.

[0012] As a further improvement of the embodiment of the present application, the second chip structure comprises opposite third and fourth surfaces, the fourth surface being away from the first chip structure, the second soldering area being located on the third surface; the second chip structure comprises a second through silicon via penetrating the fourth surface along the thickness direction of the second chip structure, a second interconnection structure arranged in the second through silicon via and further extending to the fourth surface, the second interconnection structure being used to connect to the external circuit.

[0013] As a further improvement of the embodiment of the present application, the second interconnection structure further extends to the surface of the support structure away from the first chip structure.

[0014] As a further improvement of the embodiment of the present application, the first chip structure comprises opposite first and second surfaces, the first surface being away from the second chip structure, the first soldering area being located on the first surface; the first chip structure comprises a first through silicon via penetrating the second surface along the thickness direction of the first chip structure, a first interconnection structure arranged in the first through silicon via and further extending to the second surface, the first interconnection structure connecting the first soldering area and the second soldering area.

[0015] Compared with the prior art, the present application provides a chip stack structure, the support structure is located outside the second chip structure and connected to the first chip structure, and the filling layer is further arranged between the support structure and the second chip structure, thereby improving the warping phenomenon caused by the plastic packaging between the first chip structure and the second chip structure. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic view of the chip stack structure in the first embodiment of the present application.

[0017] Figure 2 is a schematic view of the chip stack structure in the second embodiment of the present application.

[0018] Figure 3 is a schematic view of the chip stack structure in the third embodiment of the present application.

[0019] Figure 4 is a schematic diagram of a first wafer in an embodiment of the present application.

[0020] Figure 5 is a schematic diagram of a second chip structure in an embodiment of the present application.

[0021] Figure 6 is a schematic diagram of a wafer-level silicon chip in an embodiment of the present application.

[0022] Figure 7 is a schematic diagram of a wafer-level package structure formed in a first embodiment of the present application.

[0023] Figure 8 is a schematic diagram of a wafer-level package structure formed in a second embodiment of the present application.

[0024] Figure 9 is a schematic diagram of a wafer-level package structure formed in a third embodiment of the present application. DETAILED DESCRIPTION

[0025] The present application will be described in detail below with reference to the specific embodiments shown in the drawings. However, these embodiments do not limit the present application, and any changes in structure, method, or function made by those of ordinary skill in the art based on these embodiments are included in the scope of the present application.

[0026] It should be noted that the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or inherent to such a process, method, article, or device. In addition, the terms "first", "second", "third", "fourth", etc. are only for descriptive purposes and should not be understood as indicating or implying relative importance.

[0027] The term "connected", "connected to", or any other variant is intended to cover various relative positions of the connection, so that it includes direct connection or indirect connection. Among them, the direct connection can be formed by the air path pipeline, the indirect connection can be the connection relationship formed by devices such as valves, sensors, etc., can be the connection relationship formed by air path components such as brake control units, or can be the connection relationship formed by any other medium such as air.

[0028] Please refer to Figure 1 is a structural schematic diagram of a chip stacking structure 1000 provided by an embodiment of the present application.

[0029] The chip stack structure 1000 comprises a first chip structure 10 and a second chip structure 20 which are bonded, the size of the first chip structure 10 is larger than that of the second chip structure 20, the first chip structure 10 has a second surface for bonding with the second chip structure 20, the chip stack structure 1000 comprises a support structure 30 which is bonded to the second surface and a filling layer 40 which is arranged between the second chip structure 20 and the support structure 30, and the support structure 30 surrounds the second chip structure 20.

[0030] In the prior art, the size of the first chip structure 10 is larger than that of the second chip structure 20, and after the second chip structure 20 is attached to the first chip structure 10, the first chip structure 10 and the second chip structure 20 are completely filled with plastic, and due to the large thermal expansion coefficient of the filled organic material and the high curing temperature, the warping area is large and wide after curing.

[0031] The second chip structure 20 is provided with a support structure 30, and then the gap between the second chip structure 20 and the support structure 30 is filled, the filling layer is small, and the warping area is small; the material of the support structure 30 is preferably silicon material, and when the support structure 30 is silicon material, the material is consistent with the materials of the first chip structure 10 and the second chip structure 20, and the warping phenomenon of the silicon material is less; the support structure 30 can also be selected according to needs, such as glass, ceramic and other hard materials which are not easy to deform, and the thermal expansion coefficient of the selected material should be as close as possible to the thermal expansion coefficient of silicon, so as to improve the warping phenomenon.

[0032] The support structure 30 surrounds the second chip structure 20 in a ring shape.

[0033] The outer wall surface of the support structure 30 and the outer wall surface of the first chip structure 10 are located in the same plane, so as to ensure that the first chip structure layer and the second chip structure layer have the same size.

[0034] The filling layer 40 is not only located between the second chip structure 20 and the support structure 30, but also located in the gap between the first chip structure 10 and the second chip structure 20.

[0035] The first chip structure 10 comprises a first welding area 11, the second chip structure 20 comprises a second welding area 21, and the first welding area 11 is bonded to the second welding area 21 to realize the electrical connection between the first chip structure 10 and the second chip structure 20.

[0036] In the preferred embodiment, the first chip structure 10 comprises opposite first and second surfaces, the first surface faces away from the second chip structure 20, and the second surface faces the second chip structure 10.

[0037] The first soldering area 11 can be selectively located on a first surface facing away from the second chip structure 10 or a second surface close to the second chip structure 10, as long as the electrical connection with the second soldering area 21 can be achieved.

[0038] In specific embodiments, in combination with Figure 1 As shown in the figure, the first soldering area 11 is located on the first surface, and the first chip structure 10 further includes a functional area 12 arranged on the first surface; the first chip structure 10 includes a first through-silicon via penetrating through the second surface along the thickness direction of the first chip structure 10, and a first interconnection structure 13 arranged in the first through-silicon via and further extending to the second surface, the first interconnection structure 13 connecting the first soldering area 11 and the second soldering area 21.

[0039] It can be understood that, in order to facilitate the formation of the first interconnection structure 13, the first chip structure 10 includes an insulating layer and a soldering aid layer arranged between the second surface and the first interconnection structure 13.

[0040] In preferred embodiments, the first chip structure 10 includes a solder mask layer 14 arranged on the first interconnection structure 13, the solder mask layer 14 having a window to expose part of the first interconnection structure 13, and the exposed first interconnection structure 13 is used to connect to the second soldering area 21, and the solder mask layer 14 can prevent the second soldering area 21 from extending too far, resulting in a short-circuit connection between the first soldering area 11 and the second soldering area 21.

[0041] In preferred embodiments, the second chip structure 20 includes opposite third and fourth surfaces, the third surface facing the first chip structure 10, and the fourth surface facing away from the first chip structure 10, and the second soldering area 21 is located on the third surface; the second chip structure 20 includes a second through-silicon via penetrating through the fourth surface along the thickness direction of the second chip structure 20, and a second interconnection structure 22 arranged in the second through-silicon via and further extending to the fourth surface, the second interconnection structure 22 being used to connect to an external circuit.

[0042] The third and fourth surfaces of the second chip structure 20 need to be formed with the second soldering area 21 and the second interconnection structure 22, respectively, for connecting the first chip structure 10 and the external circuit, respectively. Specifically, the surface of the second interconnection structure 22 is formed with a solder ball 24, which is connected to the external circuit

[0043] In preferred embodiments, the chip stack structure 1000 includes a first metal bump 23 arranged on the second soldering area 21, and the first metal bump 23 connects the first soldering area 11.

[0044] Specifically, in combination with Figure 1As shown, the first metal bump 23 is connected to the exposed first interconnection structure 13. In practical applications, the first metal bump 23 is usually formed by soldering. The solder resist layer 14 can prevent the solder in molten state from spreading to other active circuit areas of the first chip structure 10, thereby causing short circuit or failure of the circuit. In other embodiments, the first metal bump 23 can also be formed by other soldering materials. In this case, the first chip structure 10 can not be provided with the solder resist layer 14.

[0045] In preferred embodiments, the first metal bump 23 corresponds to the middle region of the first chip structure 10. More specifically, the central axes of the first chip structure 10 and the second chip structure 20 are aligned. When the first chip structure 10 and the second chip structure 20 are attached, the central axes are aligned, thereby ensuring that the chip stacking structure 1000 has balanced stress.

[0046] In combination Figure 1 As described above, in the first embodiment, the support structure 30 is arranged outside the second chip structure 20 and connected to the second surface of the first chip structure 10. The support structure 30 can only be used to support and reduce warping. In more embodiments, the support structure 30 can also be provided with an interconnection structure, thereby realizing the function of a conversion board and taking into account the signal transmission density between the first chip structure 10 and the second chip structure 20.

[0047] In combination Figure 2 As shown, in the second embodiment, the second interconnection structure 22 of the second chip structure 20 further extends to the surface of the support structure 30 away from the first chip structure 10 and is further used to connect to an external circuit, thereby expanding the number of solder balls 24 of the second chip structure 20 and facilitating electrical connection with different external circuits.

[0048] In combination Figure 3 As shown, in the third embodiment, the support structure 30 includes a third soldering area 31 arranged on the surface facing the first chip structure 10. The third soldering area 31 is connected to the first soldering area 11. The surface of the third soldering area 31 is provided with a third metal bump 32. The third metal bump 32 is connected to the first chip structure 10, specifically to the exposed first interconnection structure 13.

[0049] Therefore, the first chip structure 10 can be connected to an external circuit through the support structure 30 alone.

[0050] Specifically, the support structure 30 includes a third through-silicon via arranged on the surface away from the first chip structure 10 and a third interconnection structure 33 arranged on the third through-silicon via. The third interconnection structure 33 is used to connect the third soldering area 31 and an external circuit.

[0051] Similarly, in the third embodiment, the second interconnection structure 22 can also be arranged to further extend to the surface of the support structure 30 away from the first chip structure 10, so that the electrical signal of the first chip structure 10 can be individually led out through the support structure 30, and the electrical signal can also be led out after the first chip structure 20 and the second chip structure 20 are electrically coupled.

[0052] In combination Figures 4-9 As shown in the drawings, the utility model discloses a wafer level packaging method, and the wafer level packaging method can obtain the chip stack structure 1000 in the above technical scheme, and the wafer level packaging method comprises the following steps:

[0053] S1: provide a first wafer 100, wherein the first wafer 100 comprises a plurality of first chip structures 10 that can be obtained by division. In combination Figure 4 As shown in the drawings, the first chip structure 10 comprises a first soldering area 11 and a functional area 12.

[0054] In combination Figure 4 As shown in the drawings, after "providing the first wafer 11", the following steps are included:

[0055] S11: manufacturing a first through silicon via on the second surface of the first wafer 100; the first surface of the first wafer 100 is provided with the first soldering area 11, and the first surface and the second surface are oppositely arranged.

[0056] Manufacturing a first interconnection structure 13 in the first through silicon via, and the first interconnection structure 13 is connected with the first soldering area 11. It is equivalent to performing a through silicon via process and a redistribution process on the second surface of the first wafer 100 to realize vertical interconnection.

[0057] It can be understood that the insulating layer and the soldering layer need to be manufactured before manufacturing the first interconnection structure 13, and then the first interconnection structure 13 is manufactured on the surface of the soldering layer; it can be understood that after manufacturing the first interconnection structure 13, a solder mask layer 14 can be manufactured on the surface of the first interconnection structure 13, and the solder mask layer 14 exposes part of the first interconnection structure 13 for electrical connection.

[0058] S2: providing a second wafer 200 and cutting the second wafer 200 to obtain a plurality of single second chip structures 20; in combination Figure 5 As shown in the drawings, the second chip structure 20 comprises a second soldering area 21.

[0059] The size of the first chip structure 10 is greater than the size of the second chip structure 20; if the size of the first chip structure 10 and the size of the second chip structure 20 are the same, wafer level bonding and single cutting can be directly performed without mounting and then performing plastic packaging and single cutting.

[0060] Before "dicing the second wafer 200", a first metal bump 23 is fabricated in the second bonding area 21 of the second wafer 200. Fabricating the first metal bump 23 before dicing is a simple, time-saving, and efficient process.

[0061] S3: Provides wafer-level silicon wafers 300, combined with... Figure 6 As shown in Figure a, the silicon wafer 300 has a plurality of mesh holes 310, the size of which matches the size of a single second chip structure 20; the specific size is slightly larger than the size of the second chip structure 20 to facilitate installation and prevent interference.

[0062] S4: The wafer-level silicon wafer 300 and several second chip structures 20 are bonded to the first wafer 100 to form a wafer-level packaging structure 2000. Figure 7 As shown, several of the second chip structures 20 are located within the mesh 310.

[0063] Specifically, “bonding several second chip structures 20 to the first wafer 100” includes: bonding the first metal bump 23 and the first interconnect structure 13, including dielectric bonding and dielectric-free bonding, wherein dielectric bonding further includes conductive adhesive bonding and metal bonding.

[0064] Combination Figure 7 , 8 As shown, in the first and second embodiments, "bonding the wafer-level silicon wafer 300 to the first wafer 100" includes: bonding one side surface of the wafer-level silicon wafer 300 to the solder mask layer 14 of the first wafer 100. No electrical connection needs to be formed between the wafer-level silicon wafer 300 and the first wafer 100.

[0065] Combination Figure 6 As shown in b, in the third embodiment, “providing a wafer-level silicon wafer 300” includes: forming a third welding area 31 on the surface of the silicon wafer 300.

[0066] Combination Figure 9 As shown, in the third embodiment, "bonding the wafer-level silicon wafer 300 to the first wafer 100" includes: bonding the first interconnect structure 13 and the third bonding area 31. Specifically, the third bonding area 31 is provided with a second metal bump 32, which is bonded to the exposed first interconnect structure 13, and an electrical connection needs to be formed between the wafer-level silicon wafer 300 and the first wafer 100.

[0067] It should be noted that there is no strict distinction between the bonding of the first wafer 100 and the second chip structure 20, and the bonding of the first wafer 100 and the wafer-level silicon wafer 300.

[0068] S5: Fill the wafer-level packaging structure 1000; combineFigure 7 As shown, after the first wafer 100, the second chip structure 20 and the wafer-level silicon chip 300 are bonded, the filling process can be performed on the bonded trench and gap to form the filling layer 40, so as to form the wafer-level structure which is completely encapsulated, and then the through-silicon via process and the redistribution layer process can be performed.

[0069] After the filling, the surface of the second chip structure 20 and the wafer-level silicon chip 300 which is away from the first wafer 100 can be optionally ground.

[0070] S6: A second through-silicon via is made on the fourth surface of the second chip structure 20, and the third surface of the second chip structure 20 is provided with a second soldering area 21; a second interconnection structure 22 is made in the second through-silicon via, and the second interconnection structure 22 is used to connect the second soldering area 21 and an external circuit.

[0071] In combination with Figure 7 As shown, in the first embodiment, the second interconnection structure 22 and the soldering ball 23 are only made on the third surface of the second chip structure 20, and the wafer-level silicon chip 300 is only used for supporting.

[0072] In combination with Figure 8 As shown, in the second embodiment, the second interconnection structure 22 and the soldering ball 24 can be continuously made on the surface of the wafer-level silicon chip 300.

[0073] In combination with Figure 9 As shown, in the third embodiment, the wafer-level packaging method comprises the steps that a third through-silicon via is made on the surface of the silicon chip 300, and a third interconnection structure 33 is made in the third through-silicon via, and the third interconnection structure 33 is used to connect an external circuit.

[0074] S6: The wafer-level packaging structure 2000 is cut to obtain a single chip stack structure 1000. The first chip structure 10 is obtained by cutting the first wafer 100, and the support structure 30 is obtained by cutting the wafer-level silicon chip 300.

[0075] The support structure 30 is located outside the second chip structure 20, and the filling layer 40 is filled between the support structure 30 and the second chip structure 20, so as to improve the warping phenomenon caused by direct encapsulation and filling; the support structure 30 is provided with the interconnection structure, and the signal transmission density is considered; after the second chip structure 20 is cut, the wafer-level silicon chip 300 is bonded with the first wafer 100, and then the filling, the interconnection structure making and the cutting are performed, which is equivalent to wafer-level packaging, and the process is simplified.

[0076] Any of the technical solutions provided in the foregoing can be formed, and details are not described herein.

[0077] It should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

[0078] The above series of detailed descriptions are only specific descriptions of the feasible embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A chip stack structure, characterized by, A chip stack structure includes a first chip structure and a second chip structure bonded together, the first chip structure having a second surface to be bonded to the second chip structure, the chip stack structure including a support structure bonded to the second surface and a filling layer disposed between the second chip structure and the support structure, the support structure surrounding the second chip structure.

2. The chip stack structure of claim 1, wherein, An outer wall surface of the support structure and an outer wall surface of the first chip structure are in the same plane.

3. The chip stack structure of claim 1, wherein, The first chip structure includes a first solder region, the second chip structure includes a second solder region, and the first solder region is bonded to the second solder region.

4. The chip stack structure of claim 3, wherein, The support structure includes a third solder region disposed on a surface facing a surface of the first chip structure, the third solder region being connected to the first solder region.

5. The chip stack structure of claim 4, wherein, The support structure includes a third through-silicon via disposed on a surface facing away from the first chip structure and a third interconnect structure disposed in the third through-silicon via, the third interconnect structure being configured to connect the third solder region to an external circuit.

6. The chip stack structure of claim 3, wherein, The chip stack structure includes a first metal bump disposed on the second solder region, the first metal bump being connected to the first solder region.

7. The chip stack structure of claim 6, wherein, The first metal bump corresponds to a middle region of the first chip structure.

8. The chip stack structure of claim 3, wherein, The second chip structure includes opposite third and fourth surfaces, the fourth surface facing away from the first chip structure, and the second solder region is disposed on the third surface; the second chip structure includes a second through-silicon via extending through the fourth surface along a thickness direction of the second chip structure, and a second interconnect structure disposed in the second through-silicon via and further extending to the fourth surface, the second interconnect structure being configured to connect to an external circuit.

9. The chip stack structure of claim 8, wherein, The second interconnect structure further extends to a surface of the support structure facing away from the first chip structure.

10. The chip stack structure of claim 3, wherein, The first chip structure includes opposite first and second surfaces, the first surface facing away from the second chip structure, and the first solder region is disposed on the first surface; the first chip structure includes a first through-silicon via extending through the second surface along a thickness direction of the first chip structure, and a first interconnect structure disposed in the first through-silicon via and further extending to the second surface, the first interconnect structure being connected to the first solder region and the second solder region.

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