Compatible fault detection card circuit

Abstract

The utility model discloses a compatible fault detection card circuit. The circuit comprises an IO chip DBU1, an LPC pin DBLPC1 and an ESPI pin DBESPI, wherein the IO chip DBU1 is provided with an LPC multiplexing pin compatible with an LPC low-speed bus and an ESPI multiplexing pin compatible with an ESPI high-speed bus, the LPC pin DBLPC1 is connected to the LPC multiplexing pin, and the ESPI pin DBESPI is connected to the ESPI multiplexing pin. In addition, the circuit also comprises a digital lamp and a 3VSB to 1.8 VSB circuit. According to the utility model, through the unique circuit design, the compatibility of the LPC low-speed bus and the ESPI high-speed bus is realized, the inconvenience caused by the bus technology upgrading to the debugging of a template and the positioning of after-sales repair problems by engineers in the development process of an X86 platform in the PC industry is effectively solved, and the circuit has the advantages of strong compatibility, convenience, high efficiency, cost reduction, complete functions and the like.

Description

Technical Field

[0001] This utility model relates to PC detection cards, specifically to a compatible fault detection card circuit. The compatible fault detection card circuit is applied to PC detection cards. Background Technology

[0002] With the rapid development of the x86 platform in the PC industry, technological innovation is happening at an unprecedented pace. In terms of bus technology, the low-speed LPC bus used in older platforms is gradually becoming insufficient to meet the ever-increasing data transmission demands. Starting with the 10th generation products of Intel and AMD platforms, a major transformation occurred within the bridge chip, with the LPC low-speed bus being completely replaced by the high-speed ESPI bus. While this technological upgrade greatly improved system performance, it also brought new challenges to engineers' debugging work and troubleshooting after-sales issues. In practice, when facing motherboards from different generations of platforms, engineers often need to carry multiple types of fault detection devices due to the lack of a convenient tool compatible with both LPC and ESPI buses. This not only increases the complexity and cost of their work but also reduces efficiency. Therefore, developing a fault detection card compatible with both LPC and ESPI buses is of significant practical importance. Utility Model Content

[0003] The main objective of this invention is to provide a compatible fault detection card circuit, aiming to solve the inconvenience faced by engineers in debugging prototypes and locating after-sales repair issues due to bus technology upgrades during the development of the X86 platform in the PC industry. By designing a fault detection card compatible with both the LPC low-speed bus and the ESPI high-speed bus, engineers can complete fault detection work using only this one device when dealing with motherboards of different platforms, thereby simplifying the workflow, improving work efficiency, and reducing operating costs.

[0004] To solve the above technical problems, this utility model provides the following solution: A compatible fault detection card circuit of this utility model includes:

[0005] The IO chip DBU1 has LPC multiplexed pins compatible with the LPC low-speed bus and ESPI multiplexed pins compatible with the ESPI high-speed bus.

[0006] LPC pin DBLPC1 is connected to the LPC multiplexer pin;

[0007] The ESPI pin DBESPI is connected to the ESPI multiplexer pin.

[0008] Furthermore, the IO chip DBU1 model is the IT8786E-80.

[0009] Furthermore, the compatible fault detection card circuit also includes a digital lamp, which is connected to the IO chip DBU1.

[0010] Furthermore, the compatible fault detection card circuit also includes a 3VSB to 1.8VSB circuit, which includes:

[0011] The power management chip UP0109 has its pin 2 (GND) and pin 9 (GND) interconnected and grounded. Pins 5 to 8 of the power management chip UP0109 are interconnected. The output terminal 4 (VOUT) of the power management chip UP0109 outputs 1.8VSB.

[0012] A series resistor DBR390 and a resistor DBR389 are connected in series, with the first end of the series connection of resistor DBR390 and resistor DBR389 grounded.

[0013] The capacitor DBC379 has its first terminal connected to the second terminal of the series connection between the resistors DBR390 and DBR389. The second terminal of the capacitor DBC379 is grounded. The first terminal of the capacitor DBC379 is also connected to pin 12 (3VSB) of the IO chip DBU1.

[0014] The capacitor DBC374 has its first terminal grounded and its second terminal connected to pin 3 (REF) of the power management chip UP0109. Pin 3 (REF) of the power management chip UP0109 is also connected to the circuit node between resistors DBR390 and DBR389.

[0015] Capacitor DBC5, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is grounded;

[0016] Resistor DBR388, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is connected to pin 12 (3VSB) of the IO chip DBU;

[0017] The capacitors DBC9 and DBC372 are connected in parallel. The first terminal of the capacitor DBC9 is grounded, and its second terminal is connected to the output terminal 4 VOUT of the power management chip UP0109.

[0018] Compared with the prior art, the beneficial effects of this utility model are:

[0019] 1. Strong compatibility of this utility model: The fault detection card circuit of this utility model, by setting up an IO chip DBU1 with LPC multiplexed pins compatible with LPC low-speed bus and ESPI multiplexed pins compatible with ESPI high-speed bus, and connecting LPC pins DBLPC1 and ESPI pins DBESPI respectively, can be perfectly compatible with motherboards of different platforms. Whether it is a motherboard using an old platform LPC low-speed bus or a motherboard using a new platform ESPI high-speed bus, it can achieve fast connection and fault detection, greatly expanding the application scope of the fault detection card.

[0020] 2. This utility model is convenient and efficient: When engineers are debugging prototypes and locating problems in after-sales repairs, they no longer need to change different fault detection devices according to the bus type of the motherboard. They only need to select the corresponding pins to connect to the motherboard according to the platform support, which greatly saves time and effort and significantly improves work efficiency.

[0021] 4. Cost reduction of this utility model: Since one fault detection card can meet the needs of multiple platforms, it reduces the procurement and maintenance costs of engineers for various types of fault detection equipment, saving a lot of money for enterprises and individuals in the long run.

[0022] 5. This utility model has comprehensive functions: The circuit also includes digital lights that can intuitively display fault information, facilitating engineers to quickly determine the fault type. Simultaneously, the 3VSB to 1.8VSB circuit design provides stable power support for the IO chip DBU1, ensuring the stable operation of the entire fault detection card circuit. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of the IO chip DBU1 and its peripheral circuits of this utility model.

[0024] Figure 2 for Figure 1 Enlarged view of the ESPI multiplexed pins and LPC multiplexed pins.

[0025] Figure 3 This is the circuit diagram of the DBJ11 interface of this utility model.

[0026] Figure 4 This is the circuit diagram for the 3VSB to 1.8VSB of this utility model.

[0027] Figure 5 This is the circuit diagram of the ESPI connector DBESPI of this utility model.

[0028] Figure 6 This is the circuit diagram of the LPC pin DBLPC1 of this utility model.

[0029] Figure 7 This is the circuit diagram of the digital lamp of this utility model. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments, so that the advantages and features of the present utility model can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present utility model. Obviously, the embodiments described in this utility model are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0031] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0032] Example 1: The specific structure of this utility model is as follows:

[0033] Please refer to the appendix. Figure 1-7 The present invention relates to a compatible fault detection card circuit, comprising an IO chip DBU1, an LPC pin DBLPC1, and an ESPI pin DBESPI.

[0034] The DBU1 I / O chip features LPC multiplexed pins compatible with the LPC low-speed bus and ESPI multiplexed pins compatible with the ESPI high-speed bus. The DBU1 I / O chip is model IT8786E-80. Functionally, it integrates a wide variety of features. In terms of temperature monitoring, it can accurately sense changes in ambient temperature, monitoring both industrial equipment operating environments and the temperature of internal heat dissipation areas in electronic devices. Voltage monitoring is also a strong point, allowing real-time monitoring of voltage conditions and preventing damage to equipment due to abnormal voltage.

[0035] The IO chip DBU1 has pins 16 (ESPI_CS#), 17 (ESPI_IO[0]), 18 (ESPI_IO[1]), 19 (ESPI_IO[2]), 20 (ESPI_IO[3]), 21 (ESPI_ALERT#), 22 (ESPI_RESET#), and 23 (ESPI_CLK).

[0036] The LPC pin DBLPC1 is connected to the LPC multiplexed pin, and the ESPI pin DBESPI is connected to the ESPI multiplexed pin. Each multiplexed pin is connected to a resistor, and the other end of each resistor is connected one-to-one to the terminals of the LPC pin DBLPC1 and the ESPI pin DBESPI.

[0037] The LPC multiplexed pin and the ESPI multiplexed pin have common pins, namely pin 16 ESPI_CS#, pin 17 ESPI_IO[0], pin 18 ESPI_IO[1], pin 19 ESPI_IO[2], pin 20 ESPI_IO[3], and pin 23 ESPI_CLK.

[0038] The ESPI multiplexed pins also include pin 21 ESPI_ALERT# and pin 22 ESPI_RESET#.

[0039] Pin 14, PLTRST#, of the IO chip DBU1 is the chip reset pin, used for resetting. This chip reset pin is connected to resistor DBR26 and the PLTRST# circuit. The other end of resistor DBR26 is connected to the 3.3V_SIO circuit. The PLTRST# circuit is connected to LPC pin DBLPC1 and ESPI pin DBESPI respectively.

[0040] Pin 12 (3VSB) and pin 53 (AVCC3) of the IO chip DBU1 are power supply pins. Pin 12 (3VSB) is connected to the positive terminal of a polarized capacitor DBC15, and the negative terminal of the polarized capacitor DBC15 is grounded. Pin 12 (3VSB) is connected to a 3VSB circuit. Pin 53 (AVCC3) is connected to two parallel polarized capacitors. One end of each parallel polarized capacitor is grounded, and the other end is connected to a 3.3V_SIO circuit.

[0041] The compatible fault detection card circuit also includes a digital lamp, which is connected to the IO chip DBU1. Pins 55 (DIG3), 56 (DIG2), 57 (DIG1), 59 (SEG_A), 60 (SEG_B), 61 (SEG_C), 62 (SEG_D), 63 (SEG_E), and 64 (SEG_F) of the IO chip DBU1 are connected to the digital lamp for controlling its operation.

[0042] The compatible fault detection card circuit also includes a 3VSB to 1.8VSB circuit. "DBVR3 is a 3.3V to 1.8V LDO", which means that DBVR3 is a low dropout linear regulator (LDO) chip whose function is to stably convert the input 3.3V DC voltage to a 1.8V DC voltage output.

[0043] The 3VSB to 1.8VSB circuit includes:

[0044] The power management chip UP0109 has its pin 2 (GND) and pin 9 (GND) interconnected and grounded. Pins 5 to 8 of the power management chip UP0109 are interconnected. The output terminal 4 (VOUT) of the power management chip UP0109 outputs 1.8VSB.

[0045] A series resistor DBR390 and a resistor DBR389 are connected in series, with the first end of the series connection of resistor DBR390 and resistor DBR389 grounded.

[0046] The capacitor DBC379 has its first terminal connected to the second terminal of the series connection between the resistors DBR390 and DBR389. The second terminal of the capacitor DBC379 is grounded. The first terminal of the capacitor DBC379 is also connected to pin 12 (3VSB) of the IO chip DBU1.

[0047] The capacitor DBC374 has its first terminal grounded and its second terminal connected to pin 3 (REF) of the power management chip UP0109. Pin 3 (REF) of the power management chip UP0109 is also connected to the circuit node between resistors DBR390 and DBR389.

[0048] Capacitor DBC5, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is grounded;

[0049] Resistor DBR388, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is connected to pin 12 (3VSB) of the IO chip DBU;

[0050] The capacitors DBC9 and DBC372 are connected in parallel. The first terminal of the capacitor DBC9 is grounded, and its second terminal is connected to the output terminal 4 VOUT of the power management chip UP0109.

[0051] The old LPC low-speed bus has been replaced by the new high-speed ESPI bus. Starting from the 10th generation, Intel and AMD platforms no longer have LPC inside the bridge chip; it has been replaced by ESPI. To facilitate engineers' debugging of prototypes and the location of after-sales repair issues, a new detection card was designed. This detection card is compatible with both LPC and ESPI. The card uses the ITE 8786E-80 chip and has two types of pins: LPC pins (DBLPC1) and ESPI pins (DBESPI). Depending on the platform support, the corresponding pin is selected to connect to the motherboard.

[0052] In summary, this utility model has strong compatibility: the fault detection card circuit of this utility model, by setting up an IO chip DBU1 with LPC multiplexed pins compatible with the LPC low-speed bus and ESPI multiplexed pins compatible with the ESPI high-speed bus, and connecting LPC pins DBLPC1 and ESPI pins DBESPI respectively, can be perfectly compatible with motherboards of different platforms. Whether it is a motherboard using an old platform with an LPC low-speed bus or a motherboard using a new platform with an ESPI high-speed bus, it can achieve fast connection and fault detection, greatly expanding the application scope of the fault detection card.

[0053] This utility model is convenient and efficient: when engineers are debugging prototypes and locating after-sales repair issues, they no longer need to change different fault detection devices according to the motherboard's bus type. They only need to select the corresponding pins to connect to the motherboard according to the platform's support, which greatly saves time and effort and significantly improves work efficiency.

[0054] This invention reduces costs: Since a single fault detection card can meet the needs of multiple platforms, it reduces the procurement and maintenance costs for engineers of various types of fault detection equipment, saving a significant amount of money for businesses and individuals in the long run.

[0055] This utility model boasts comprehensive functionality: the circuit incorporates digital lights to intuitively display fault information, facilitating rapid fault identification by engineers. Furthermore, the 3VSB to 1.8VSB circuit design provides stable power support for the DBU1 IO chip, ensuring the stable operation of the entire fault detection card circuit.

[0056] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural or procedural transformations made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A compatible fault detection card circuit, characterized in that, include: The IO chip DBU1 has LPC multiplexed pins compatible with the LPC low-speed bus and ESPI multiplexed pins compatible with the ESPI high-speed bus. LPC pin DBLPC1 is connected to the LPC multiplexer pin; The ESPI pin DBESPI is connected to the ESPI multiplexer pin.

2. The compatible fault detection card circuit according to claim 1, characterized in that, The IO chip DBU1 model is the IT8786E-80.

3. The compatible fault detection card circuit according to claim 1, characterized in that, The compatible fault detection card circuit also includes a digital lamp, which is connected to the IO chip DBU1.

4. The compatible fault detection card circuit according to claim 1, characterized in that, The compatible fault detection card circuit also includes a 3VSB to 1.8VSB circuit, which includes: The power management chip UP0109 has its pin 2 (GND) and pin 9 (GND) interconnected and grounded. Pins 5 to 8 of the power management chip UP0109 are interconnected. The output terminal 4 (VOUT) of the power management chip UP0109 outputs 1.8VSB. A series resistor DBR390 and a resistor DBR389 are connected in series, with the first end of the series connection of resistor DBR390 and resistor DBR389 grounded. The capacitor DBC379 has its first terminal connected to the second terminal of the series connection between the resistors DBR390 and DBR389. The second terminal of the capacitor DBC379 is grounded. The first terminal of the capacitor DBC379 is also connected to pin 12 (3VSB) of the IO chip DBU1. The capacitor DBC374 has its first terminal grounded and its second terminal connected to pin 3 (REF) of the power management chip UP0109. Pin 3 (REF) of the power management chip UP0109 is also connected to the circuit node between resistors DBR390 and DBR389. Capacitor DBC5, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is grounded; Resistor DBR388, the first end of which is connected to pin 8 of the power management chip UP0109, and the second end of which is connected to pin 12 (3VSB) of the IO chip DBU; The capacitors DBC9 and DBC372 are connected in parallel. The first terminal of the capacitor DBC9 is grounded, and its second terminal is connected to the output terminal 4 VOUT of the power management chip UP0109.

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