Driving circuit, driving module and display device

Abstract

The utility model provides a driving circuit, a driving module and a display device. The driving circuit comprises an input circuit, N output control circuits and N driving output circuits; n is a positive integer; the input circuit controls the potential of a first node according to an input signal; the nth output control circuit controls the connection or disconnection between the first node and the nth output control node under the control of the control voltage; n is a positive integer smaller than or equal to N; the nth driving output circuit supplies the nth output clock signal to the nth driving output end under the control of the potential of the nth output control node. According to the utility model, a narrow frame is realized.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a driving circuit, a driving module, and a display device. Background Technology

[0002] The related driving circuit cannot easily control multiple driving output terminals to output corresponding driving signals through a first node, which is not conducive to reducing the number of transistors used and to achieving a narrow bezel. Summary of the Invention

[0003] The main purpose of this invention is to provide a driving circuit that solves the problem that existing driving circuits are not conducive to reducing the number of transistors used and to achieving a narrow bezel.

[0004] In the first aspect, the present invention provides a driving circuit, including an input circuit, N output control circuits and N driving output circuits; N is a positive integer;

[0005] The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal;

[0006] The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N;

[0007] The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

[0008] Optionally, both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or,

[0009] The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

[0010] Optionally, the driving circuit described in at least one embodiment of this utility model further includes N energy storage circuits;

[0011] The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal.

[0012] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal;

[0013] The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node.

[0014] The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0015] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal;

[0016] The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node.

[0017] The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0018] Optionally, the driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; the second input circuit is electrically connected to the input terminal, the control node, and the first node respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or,

[0019] The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

[0020] Optionally, the control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit.

[0021] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0022] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

[0023] Optionally, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit;

[0024] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0025] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node;

[0026] The third first node control circuit is electrically connected to the second second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node.

[0027] The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

[0028] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit;

[0029] The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal.

[0030] The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

[0031] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit.

[0032] The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal.

[0033] The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

[0034] Optionally, the driving circuit described in at least one embodiment of this utility model further includes N output reset circuits;

[0035] The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

[0036] Optionally, the driving circuit described in at least one embodiment of this utility model further includes N output reset circuits;

[0037] The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

[0038] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a carry output circuit and a carry energy storage circuit;

[0039] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0040] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0041] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a carry output circuit, a carry output control circuit, and a carry energy storage circuit;

[0042] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0043] The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal.

[0044] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0045] Optionally, both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal; or,

[0046] The transistors included in the input circuit and the transistors included in the carry-out control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal.

[0047] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a carry output circuit and a carry energy storage circuit;

[0048] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the second second node.

[0049] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0050] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a carry output circuit, a carry output control circuit, and a carry energy storage circuit;

[0051] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0052] The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal.

[0053] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0054] Optionally, both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the first control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. Similarly, the difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the second control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal. Alternatively,

[0055] Both the transistors in the input circuit and the transistors in the carry-out control circuit are p-type transistors. The difference between the threshold voltage of the transistor whose gate is electrically connected to the first control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor whose gate is electrically connected to the second control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0056] Optionally, the input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node;

[0057] The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; the gate of the nth second transistor is electrically connected to the second control voltage terminal, the first electrode of the nth second transistor is electrically connected to the nth output control node, and the second electrode of the nth second transistor is electrically connected to the first node.

[0058] Optionally, the control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or...

[0059] The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

[0060] Optionally, the second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor;

[0061] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0062] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0063] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0064] Optionally, the second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor.

[0065] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0066] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0067] The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node;

[0068] The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal.

[0069] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0070] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0071] Optionally, the first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor;

[0072] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0073] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0074] Optionally, the first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor.

[0075] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0076] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0077] The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node.

[0078] The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

[0079] Optionally, the first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor;

[0080] The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node.

[0081] The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

[0082] Optionally, the first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor;

[0083] The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node.

[0084] The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

[0085] Optionally, the nth output reset circuit includes an nth output reset transistor;

[0086] The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

[0087] Optionally, the nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor;

[0088] The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal.

[0089] The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

[0090] Optionally, the carry output circuit includes a carry capacitor, a carry output transistor, and a first carry reset transistor;

[0091] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0092] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0093] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0094] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; and the carry energy storage circuit includes a carry capacitor.

[0095] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0096] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0097] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0098] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0099] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry energy storage circuit includes a carry capacitor.

[0100] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0101] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0102] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0103] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0104] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor.

[0105] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0106] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0107] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0108] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0109] The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node.

[0110] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0111] Optionally, the nth drive output circuit includes an nth drive output transistor, and the nth energy storage circuit includes an nth output capacitor;

[0112] The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal.

[0113] The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

[0114] In a second aspect, embodiments of the present invention provide a driving module comprising multiple stages of the aforementioned driving circuits.

[0115] In a third aspect, embodiments of the present invention provide a display device including the aforementioned driving module.

[0116] The driving circuit, driving module, and display device described in this invention can reduce the number of transistors used, which is not conducive to achieving a narrow bezel. Attached Figure Description

[0117] Figure 1A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0118] Figure 1B yes Figure 1A The structural diagram of the first part;

[0119] Figure 1C yes Figure 1A The structural diagram of the second part;

[0120] Figure 2A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0121] Figure 2B yes Figure 2A The structural diagram of the first part;

[0122] Figure 2C yes Figure 2A The structural diagram of the second part;

[0123] Figure 3A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0124] Figure 3B yes Figure 3A The structural diagram of the first part;

[0125] Figure 3C yes Figure 3A The structural diagram of the second part;

[0126] Figure 4A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0127] Figure 4B yes Figure 4A The structural diagram of the first part;

[0128] Figure 4C yes Figure 4A The structural diagram of the second part;

[0129] Figure 5A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0130] Figure 5B yes Figure 5A The structural diagram of the first part;

[0131] Figure 5C yes Figure 5A The structural diagram of the second part;

[0132] Figure 6A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0133] Figure 6B yes Figure 6A The structural diagram of the first part;

[0134] Figure 6C yes Figure 6A The structural diagram of the second part;

[0135] Figure 7A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0136] Figure 7B yes Figure 7A The structural diagram of the first part;

[0137] Figure 7C yes Figure 7A The structural diagram of the second part;

[0138] Figure 8A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0139] Figure 8B yes Figure 8A The structural diagram of the first part;

[0140] Figure 8C yes Figure 8A The structural diagram of the second part;

[0141] Figure 9A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0142] Figure 9B yes Figure 9A The structural diagram of the first part;

[0143] Figure 9C yes Figure 9A The structural diagram of the second part;

[0144] Figure 10A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0145] Figure 10B yes Figure 10A The structural diagram of the first part;

[0146] Figure 10C yes Figure 10A The structural diagram of the second part;

[0147] Figure 11A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0148] Figure 11B yes Figure 11A The structural diagram of the first part;

[0149] Figure 11C yes Figure 11A The structural diagram of the second part;

[0150] Figure 12A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0151] Figure 12B yes Figure 12A The structural diagram of the first part;

[0152] Figure 12C yes Figure 12A The structural diagram of the second part;

[0153] Figure 13A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0154] Figure 13B yes Figure 13A The structural diagram of the first part;

[0155] Figure 13C yes Figure 13A The structural diagram of the second part;

[0156] Figure 14A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0157] Figure 14B yes Figure 14A The structural diagram of the first part;

[0158] Figure 14C yes Figure 14A The structural diagram of the second part;

[0159] Figure 15A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0160] Figure 15B yes Figure 15A The structural diagram of the first part;

[0161] Figure 15C yes Figure 15A The structural diagram of the second part;

[0162] Figure 15D This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0163] Figure 15E yes Figure 15D The structural diagram of the second part;

[0164] Figure 16A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0165] Figure 16B yes Figure 16A The structural diagram of the first part;

[0166] Figure 16C yes Figure 16A The structural diagram of the second part;

[0167] Figure 17A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0168] Figure 17B yes Figure 17A The structural diagram of the first part;

[0169] Figure 17C yes Figure 17A The structural diagram of the second part;

[0170] Figure 18A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0171] Figure 18B yes Figure 18A The structural diagram of the first part;

[0172] Figure 18C yes Figure 18A The structural diagram of the second part;

[0173] Figure 19A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0174] Figure 19B yes Figure 19A The structural diagram of the first part;

[0175] Figure 19C yes Figure 19A The structural diagram of the second part;

[0176] Figure 20A This is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0177] Figure 20B yes Figure 20A The structural diagram of the first part;

[0178] Figure 20C yes Figure 20A The structural diagram of the second part;

[0179] Figure 21A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0180] Figure 21B yes Figure 21A The structural diagram of the first part;

[0181] Figure 21C yes Figure 21A The structural diagram of the second part;

[0182] Figure 21D This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0183] Figure 21E yes Figure 21D The structural diagram of the second part;

[0184] Figure 22A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0185] Figure 22B yes Figure 22A The structural diagram of the first part;

[0186] Figure 22C yes Figure 22A The structural diagram of the second part;

[0187] Figure 22D This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0188] Figure 22E yes Figure 22D The structural diagram of the second part;

[0189] Figure 23A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0190] Figure 23B yes Figure 23A The structural diagram of the first part;

[0191] Figure 23C yes Figure 23A The structural diagram of the second part;

[0192] Figure 24A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0193] Figure 24B yes Figure 24A The structural diagram of the first part;

[0194] Figure 24C yes Figure 24A The structural diagram of the second part;

[0195] Figure 24D This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0196] Figure 24E yes Figure 24D The structural diagram of the second part;

[0197] Figure 25A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0198] Figure 25B yes Figure 25A The structural diagram of the first part;

[0199] Figure 25C yes Figure 25A The structural diagram of the second part;

[0200] Figure 26A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0201] Figure 26B yes Figure 26A The structural diagram of the first part;

[0202] Figure 26C yes Figure 26A The structural diagram of the second part;

[0203] Figure 26D This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0204] Figure 26E yes Figure 26D The structural diagram of the second part;

[0205] Figure 27A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0206] Figure 27B yes Figure 27A The structural diagram of the first part;

[0207] Figure 27C yes Figure 27A The structural diagram of the second part;

[0208] Figure 28A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0209] Figure 28B yes Figure 28A The structural diagram of the first part;

[0210] Figure 28C yes Figure 28A The structural diagram of the second part;

[0211] Figure 29A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0212] Figure 29B yes Figure 29A The structural diagram of the first part;

[0213] Figure 29C yes Figure 29A The structural diagram of the second part;

[0214] Figure 30A This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0215] Figure 30B yes Figure 30A The structural diagram of the first part;

[0216] Figure 30C yes Figure 30A The structural diagram of the second part;

[0217] Figure 31 This is a structural diagram of the drive module according to at least one embodiment of the present invention;

[0218] Figure 32 yes Figure 31 The timing diagram shows the operation of at least one embodiment of the driving module. Detailed Implementation

[0219] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0220] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0221] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0222] The driving circuit described in this embodiment of the utility model includes an input circuit, N output control circuits, and N driving output circuits; N is a positive integer;

[0223] The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal;

[0224] The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N;

[0225] The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

[0226] When the driving circuit described in this embodiment of the present invention is working, the nth output control circuit controls the connection or disconnection between the first node and the nth output control node under the control of the control voltage; the nth drive output circuit provides the nth output clock signal to the nth drive output terminal under the control of the potential of the nth output control node; the driving circuit described in this embodiment of the present invention can control N drive output terminals to output corresponding drive signals through one first node, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0227] Optionally, both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or,

[0228] The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

[0229] When the driving circuit described in this embodiment of the present invention is working, there will be leakage current from the nth output control node to the first node, which will cause an output abnormality at the nth drive output terminal. Based on this, in at least one embodiment of the present invention, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors, the difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; when both the transistors included in the input circuit and the transistors included in the nth output control circuit are p-type transistors, the difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; so that when the potential of the nth output control node is bootstrapping, the transistors included in the nth output control circuit can be turned off, to prevent leakage from the nth output control node to the first node from causing the potential of the nth output control node to not be properly pulled up, resulting in an output error.

[0230] In at least one embodiment of this invention, the effective voltage value of the control voltage can be equal to the effective voltage value of the input signal. In this case, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors, the threshold voltage of the transistor included in the nth output control circuit is set to be greater than the difference between the threshold voltages of the transistors included in the input circuit and the threshold voltage of the transistors included in the input circuit. When both the transistors included in the input circuit and the transistors included in the nth output control circuit are p-type transistors, the threshold voltage of the transistor included in the nth output control circuit is set to be less than the threshold voltage of the transistors included in the input circuit.

[0231] In at least one embodiment of this invention, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors,

[0232] The effective voltage value of the input signal is: the voltage value of the input signal when the input signal is a high voltage signal;

[0233] The effective voltage value of the control voltage is: the voltage value of the control voltage when the control voltage is high;

[0234] When both the transistors in the input circuit and the transistors in the nth output control circuit are p-type transistors,

[0235] The effective voltage value of the input signal is: the voltage value of the input signal when the input signal is a low voltage signal;

[0236] The effective voltage value of the control voltage is: the voltage value of the control voltage when the control voltage is low.

[0237] In at least one embodiment of the present invention, when both the transistor included in the nth output control circuit and the transistor included in the input circuit are n-type transistors, the channel width-to-length ratio of the transistor included in the nth output control circuit is smaller than the channel width-to-length ratio of the transistor included in the input circuit.

[0238] In practical implementation, given that the channel widths of the transistors are the same, for n-type transistors, the transistors with larger channel lengths have larger threshold voltages. Therefore, the channel width-to-length ratio of the transistors included in the nth output control circuit can be set to be smaller than the channel width-to-length ratio of the transistors included in the input circuit.

[0239] The driving circuit described in at least one embodiment of the present invention further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal.

[0240] The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node.

[0241] The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0242] In a specific implementation, the control voltage terminal may include a first control voltage terminal, and the driving circuit may further include a second node control circuit and a first node control circuit; the second node control circuit controls the potential of the first second node according to the first control voltage, and controls the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node; the first node control circuit controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0243] Optionally, the first voltage terminal can be a first low voltage terminal.

[0244] In at least one embodiment of this utility model, the driving circuit may further include N energy storage circuits;

[0245] The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal. The nth energy storage circuit is used to store electrical energy.

[0246] like Figure 1A As shown, the driving circuit of at least one embodiment of this utility model includes an input circuit 10, a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a second node control circuit 31, and a first node control circuit 32; the control voltage terminal includes a first control voltage terminal VDDA;

[0247] The input circuit 10 is electrically connected to the input terminal IS and the first node PU, and is used to control the potential of the first node PU according to the input signal provided by the input terminal IS.

[0248] The first output control circuit 11 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the first output control node PU1, respectively, and is used to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0249] The second output control circuit 12 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the second output control node PU2, respectively, and is used to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0250] The third output control circuit 13 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the third output control node PU3, respectively, and is used to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0251] The fourth output control circuit 14 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the fourth output control node PU4, respectively, and is used to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0252] The first drive output circuit 21 is electrically connected to the first output control node PU1, the first drive output terminal GT1 and the first output clock signal terminal CK1 respectively, and is used to provide the first output clock signal provided by the first output clock signal terminal CK1 to the first drive output terminal GT1 under the control of the potential of the first output control node PU1.

[0253] The second drive output circuit 22 is electrically connected to the second output control node PU2, the second drive output terminal GT2, and the second output clock signal terminal CK2, respectively, and is used to provide the second output clock signal provided by the second output clock signal terminal CK2 to the second drive output terminal GT2 under the control of the potential of the second output control node PU2.

[0254] The third drive output circuit 23 is electrically connected to the third output control node PU3, the third drive output terminal GT3 and the third output clock signal terminal CK3 respectively, and is used to provide the third output clock signal provided by the third output clock signal terminal CK3 to the third drive output terminal GT3 under the control of the potential of the third output control node PU3.

[0255] The fourth drive output circuit 24 is electrically connected to the fourth output control node PU4, the fourth drive output terminal GT4 and the fourth output clock signal terminal CK4 respectively, and is used to provide the fourth output clock signal provided by the fourth output clock signal terminal CK4 to the fourth drive output terminal GT4 under the control of the potential of the fourth output control node PU4.

[0256] The first terminal of the first energy storage circuit SC1 is electrically connected to the first output control node PU1, and the second terminal of the first energy storage circuit SC1 is electrically connected to the first drive output terminal GT1.

[0257] The first terminal of the second energy storage circuit SC2 is electrically connected to the second output control node PU2, and the second terminal of the second energy storage circuit SC2 is electrically connected to the second drive output terminal GT2.

[0258] The first terminal of the third energy storage circuit SC3 is electrically connected to the third output control node PU3, and the second terminal of the third energy storage circuit SC3 is electrically connected to the third drive output terminal GT3.

[0259] The first terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth output control node PU4, and the second terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth drive output terminal GT4.

[0260] The second node control circuit 31 is electrically connected to the first control voltage terminal VDDA, the first node PU, the first second node PDA and the first voltage terminal V1 respectively. It is used to control the potential of the first second node PDA according to the first control voltage provided by the first control voltage terminal VDDA, and control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the potential of the first node PU.

[0261] The first node control circuit 32 is electrically connected to the first second node PDA, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0262] Figure 1B yes Figure 1A The structural diagram of the first part B1 in the diagram. Figure 1C yes Figure 1A The structural diagram of the second part, B2.

[0263] like Figure 1B As shown, the first part B1 includes an input circuit 10, a first node control circuit 32, and a second node control circuit 31.

[0264] like Figure 1C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0265] The driving circuit described in at least one embodiment of the present invention further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal.

[0266] The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node.

[0267] The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0268] In a specific implementation, the control voltage terminal may include a first control voltage terminal and a second control voltage terminal, and the driving circuit may further include a two-node control circuit and a first-node control circuit; the second-node control circuit controls the potential of the first second node according to the first control voltage, and controls the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node, and controls the potential of the second second node according to the second control voltage, and controls the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node; the first-node control circuit controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0269] like Figure 2A As shown, the driving circuit of at least one embodiment of this utility model includes an input circuit 10, a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a second node control circuit 31, and a first node control circuit 32; the control voltage terminals include a first control voltage terminal VDDA and a second control voltage terminal VDDB.

[0270] The input circuit 10 is electrically connected to the input terminal IS and the first node PU, and is used to control the potential of the first node PU according to the input signal provided by the input terminal IS.

[0271] The first output control circuit 11 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the first output control node PU1, respectively. It is used to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0272] The second output control circuit 12 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the second output control node PU2, respectively. It is used to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0273] The third output control circuit 13 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the third output control node PU3, respectively. It is used to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0274] The fourth output control circuit 14 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the fourth output control node PU4, respectively. It is used to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0275] The first drive output circuit 21 is electrically connected to the first output control node PU1, the first drive output terminal GT1 and the first output clock signal terminal CK1 respectively, and is used to provide the first output clock signal provided by the first output clock signal terminal CK1 to the first drive output terminal GT1 under the control of the potential of the first output control node PU1.

[0276] The second drive output circuit 22 is electrically connected to the second output control node PU2, the second drive output terminal GT2, and the second output clock signal terminal CK2, respectively, and is used to provide the second output clock signal provided by the second output clock signal terminal CK2 to the second drive output terminal GT2 under the control of the potential of the second output control node PU2.

[0277] The third drive output circuit 23 is electrically connected to the third output control node PU3, the third drive output terminal GT3 and the third output clock signal terminal CK3 respectively, and is used to provide the third output clock signal provided by the third output clock signal terminal CK3 to the third drive output terminal GT3 under the control of the potential of the third output control node PU3.

[0278] The fourth drive output circuit 24 is electrically connected to the fourth output control node PU4, the fourth drive output terminal GT4 and the fourth output clock signal terminal CK4 respectively, and is used to provide the fourth output clock signal provided by the fourth output clock signal terminal CK4 to the fourth drive output terminal GT4 under the control of the potential of the fourth output control node PU4.

[0279] The first terminal of the first energy storage circuit SC1 is electrically connected to the first output control node PU1, and the second terminal of the first energy storage circuit SC1 is electrically connected to the first drive output terminal GT1.

[0280] The first terminal of the second energy storage circuit SC2 is electrically connected to the second output control node PU2, and the second terminal of the second energy storage circuit SC2 is electrically connected to the second drive output terminal GT2.

[0281] The first terminal of the third energy storage circuit SC3 is electrically connected to the third output control node PU3, and the second terminal of the third energy storage circuit SC3 is electrically connected to the third drive output terminal GT3.

[0282] The first terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth output control node PU4, and the second terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth drive output terminal GT4.

[0283] The second node control circuit 31 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the potential of the first second node PDA according to the first control voltage provided by the first control voltage terminal VDDA, and control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the potential of the first node PU. It is also used to control the potential of the second second node PDB according to the second control voltage provided by the second control voltage terminal VDDB, and control the connection or disconnection between the second second node PDB and the first voltage terminal V1 under the control of the potential of the first node PU.

[0284] The first node control circuit 32 is electrically connected to the first second node PDA, the second second node PDB, the first node PU, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0285] Figure 2B yes Figure 2A The structural diagram of the first part B1 in the diagram. Figure 2C yes Figure 2A The circuit diagram for part B2 of the diagram.

[0286] like Figure 2B As shown, the first part B1 includes an input circuit 10, a first node control circuit 32, and a second node control circuit 31.

[0287] like Figure 2C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0288] In at least one embodiment of this utility model, the driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; the second input circuit is electrically connected to the input terminal, the control node, and the first node respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or,

[0289] The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

[0290] like Figure 3A As shown, in Figure 1A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a control circuit 30; the input circuit includes a first input circuit 101 and a second input circuit 102.

[0291] The control circuit 30 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0292] The first input circuit 101 is electrically connected to the input terminal IS and the control node P1 respectively, and is used to control the potential of the control node P1 according to the input signal;

[0293] The second input circuit 102 is electrically connected to the input terminal IS, the control node P1 and the first node PU respectively, and is used to control the connection or disconnection between the control node P1 and the first node PU under the control of the input signal. Figure 3A In at least one embodiment of the driving circuit shown, during operation, the control circuit 30 controls the potential of the control node P1 under the control of the potential of the first node PU; and the input circuit is configured to include a first input circuit 101 and a second input circuit 102, which are electrically connected to each other through the control node P1. By controlling the potential of the control node P1, during the drive output stage, the leakage current of the transistors included in the input circuit is reduced, which helps to maintain the potential of the first node PU.

[0294] Figure 3B yes Figure 3A The structural diagram of the first part B1 in the diagram. Figure 3C yes Figure 3A The structural diagram of the second part, B2.

[0295] like Figure 3B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first node control circuit 32, and a second node control circuit 31.

[0296] like Figure 3C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0297] like Figure 4A As shown, in Figure 2A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a control circuit 30; the input circuit includes a first input circuit 101 and a second input circuit 102.

[0298] The control circuit 30 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0299] The first input circuit 101 is electrically connected to the input terminal IS and the control node P1 respectively, and is used to control the potential of the control node P1 according to the input signal;

[0300] The second input circuit 102 is electrically connected to the input terminal IS, the control node P1 and the first node PU respectively, and is used to control the connection or disconnection between the control node P1 and the first node PU under the control of the input signal.

[0301] Figure 4A In at least one embodiment of the driving circuit shown, during operation, the control circuit 30 controls the potential of the control node P1 under the control of the potential of the first node PU; and the input circuit is configured to include a first input circuit 101 and a second input circuit 102, which are electrically connected to each other through the control node P1. By controlling the potential of the control node P1, during the drive output stage, the leakage current of the transistors included in the input circuit is reduced, which helps to maintain the potential of the first node PU.

[0302] Figure 4B yes Figure 4A The structural diagram of the first part B1 in the diagram. Figure 4C yes Figure 4A The structural diagram of the second part, B2.

[0303] like Figure 4B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first node control circuit 32, and a second node control circuit 31.

[0304] like Figure 4C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0305] like Figure 5A As shown, in Figure 1A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a control circuit;

[0306] The input circuit includes a first input circuit 101 and a second input circuit 102;

[0307] The control circuit includes a first control circuit 301 and a second control circuit 302;

[0308] The first control circuit 301 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0309] The second control circuit 302 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the intermediate node Z1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU.

[0310] The first input circuit 101 is electrically connected to the input terminal IS and the intermediate node Z1 respectively, and is used to control the potential of the intermediate node Z1 according to the input signal;

[0311] The second input circuit 102 is electrically connected to the input terminal IS, the intermediate node Z1 and the first node PU respectively, and is used to control the connection or disconnection between the intermediate node Z1 and the first node PU under the control of the input signal.

[0312] Figure 5A In at least one embodiment of the driving circuit shown, when in operation, the control circuit includes a first control circuit 301 and a second control circuit 302. The first control circuit 301, under the control of the potential of the first node PU, controls the connection or disconnection between the power supply voltage terminal VDD and the control node P1. The second control circuit 302, under the control of the potential of the first node PU, controls the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1. By controlling the potential of the intermediate node Z1, the leakage current of the transistors included in the input circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0313] Figure 5B yes Figure 5A The structural diagram of the first part B1 in the diagram. Figure 5C yes Figure 5A The structural diagram of the second part, B2.

[0314] like Figure 5B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 32, and a second node control circuit 31.

[0315] like Figure 5CAs shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0316] like Figure 6A As shown, in Figure 2A Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a control circuit;

[0317] The input circuit includes a first input circuit 101 and a second input circuit 102;

[0318] The control circuit includes a first control circuit 301 and a second control circuit 302;

[0319] The first control circuit 301 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0320] The second control circuit 302 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the intermediate node Z1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU.

[0321] The first input circuit 101 is electrically connected to the input terminal IS and the intermediate node Z1 respectively, and is used to control the potential of the intermediate node Z1 according to the input signal;

[0322] The second input circuit 102 is electrically connected to the input terminal IS, the intermediate node Z1 and the first node PU respectively, and is used to control the connection or disconnection between the intermediate node Z1 and the first node PU under the control of the input signal.

[0323] Figure 6AIn at least one embodiment of the driving circuit shown, when in operation, the control circuit includes a first control circuit 301 and a second control circuit 302. The first control circuit 301, under the control of the potential of the first node PU, controls the connection or disconnection between the power supply voltage terminal VDD and the control node P1. The second control circuit 302, under the control of the potential of the first node PU, controls the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1. By controlling the potential of the intermediate node Z1, the leakage current of the transistors included in the input circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0324] Figure 6B yes Figure 6A The structural diagram of the first part B1 in the diagram. Figure 6C yes Figure 6A The structural diagram of the second part, B2.

[0325] like Figure 6B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 32, and a second node control circuit 31.

[0326] like Figure 6C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0327] In at least one embodiment of the present invention, the control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit;

[0328] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0329] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

[0330] like Figure 7A As shown, in Figure 3ABased on at least one embodiment of the driving circuit shown, the first node control circuit includes a first first node control circuit 321 and a second first node control circuit 322.

[0331] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0332] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0333] Figure 7A In at least one embodiment of the driving circuit shown, when in operation, the first first node control circuit 321 controls the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA; by controlling the potential of the control node P1, the leakage current of the transistor included in the first first node control circuit 321 can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0334] Figure 7B yes Figure 7A The structural diagram of the first part B1 in the diagram. Figure 7C yes Figure 7A The structural diagram of the second part, B2.

[0335] like Figure 7B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first node control circuit 321, a second node control circuit 322, and a second node control circuit 31.

[0336] like Figure 7C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0337] like Figure 8A As shown, in Figure 5ABased on at least one embodiment of the driving circuit shown, the first node control circuit includes a first first node control circuit 321 and a second first node control circuit 322.

[0338] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0339] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0340] Figure 8A In at least one embodiment of the driving circuit shown, when in operation, the first node control circuit 321 controls the connection or disconnection between the first node PU and the control node P1 under the control of the potential of the first second node PDA; by controlling the potential of the control node P1, the leakage current of the transistor included in the first node control circuit 321 can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0341] Figure 8B yes Figure 8A The structural diagram of the first part B1 in the diagram. Figure 8C yes Figure 8A The structural diagram of the second part, B2.

[0342] like Figure 8B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 321, a second node control circuit 322, and a second node control circuit 31.

[0343] like Figure 8C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0344] In at least one embodiment of the present invention, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit;

[0345] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0346] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node;

[0347] The third first node control circuit is electrically connected to the second second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node.

[0348] The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

[0349] In specific implementation, the control voltage terminal may include a first control voltage terminal and a second control voltage terminal; the first node control circuit may include a first first node control circuit, a second first node control circuit, a third first node control circuit, and a fourth first node control circuit; the first first node control circuit, under the potential control of the first second node, controls the connection or disconnection between the first node and the control node; the second first node control circuit, under the potential control of the first second node, controls the connection or disconnection between the control node and the first voltage terminal; the third first node control circuit, under the potential control of the second second node, controls the connection or disconnection between the first node and the control node; the fourth first node control circuit, under the potential control of the second second node, controls the connection or disconnection between the control node and the first voltage terminal. In at least one embodiment of this utility model, the driving circuit reduces the leakage current of the transistors included in the first first node control circuit and the third first node control circuit by setting the potential of the control node P1, thereby facilitating the maintenance of the first node's potential.

[0350] like Figure 9A As shown, in Figure 4A Based on at least one embodiment of the driving circuit shown, the first node control circuit includes a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, and a fourth first node control circuit 324.

[0351] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0352] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0353] The third first node control circuit 323 is electrically connected to the second second node PDB, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the second second node PDB.

[0354] The fourth first node control circuit 324 is electrically connected to the second second node PDB, the control node P1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0355] Figure 9A In at least one embodiment of the driving circuit shown, during operation, the first first node control circuit 321, under the potential control of the first second node PDA, controls the connection or disconnection between the first node PU and the control node P1; the third first node control circuit 323, under the potential control of the second second node PDB, controls the connection or disconnection between the first node PU and the control node P1; by controlling the potential of the control node P1, the leakage current of the transistors included in the first first node control circuit 321 and the leakage current of the transistors included in the third first node control circuit 323 can be reduced, which is beneficial to maintaining the potential of the first node PU.

[0356] Figure 9B yes Figure 9A The structural diagram of the first part B1 in the diagram. Figure 9C yes Figure 9AThe structural diagram of the second part, B2.

[0357] like Figure 9B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, and a second node control circuit 31.

[0358] like Figure 9C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0359] like Figure 10A As shown, in Figure 6A Based on at least one embodiment of the driving circuit shown, the first node control circuit includes a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, and a fourth first node control circuit 324.

[0360] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0361] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0362] The third first node control circuit 323 is electrically connected to the second second node PDB, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the second second node PDB.

[0363] The fourth first node control circuit 324 is electrically connected to the second second node PDB, the control node P1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0364] Figure 10A In at least one embodiment of the driving circuit shown, during operation, the first first node control circuit 321, under the potential control of the first second node PDA, controls the connection or disconnection between the first node PU and the control node P1; the third first node control circuit 323, under the potential control of the second second node PDB, controls the connection or disconnection between the first node PU and the control node P1; by controlling the potential of the control node P1, the leakage current of the transistors included in the first first node control circuit 321 and the leakage current of the transistors included in the third first node control circuit 323 can be reduced, which is beneficial to maintaining the potential of the first node PU.

[0365] Figure 10B yes Figure 10A The structural diagram of the first part B1 in the diagram. Figure 10C yes Figure 10A The structural diagram of the second part, B2.

[0366] like Figure 10B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, and a second node control circuit 31.

[0367] like Figure 10C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0368] The driving circuit described in at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit.

[0369] The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal.

[0370] The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

[0371] In a specific implementation, the driving circuit may further include a first node reset circuit; the first node reset circuit may include a first first node reset circuit and a second first node reset circuit; the first first node reset circuit, under the control of the reset control signal, controls the connection or disconnection between the first node and the control node; the second first node reset circuit, under the control of the reset control signal, controls the connection or disconnection between the control node and the first voltage terminal. By setting the potential of the control node, the leakage current of the transistor included in the first first node reset circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0372] The driving circuit described in at least one embodiment of this utility model further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit.

[0373] The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal.

[0374] The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

[0375] In specific implementations, the driving circuit described in at least one embodiment of this utility model may further include a frame reset circuit; the frame reset circuit may include a first frame reset circuit and a second frame reset circuit; the first frame reset circuit, under the control of the frame reset signal, controls the connection or disconnection between the first node and the control node; the second frame reset circuit, under the control of the frame reset signal, controls the connection or disconnection between the control node and the first voltage terminal. By setting the potential of the control node, the leakage current of the transistor included in the first frame reset circuit can be reduced during the driving output stage, which is beneficial to maintaining the potential of the first node PU.

[0376] like Figure 11A As shown, in Figure 7ABased on at least one embodiment of the driving circuit described above, the driving circuit of at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0377] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0378] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0379] The driving circuit described in at least one embodiment of this utility model further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0380] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0381] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0382] Figure 11B yes Figure 11A The structural diagram of the first part B1 in the diagram. Figure 11C yes Figure 11A The structural diagram of the second part, B2.

[0383] like Figure 11B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0384] like Figure 11CAs shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0385] like Figure 12A As shown, in Figure 8A Based on at least one embodiment of the driving circuit described above, the driving circuit of at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0386] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0387] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0388] The driving circuit described in at least one embodiment of this utility model further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0389] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0390] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0391] Figure 12B yes Figure 12A The structural diagram of the first part B1 in the diagram. Figure 12C yes Figure 12A The structural diagram of the second part, B2.

[0392] like Figure 12B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0393] like Figure 12C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0394] like Figure 13A As shown, in Figure 9A Based on at least one embodiment of the driving circuit described above, the driving circuit of at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0395] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0396] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0397] The driving circuit described in at least one embodiment of this utility model further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0398] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0399] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0400] Figure 13B yes Figure 13A The structural diagram of the first part B1 in the diagram. Figure 13C yes Figure 13A The structural diagram of the second part, B2.

[0401] like Figure 13B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0402] like Figure 13C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0403] like Figure 14A As shown, in Figure 10A Based on at least one embodiment of the driving circuit described above, the driving circuit of at least one embodiment of the present invention further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0404] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0405] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0406] The driving circuit described in at least one embodiment of this utility model further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0407] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0408] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0409] Figure 14B yes Figure 14A The structural diagram of the first part B1 in the diagram. Figure 14C yes Figure 14A The structural diagram of the second part, B2.

[0410] like Figure 14B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0411] like Figure 14C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0412] The driving circuit described in at least one embodiment of this utility model further includes N output reset circuits;

[0413] The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

[0414] In a specific implementation, the driving circuit may further include N output reset circuits. The nth output reset circuit controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the first second node.

[0415] The driving circuit described in at least one embodiment of this utility model further includes N output reset circuits;

[0416] The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

[0417] In a specific implementation, the driving circuit may further include N output reset circuits; the nth output reset circuit controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the first second node, and controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the second second node.

[0418] Optionally, the second voltage terminal can be a second low voltage terminal.

[0419] The driving circuit described in at least one embodiment of this utility model further includes a carry output circuit and a carry energy storage circuit;

[0420] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0421] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0422] In a specific implementation, the driving circuit may further include a carry output circuit; under the control of the potential of the first node, the carry output circuit provides a carry clock signal to the carry output terminal, and under the control of the potential of the first and second nodes, provides a first voltage signal to the carry output terminal.

[0423] In at least one embodiment of this utility model, the carry signal provided by the carry output terminal can be used for cascading.

[0424] The driving circuit described in at least one embodiment of this utility model may further include a carry output circuit, a carry output control circuit, and a carry energy storage circuit.

[0425] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0426] The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal.

[0427] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0428] In at least one embodiment of this utility model, a carry output control circuit can be added, wherein the carry output circuit provides a carry clock signal to the carry output terminal under the potential control of the carry output node;

[0429] When both the transistors in the carry-out control circuit and the transistors in the input circuit are n-type transistors, the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is set to be greater than the difference between the effective voltage of the first control voltage and the effective voltage of the input signal. When both the transistors in the carry-out control circuit and the transistors in the input circuit are p-type transistors, the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is set to be less than the difference between the effective voltage of the first control voltage and the effective voltage of the input signal. This ensures that when the potential of the carry-out node is bootstrapping, the transistors in the carry-out control circuit can be turned off to prevent leakage from the carry-out node to the first node from causing the potential of the carry-out node to not be properly pulled up, resulting in an incorrect carry signal output.

[0430] Optionally, the driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit;

[0431] The second node setting circuit is electrically connected to the input terminal, the first second node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first second node and the first voltage terminal under the control of the input signal provided by the input terminal.

[0432] The driving circuit described in at least one embodiment of this utility model further includes a carry output circuit and a carry energy storage circuit;

[0433] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the second second node.

[0434] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0435] In a specific implementation, the driving circuit may further include a carry output circuit; the carry output circuit provides a carry clock signal to the carry output terminal under the control of the potential of the first node, provides a first voltage signal to the carry output terminal under the control of the potential of the first second node, and provides a first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0436] The driving circuit described in at least one embodiment of this utility model may further include a carry output circuit, a carry output control circuit, and a carry energy storage circuit.

[0437] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0438] The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal.

[0439] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0440] In at least one embodiment of this utility model, a carry output control circuit can be added, wherein the carry output circuit provides a carry clock signal to the carry output terminal under the potential control of the carry output node;

[0441] When both the transistors included in the carry-out control circuit and the transistors included in the input circuit are n-type transistors, the difference between the threshold voltage of the first carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the second carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0442] When both the transistors included in the carry-out control circuit and the transistors included in the input circuit are p-type transistors, the difference between the threshold voltage of the first carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the second carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0443] This ensures that when the potential of the carry output node is bootstrapping, the transistors included in the carry output control circuit can be turned off to prevent leakage current from the carry output node to the first node from causing the potential of the carry output node to not be properly pulled up, resulting in an incorrect carry signal output.

[0444] Optionally, the driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit;

[0445] The second node setting circuit is electrically connected to the input terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the connection or disconnection between the first second node and the first voltage terminal under the control of the input signal provided by the input terminal, and to control the connection or disconnection between the second second node and the first voltage terminal.

[0446] like Figure 15A As shown, in Figure 11A Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0447] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0448] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0449] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0450] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0451] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0452] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0453] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0454] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0455] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0456] Figure 15B yes Figure 15A The structural diagram of the first part B1 in the diagram. Figure 15C yes Figure 15A The structural diagram of the second part, B2.

[0457] like Figure 15B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0458] like Figure 15C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0459] Figure 15DAt least one embodiment of the driving circuit shown is Figure 15A The differences between at least one embodiment of the driving circuit shown are as follows:

[0460] The driving circuit described in at least one embodiment of this utility model further includes a carry output control circuit 150;

[0461] The carry output circuit 70 is not electrically connected to the first node PU, but is electrically connected to the carry output node PU0. It is used to provide the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT under the control of the potential of the carry output node PU0.

[0462] The first terminal of the carry energy storage circuit 80 is electrically connected to the carry output node PU0.

[0463] The carry-out control circuit 150 is electrically connected to the first control voltage terminal VDDA, the carry-out node PU0, and the first node PU, respectively, and is used to control the connection or disconnection between the carry-out node PU0 and the first node PU under the control of the first control voltage provided by the first control voltage terminal VDDA. Figure 15D The structural diagram of the first part B1 is as follows: Figure 15B As shown, Figure 15D The structural diagram of the second part B2 is as follows: Figure 15E As shown.

[0464] like Figure 16A As shown, in Figure 12A Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0465] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0466] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0467] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0468] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0469] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0470] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0471] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0472] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0473] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0474] Figure 16B yes Figure 16A The structural diagram of the first part B1 in the diagram. Figure 16C yes Figure 16A The structural diagram of the second part, B2.

[0475] like Figure 16BAs shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0476] like Figure 16C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0477] like Figure 17A As shown, in Figure 13A Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0478] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0479] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0480] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0481] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0482] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0483] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0484] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0485] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0486] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0487] Figure 17B yes Figure 17A The structural diagram of the first part B1 in the diagram. Figure 17C yes Figure 17A The structural diagram of the second part, B2.

[0488] like Figure 17B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0489] like Figure 17C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0490] like Figure 18A As shown, in Figure 14A Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0491] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0492] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0493] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0494] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0495] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0496] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0497] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0498] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0499] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0500] Figure 18B yes Figure 18A The structural diagram of the first part B1 in the diagram. Figure 18C yes Figure 18A The structural diagram of the second part, B2.

[0501] like Figure 18B As shown, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0502] like Figure 18C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0503] like Figure 19A As shown, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this utility model may further include a first node reset circuit 41 and a frame reset circuit 51.

[0504] The first node reset circuit 41 is electrically connected to the reset control terminal RST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the reset control signal provided by the reset control terminal RST.

[0505] The frame reset circuit 51 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0506] The driving circuit described in at least one embodiment of this utility model further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, and a fourth output reset circuit 64;

[0507] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0508] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0509] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0510] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0511] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0512] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0513] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0514] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0515] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0516] Figure 19B yes Figure 19A The structural diagram of the first part B1 in the diagram. Figure 19C yes Figure 19A The structural diagram of the second part, B2.

[0517] like Figure 19B As shown, the first part B1 includes an input circuit 10, a first node control circuit 32, a first node reset circuit 41, a frame reset circuit 51, a second node control circuit 31, and a second node set circuit 71.

[0518] like Figure 19C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0519] like Figure 20A As shown, in Figure 2ABased on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of the present invention may further include a first node reset circuit 41 and a frame reset circuit 51.

[0520] The first node reset circuit 41 is electrically connected to the reset control terminal RST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the reset control signal provided by the reset control terminal RST.

[0521] The frame reset circuit 51 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0522] The driving circuit described in at least one embodiment of this utility model further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, and a fourth output reset circuit 64;

[0523] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0524] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0525] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0526] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0527] The driving circuit described in at least one embodiment of the present invention further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0528] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0529] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0530] The driving circuit described in at least one embodiment of the present invention may further include a second node setting circuit 71;

[0531] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0532] Figure 20B yes Figure 20A The structural diagram of the first part B1 in the diagram. Figure 20C yes Figure 20A The structural diagram of the second part, B2.

[0533] like Figure 20BAs shown, the first part B1 includes an input circuit 10, a first node control circuit 32, a first node reset circuit 41, a frame reset circuit 51, a second node control circuit 31, and a second node set circuit 71.

[0534] like Figure 20C As shown, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0535] Optionally, the input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node;

[0536] The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; the gate of the nth second transistor is electrically connected to the second control voltage terminal, the first electrode of the nth second transistor is electrically connected to the nth output control node, and the second electrode of the nth second transistor is electrically connected to the first node.

[0537] Optionally, the control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or...

[0538] The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

[0539] Optionally, the second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor;

[0540] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0541] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0542] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0543] Optionally, the second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor.

[0544] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0545] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0546] The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node;

[0547] The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal.

[0548] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0549] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0550] Optionally, the first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor;

[0551] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0552] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0553] Optionally, the first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor.

[0554] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0555] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0556] The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node.

[0557] The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

[0558] Optionally, the first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor;

[0559] The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node.

[0560] The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

[0561] Optionally, the first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor;

[0562] The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node.

[0563] The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

[0564] Optionally, the nth output reset circuit includes an nth output reset transistor;

[0565] The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

[0566] Optionally, the nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor;

[0567] The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal.

[0568] The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

[0569] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry energy storage circuit includes a carry capacitor;

[0570] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0571] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0572] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0573] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; and the carry energy storage circuit includes a carry capacitor.

[0574] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0575] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0576] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0577] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0578] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry energy storage circuit includes a carry capacitor.

[0579] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0580] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0581] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0582] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0583] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor.

[0584] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0585] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0586] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0587] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0588] The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node.

[0589] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0590] Optionally, the nth drive output circuit includes an nth drive output transistor and an nth output capacitor;

[0591] The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal.

[0592] The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

[0593] like Figure 21A As shown, in Figure 19A Based on at least one embodiment of the driving circuit shown, the input circuit includes an input transistor MI;

[0594] The gate and source of the input transistor MI are electrically connected to the input terminal IS, and the drain of the input transistor MI is electrically connected to the first node PU.

[0595] The control voltage terminal includes a first control voltage terminal VDDA;

[0596] The first output control circuit includes a first transistor M11;

[0597] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0598] The second output control circuit includes a second first transistor M21;

[0599] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0600] The third output control circuit includes a third first transistor M31;

[0601] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0602] The fourth output control circuit includes a fourth first transistor M41;

[0603] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0604] The second node control circuit includes a third transistor M3 and a fourth transistor M4, and the first node control circuit includes a fifth transistor M;

[0605] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0606] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0607] The gate of M5 is electrically connected to the first second node PDA, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0608] The first node reset circuit includes a ninth transistor M9;

[0609] The gate of M9 is electrically connected to the reset control terminal RST, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0610] The frame reset circuit includes a tenth transistor M10;

[0611] The gate of M10 is electrically connected to the frame reset terminal TRST, the source of M10 is electrically connected to the first node PU, and the drain of M10 is electrically connected to the first low voltage terminal.

[0612] The second node setting circuit includes an eleventh transistor M011;

[0613] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0614] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0615] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0616] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0617] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0618] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0619] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0620] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0621] The first output reset circuit includes a first output reset transistor MR1;

[0622] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0623] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0624] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0625] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0626] The second output reset circuit includes a second output reset transistor MR2;

[0627] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0628] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0629] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0630] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0631] The first output reset circuit includes a third output reset transistor MR3;

[0632] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0633] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0634] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0635] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0636] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0637] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0638] exist Figure 21A In at least one embodiment shown, all transistors are n-type transistors.

[0639] exist Figure 21A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MI to prevent leakage from the first output control node PU1 to the first node PU.

[0640] The threshold voltage of M21 is greater than the threshold voltage of MI to prevent leakage from the second output control node PU2 to the first node PU.

[0641] The threshold voltage of M31 is greater than the threshold voltage of MI to prevent leakage from the third output control node PU3 to the first node PU.

[0642] The threshold voltage of M41 is greater than the threshold voltage of MI to prevent leakage from the fourth output control node PU4 to the first node PU.

[0643] Figure 21AIn at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage when the first control voltage provided by VDDA is a high voltage. The threshold voltage of M11 is set to be greater than the threshold voltage of MI, the threshold voltage of M21 is set to be greater than the threshold voltage of MI, the threshold voltage of M31 is set to be greater than the threshold voltage of MI, and the threshold voltage of M41 is set to be greater than the threshold voltage of MI. This ensures that when the potentials of PU1, PU2, PU3, and PU4 are bootstrap, M11, M21, M31, and M41 are turned off to prevent leakage from PU1 to PU4. Leakage from PU2 to PU, from PU3 to PU, and from PU4 to PU prevents the maintenance of high potentials for PU1, PU2, PU3, and PU4, leading to output errors. The potentials of PU are V0-Vthi. Vdda-V0+Vthi is set to be less than Vth11, Vdda-V0+Vthi to be less than Vth21, Vdda-V0+Vthi to be less than Vth31, and Vdda-V0+Vthi to be less than Vth41. When the potentials of PU1, PU2, PU3, and PU4 rise automatically, M11, M21, M31, and M41 are turned off. Here, Vthi is the threshold voltage of MI, Vth11 is the threshold voltage of M11, Vth21 is the threshold voltage of M21, Vth31 is the threshold voltage of M31, and Vth41 is the threshold voltage of M41.

[0644] This utility model Figure 21A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0645] In this utility model Figure 21A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0646] Figure 21B yes Figure 21A The structural diagram of the first part B1 in the diagram. Figure 21C yes Figure 21A The structural diagram of the second part, B2.

[0647] like Figure 21B As shown, the first part B1 includes MI, M3, M4, M5, M9, M10 and M011;

[0648] like Figure 21C As shown, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0649] In this utility model Figure 21A In at least one embodiment of the driving circuit shown, VDDA can be used to provide a high voltage signal.

[0650] In this utility model Figure 21A In at least one embodiment of the driving circuit shown, the channel width-to-length ratio of M3 can be smaller than that of M4, so that when M3 and M4 are turned on at the same time, the potential of PU is low.

[0651] This utility model Figure 21A In at least one embodiment of the driving circuit shown, VDDA provides a high voltage signal during operation; a frame display time may include an input phase, an output phase, and a reset phase set sequentially.

[0652] During the input phase, IS provides a high voltage signal, RST and TRST provide low voltage signals, MI is turned on, PU and IS are connected, and the potential of PU is high voltage; M4 is turned on, pulling the potential of PDA low; M11, M21, M31 and M41 are all turned on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0653] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0654] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0655] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0656] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF1 is on, CT provides a low voltage signal, MR1, MR2, MR3 and MR4 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0657] This utility model Figure 21A In at least one embodiment of the driving circuit shown, during the blank period between two display frames, TRST can provide a high voltage signal, M10 is turned on, PU has a low voltage potential, M3 is turned on, M4 is turned off, PDA has a high voltage potential, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0658] This utility model Figure 21D At least one embodiment of the driving circuit shown is related to the present invention. Figure 21A The differences between at least one embodiment of the driving circuit shown are as follows:

[0659] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01;

[0660] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0661] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0662] exist Figure 21D In at least one embodiment shown, all transistors are n-type transistors.

[0663] Figure 21D The structural diagram of the first part B1 is as follows: Figure 21B As shown, Figure 21D The structural diagram of the second part B2 is as follows: Figure 21E As shown.

[0664] This utility model Figure 21D In at least one embodiment shown, M01 is added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 being turned on when the potential of PU0 is bootstrapping.

[0665] In practical implementation, when both M01 and MI are replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI to prevent output errors caused by M01 turning on when the potential of PU0 is bootstrapping.

[0666] like Figure 22A As shown, in Figure 20A Based on at least one embodiment of the driving circuit shown, the input circuit includes an input transistor MI;

[0667] The gate and source of the input transistor MI are electrically connected to the input terminal IS, and the drain of the input transistor MI is electrically connected to the first node PU.

[0668] The control voltage terminals include a first control voltage terminal VDDA and a second control voltage terminal VDDB.

[0669] The first output control circuit includes a first transistor M11 and a first transistor M12;

[0670] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0671] The gate of M12 is electrically connected to the second control voltage terminal VDDB, the source of M12 is electrically connected to the first output control node PU1, and the drain of M12 is electrically connected to the first node PU; the threshold voltage of M12 is greater than the threshold voltage of MI.

[0672] The second output control circuit includes a second first transistor M21 and a second second transistor M22;

[0673] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0674] The gate of M22 is electrically connected to the second control voltage terminal VDDB, the source of M22 is electrically connected to the second output control node PU2, and the drain of M22 is electrically connected to the first node PU; the threshold voltage of M22 is greater than the threshold voltage of MI.

[0675] The third output control circuit includes a third first transistor M31 and a third second transistor M32;

[0676] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0677] The gate of M32 is electrically connected to the second control voltage terminal VDDB, the source of M32 is electrically connected to the third output control node PU3, and the drain of M32 is electrically connected to the first node PU; the threshold voltage of M32 is greater than the threshold voltage of MI.

[0678] The fourth output control circuit includes a fourth first transistor M41 and a fourth second transistor M42;

[0679] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0680] The gate of M42 is electrically connected to the second control voltage terminal VDDB, the source of M42 is electrically connected to the fourth output control node PU4, and the drain of M42 is electrically connected to the first node PU; the threshold voltage of M42 is greater than the threshold voltage of MI.

[0681] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7; the first node control circuit includes a fifth transistor M5 and an eighth transistor M8.

[0682] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0683] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0684] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0685] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0686] The gate of M5 is electrically connected to the first second node PDA, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0687] The gate of M8 is electrically connected to the second node PDB, the source of M8 is electrically connected to the first node PU, and the drain of M8 is electrically connected to the first low voltage terminal LVGL.

[0688] The first node reset circuit includes a ninth transistor M9;

[0689] The gate of M9 is electrically connected to the reset control terminal RST, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0690] The frame reset circuit includes a tenth transistor M10;

[0691] The gate of M10 is electrically connected to the frame reset terminal TRST, the source of M10 is electrically connected to the first node PU, and the drain of M10 is electrically connected to the first low voltage terminal.

[0692] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0693] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0694] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M12 is electrically connected to the first low voltage terminal LVGL.

[0695] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor C0.

[0696] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0697] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0698] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0699] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0700] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0701] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0702] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0703] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[0704] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[0705] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[0706] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0707] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0708] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0709] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[0710] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[0711] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[0712] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0713] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0714] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0715] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[0716] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[0717] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[0718] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0719] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0720] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0721] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[0722] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[0723] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[0724] exist Figure 22A In at least one embodiment shown, all transistors are n-type transistors.

[0725] Figure 22A In at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal;

[0726] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[0727] exist Figure 22A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MI, and the threshold voltage of M12 is greater than the threshold voltage of MI, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0728] The threshold voltage of M21 is greater than the threshold voltage of MI, and the threshold voltage of M22 is greater than the threshold voltage of MI, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0729] The threshold voltage of M31 is greater than the threshold voltage of MI, and the threshold voltage of M32 is greater than the threshold voltage of MI, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0730] The threshold voltage of M41 is greater than the threshold voltage of MI, and the threshold voltage of M42 is greater than the threshold voltage of MI, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0731] This utility model Figure 22A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0732] In this utility model Figure 22A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0733] In this utility model Figure 22AIn at least one embodiment of the driving circuit shown, when VDDA provides a high voltage signal, VDDB can provide a low voltage signal; when VDDB provides a low voltage signal, VDDA can provide a high voltage signal, and PDA and PDB work alternately.

[0734] In this utility model Figure 22A In at least one embodiment of the driving circuit shown, the channel width-to-length ratio of M4 can be greater than that of M3, and the channel width-to-length ratio of M7 can be greater than that of M6.

[0735] Figure 22B yes Figure 22A The structural diagram of the first part B1 in the diagram. Figure 22C yes Figure 22A The structural diagram of the second part, B2.

[0736] like Figure 22B As shown, the first part B1 includes MI, M3, M4, M5, M6, M7, M8, M9, M10, M011 and M012;

[0737] like Figure 22C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[0738] This utility model Figure 22A When at least one embodiment of the driving circuit shown is in operation, if VDDA provides a high voltage signal and VDDB provides a low voltage signal, a frame display time may include an input phase, an output phase and a reset phase set sequentially.

[0739] During the input phase, IS provides a high voltage signal, RST and TRST both provide low voltage signals, MI is on, PU is connected to IS, and the potential of PU is high voltage; M3 and M4 are on, and the potential of PDA is low voltage; M11, M21, M31 and M41 are all on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0740] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0741] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0742] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0743] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF1 is on, CT provides a low voltage signal, MR11, MR21, MR31 and MR41 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0744] This utility model Figure 22A In at least one embodiment of the driving circuit shown, when VDDA provides a high voltage signal and VDDB provides a low voltage signal, during the blank time period between two display frames, TRST can provide a high voltage signal, M10 is turned on, the potential of PU is low voltage, M3 is turned on, M4 is turned off, the potential of PDA is high voltage, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0745] This utility model Figure 22A In at least one embodiment of the driving circuit shown, when VDDA provides a low voltage signal and VDDB provides a high voltage signal, a frame display time may include an input phase, an output phase, and a reset phase set sequentially.

[0746] During the input phase, IS provides a high voltage signal, RST and TRST both provide low voltage signals, MI is on, PU is connected to IS, and the potential of PU is high voltage; M3 and M4 are on, and the potential of PDB is low voltage; M12, M22, M32 and M42 are all on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0747] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0748] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0749] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0750] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF2 is on, CT provides a low voltage signal, MR12, MR22, MR32 and MR42 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0751] This utility model Figure 22A In at least one embodiment of the driving circuit shown, when VDDA provides a high voltage signal and VDDB provides a low voltage signal, during the blank time period between two display frames, TRST can provide a high voltage signal, M10 is turned on, PU has a low voltage potential, M6 is turned on, M7 is turned off, PDB has a high voltage potential, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0752] This utility model Figure 22D At least one embodiment of the driving circuit shown is related to the present invention. Figure 22A The differences between at least one embodiment of the driving circuit shown are as follows:

[0753] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[0754] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0755] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[0756] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0757] exist Figure 22D In at least one embodiment shown, all transistors are n-type transistors.

[0758] Figure 22D The structural diagram of the first part B1 is as follows: Figure 22B As shown, Figure 22D The structural diagram of the second part B2 is as follows: Figure 22E As shown.

[0759] This utility model Figure 22D In at least one embodiment shown, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0760] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0761] like Figure 23A As shown, in Figure 15A Based on at least one embodiment of the driving circuit shown,

[0762] The control circuit includes a control transistor M0, the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB;

[0763] The gate of M0 is electrically connected to the first node PU, the first terminal of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the control node P1.

[0764] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the control node P1.

[0765] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the control node P1, and the drain of the MIB is electrically connected to the first node PU.

[0766] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0767] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0768] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0769] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0770] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0771] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0772] The first first node control circuit includes a first fifth transistor M15, and the second first node control circuit includes a second fifth transistor M25;

[0773] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0774] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0775] The second node control circuit includes a third transistor M3 and a fourth transistor M4;

[0776] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0777] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0778] The second node setting circuit includes an eleventh transistor M011;

[0779] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0780] The first output control circuit includes a first transistor M11;

[0781] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0782] The second output control circuit includes a second first transistor M21;

[0783] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0784] The third output control circuit includes a third first transistor M31;

[0785] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0786] The fourth output control circuit includes a fourth first transistor M41;

[0787] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0788] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0789] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0790] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0791] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0792] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0793] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0794] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0795] The first output reset circuit includes a first output reset transistor MR1;

[0796] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0797] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0798] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0799] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0800] The second output reset circuit includes a second output reset transistor MR2;

[0801] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0802] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0803] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0804] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0805] The first output reset circuit includes a third output reset transistor MR3;

[0806] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0807] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0808] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0809] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0810] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0811] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0812] exist Figure 23A In at least one embodiment shown, all transistors are n-type transistors.

[0813] Figure 23B yes Figure 23A The structural diagram of the first part B1 in the diagram. Figure 23C yes Figure 23A The structural diagram of the second part, B2.

[0814] like Figure 23B As shown, the first part B1 includes MIA, MIB, M0, M3, M4, M15, M25, M19, M29, M110, M210 and M011;

[0815] like Figure 23C As shown, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0816] exist Figure 23A In at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal.

[0817] exist Figure 23A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MIA, and the threshold voltage of M11 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0818] The threshold voltage of M21 is greater than the threshold voltage of MIA, and the threshold voltage of M21 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0819] The threshold voltage of M31 is greater than the threshold voltage of MIA, and the threshold voltage of M31 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0820] The threshold voltage of M41 is greater than the threshold voltage of MIA, and the threshold voltage of M41 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0821] This utility model Figure 23A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0822] In this utility model Figure 23A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0823] In this utility model Figure 23A In at least one embodiment of the driving circuit shown, VDDA can be used to provide a high voltage signal.

[0824] This utility model Figure 23AIn at least one embodiment of the driving circuit shown, when the potential of PU is high, M0 is turned on, the potential of P1 is high, the intermediate nodes of MIA and MIB are electrically connected to P1, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, and the intermediate nodes of M15 and M25 are electrically connected to P1, so as to reduce the leakage current of MIB, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, and help maintain the potential of PU.

[0825] like Figure 24A As shown, in Figure 17A Based on at least one embodiment of the driving circuit shown,

[0826] The control circuit includes a control transistor M0, the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB;

[0827] The gate of M0 is electrically connected to the first node PU, the first terminal of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the control node P1.

[0828] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the control node P1.

[0829] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the control node P1, and the drain of the MIB is electrically connected to the first node PU.

[0830] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0831] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0832] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0833] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0834] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0835] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0836] The first first node control circuit includes a first fifth transistor M15, the second first node control circuit includes a second fifth transistor M25; the third first node control circuit includes a first eighth transistor M18, and the fourth first node control circuit includes a second eighth transistor M28.

[0837] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0838] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0839] The gate of M18 is electrically connected to the second node PDB, the source of M18 is electrically connected to the first node PU, and the drain of M18 is electrically connected to the control node P1.

[0840] The gate of M28 is electrically connected to the second node PDB, the source of M28 is electrically connected to the control node P1, and the drain of M28 is electrically connected to the first low voltage terminal LVGL.

[0841] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7;

[0842] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0843] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0844] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0845] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0846] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0847] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0848] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M012 is electrically connected to the first low voltage terminal LVGL.

[0849] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor.

[0850] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0851] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0852] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0853] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0854] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0855] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0856] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0857] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[0858] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[0859] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[0860] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0861] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0862] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0863] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[0864] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[0865] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[0866] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0867] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0868] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0869] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[0870] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[0871] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[0872] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0873] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0874] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0875] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[0876] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[0877] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[0878] exist Figure 24A In at least one embodiment shown, all transistors are n-type transistors.

[0879] Figure 24B yes Figure 24A The structural diagram of the first part B1 in the diagram. Figure 24C yes Figure 24A The structural diagram of the second part, B2.

[0880] like Figure 24BAs shown, the first part B1 includes MIA, MIB, M0, M3, M4, M15, M25, M6, M7, M18, M28, M19, M29, M110, M210, M011 and M012;

[0881] like Figure 24C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[0882] Figure 24A In at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal;

[0883] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[0884] exist Figure 24A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MIA, the threshold voltage of M11 is greater than the threshold voltage of MIB, the threshold voltage of M12 is greater than the threshold voltage of MIA, and the threshold voltage of M12 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0885] The threshold voltage of M21 is greater than the threshold voltage of MIA, the threshold voltage of M21 is greater than the threshold voltage of MIB, the threshold voltage of M22 is greater than the threshold voltage of MIA, and the threshold voltage of M22 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0886] The threshold voltage of M31 is greater than the threshold voltage of MIA, the threshold voltage of M31 is greater than the threshold voltage of MIB, the threshold voltage of M32 is greater than the threshold voltage of MIA, and the threshold voltage of M32 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0887] The threshold voltage of M41 is greater than the threshold voltage of MIA, the threshold voltage of M41 is greater than the threshold voltage of MIB, the threshold voltage of M42 is greater than the threshold voltage of MIA, and the threshold voltage of M42 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0888] This utility model Figure 24A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0889] In this utility model Figure 24A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0890] This utility model Figure 24A At least one embodiment of the driving circuit shown, when in operation,

[0891] When the potential of PU is high, M0 is turned on, and the potential of P1 is high.

[0892] The intermediate nodes of MIA and MIB are electrically connected to P1, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, the intermediate nodes of M15 and M25 are electrically connected to P1, and the intermediate nodes of M18 and M28 are electrically connected to P1 to reduce leakage current in MIB, M19, M110, M15, and M18, thereby helping to maintain the potential of PU.

[0893] This utility model Figure 24D At least one embodiment of the driving circuit shown is related to the present invention. Figure 24A The differences between at least one embodiment of the driving circuit shown are as follows:

[0894] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[0895] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0896] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[0897] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0898] exist Figure 24DIn at least one embodiment shown, all transistors are n-type transistors.

[0899] Figure 24D The structural diagram of the first part B1 is as follows: Figure 24B As shown, Figure 24D The structural diagram of the second part B2 is as follows: Figure 24E As shown.

[0900] This utility model Figure 24D In at least one embodiment shown, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0901] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0902] like Figure 25A As shown, in Figure 16A Based on at least one embodiment of the driving circuit shown,

[0903] The first control circuit includes a first control transistor MOA, and the second control circuit includes a second control transistor MOB; the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0904] The gate of MOA is electrically connected to the first node PU, the source of MOA is electrically connected to the power supply voltage terminal VDD, and the drain of MOA is electrically connected to the control node P1.

[0905] The gate of MOSFET is electrically connected to the first node PU, the source of MOSFET is electrically connected to the power supply voltage terminal VDD, and the drain of MOSFET is electrically connected to the intermediate node Z1.

[0906] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the intermediate node Z1.

[0907] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the intermediate node Z1, and the drain of the MIB is electrically connected to the first node PU.

[0908] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0909] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0910] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0911] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0912] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0913] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0914] The first first node control circuit includes a first fifth transistor M15, and the second first node control circuit includes a second fifth transistor M25;

[0915] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0916] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0917] The second node control circuit includes a third transistor M3 and a fourth transistor M4;

[0918] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0919] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0920] The second node setting circuit includes an eleventh transistor M011;

[0921] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0922] The first output control circuit includes a first transistor M11;

[0923] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0924] The second output control circuit includes a second first transistor M21;

[0925] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0926] The third output control circuit includes a third first transistor M31;

[0927] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0928] The fourth output control circuit includes a fourth first transistor M41;

[0929] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0930] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0931] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0932] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0933] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0934] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0935] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0936] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0937] The first output reset circuit includes a first output reset transistor MR1;

[0938] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0939] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0940] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0941] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0942] The second output reset circuit includes a second output reset transistor MR2;

[0943] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0944] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0945] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0946] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0947] The first output reset circuit includes a third output reset transistor MR3;

[0948] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0949] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0950] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0951] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0952] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0953] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0954] Figure 25B yes Figure 25A The structural diagram of the first part B1 in the diagram. Figure 25C yes Figure 25A The structural diagram of the second part, B2.

[0955] like Figure 25B As shown, the first part B1 includes MIA, MIB, M0A, M0B, M3, M4, M15, M25, M19, M29, M110, M210 and M011;

[0956] like Figure 25CAs shown, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0957] Figure 25A In at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage when the first control voltage provided by VDDA is a high voltage.

[0958] exist Figure 25A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MIA, and the threshold voltage of M11 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0959] The threshold voltage of M21 is greater than the threshold voltage of MIA, and the threshold voltage of M21 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0960] The threshold voltage of M31 is greater than the threshold voltage of MIA, and the threshold voltage of M31 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0961] The threshold voltage of M41 is greater than the threshold voltage of MIA, and the threshold voltage of M41 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0962] This utility model Figure 25A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0963] In this utility model Figure 25A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0964] This utility model Figure 25AIn at least one embodiment of the driving circuit shown, when the potential of PU is high, both M0A and M0B are turned on, VDD is connected to Z1, and P1 is connected to VDD. The potentials of Z1 and P1 are both high, so as to reduce the leakage current of M1B, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, and help maintain the potential of PU.

[0965] like Figure 26A As shown, in Figure 18A Based on at least one embodiment of the driving circuit shown,

[0966] The first control circuit includes a first control transistor MOA, and the second control circuit includes a second control transistor MOB; the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0967] The gate of MOA is electrically connected to the first node PU, the source of MOA is electrically connected to the power supply voltage terminal VDD, and the drain of MOA is electrically connected to the control node P1.

[0968] The gate of MOSFET is electrically connected to the first node PU, the source of MOSFET is electrically connected to the power supply voltage terminal VDD, and the drain of MOSFET is electrically connected to the intermediate node Z1.

[0969] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the intermediate node Z1.

[0970] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the intermediate node Z1, and the drain of the MIB is electrically connected to the first node PU.

[0971] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0972] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0973] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0974] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0975] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0976] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0977] The first first node control circuit includes a first fifth transistor M15, the second first node control circuit includes a second fifth transistor M25; the third first node control circuit includes a first eighth transistor M18, and the fourth first node control circuit includes a second eighth transistor M28.

[0978] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0979] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0980] The gate of M18 is electrically connected to the second node PDB, the source of M18 is electrically connected to the first node PU, and the drain of M18 is electrically connected to the control node P1; the gate of M28 is electrically connected to the second node PDB, the source of M28 is electrically connected to the control node P1, and the drain of M28 is electrically connected to the first low voltage terminal LVGL.

[0981] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7;

[0982] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0983] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0984] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0985] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0986] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0987] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0988] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M012 is electrically connected to the first low voltage terminal LVGL.

[0989] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor C0.

[0990] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0991] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0992] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0993] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0994] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0995] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0996] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0997] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[0998] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[0999] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[1000] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[1001] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[1002] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[1003] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[1004] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[1005] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[1006] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[1007] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[1008] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[1009] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[1010] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[1011] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[1012] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[1013] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[1014] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[1015] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[1016] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[1017] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[1018] Figure 26B yes Figure 26A The structural diagram of the first part B1 in the diagram. Figure 26C yes Figure 26A The structural diagram of the second part, B2.

[1019] like Figure 26BAs shown, the first part B1 includes MIA, MIB, M0A, M0B, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012;

[1020] like Figure 26C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[1021] exist Figure 26A In at least one embodiment shown, all transistors are n-type transistors.

[1022] Figure 26A In at least one embodiment shown, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal;

[1023] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[1024] exist Figure 26A In at least one embodiment shown, the threshold voltage of M11 is greater than the threshold voltage of MIA, the threshold voltage of M11 is greater than the threshold voltage of MIB, the threshold voltage of M12 is greater than the threshold voltage of MIA, and the threshold voltage of M12 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[1025] The threshold voltage of M21 is greater than the threshold voltage of MIA, the threshold voltage of M21 is greater than the threshold voltage of MIB, the threshold voltage of M22 is greater than the threshold voltage of MIA, and the threshold voltage of M22 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[1026] The threshold voltage of M31 is greater than the threshold voltage of MIA, the threshold voltage of M31 is greater than the threshold voltage of MIB, the threshold voltage of M32 is greater than the threshold voltage of MIA, and the threshold voltage of M32 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[1027] The threshold voltage of M41 is greater than the threshold voltage of MIA, the threshold voltage of M41 is greater than the threshold voltage of MIB, the threshold voltage of M42 is greater than the threshold voltage of MIA, and the threshold voltage of M42 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[1028] This utility model Figure 26A At least one embodiment of the driving circuit shown controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[1029] In this utility model Figure 26A In at least one embodiment of the driving circuit shown, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[1030] This utility model Figure 26A In at least one embodiment of the driving circuit shown, when the potential of PU is high, both MOA and MOB are turned on, VDD is connected to Z1, P1 is connected to VDD, the potentials of Z1 and P1 are both high, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, the intermediate nodes of M15 and M25 are electrically connected to P1, and the intermediate nodes of M18 and M28 are electrically connected to P1, so as to reduce the leakage current of MIB, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, reduce the leakage current of M18, and facilitate the maintenance of the potential of PU.

[1031] This utility model Figure 26D At least one embodiment of the driving circuit shown is related to the present invention. Figure 26A The differences between at least one embodiment of the driving circuit shown are as follows:

[1032] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[1033] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[1034] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[1035] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[1036] exist Figure 26D In at least one embodiment shown, all transistors are n-type transistors.

[1037] Figure 26D The structural diagram of the first part B1 is as follows: Figure 26B As shown, Figure 26D The structural diagram of the second part B2 is as follows: Figure 26E As shown.

[1038] This utility model Figure 26D In at least one embodiment shown, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[1039] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[1040] This utility model Figure 27A At least one embodiment of the driving circuit shown is related to the present invention. Figure 24A The difference in at least one embodiment of the driving circuit shown is that:

[1041] Excluding PU4, MT4, C4, GT4, M41, M42, MR41 and MR42.

[1042] This utility model Figure 27A At least one embodiment of the driving circuit shown outputs three levels of driving signals.

[1043] Figure 27B yes Figure 27A The structural diagram of the first part B1 in the diagram. Figure 27C yes Figure 27A The structural diagram of the second part, B2.

[1044] like Figure 27B As shown, the first part B1 includes MIA, MIB, M0, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012;

[1045] like Figure 27CAs shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31 and MR32.

[1046] This utility model Figure 28A At least one embodiment of the driving circuit shown is related to the present invention. Figure 27A The difference in at least one embodiment of the driving circuit shown is that:

[1047] Excluding PU3, MT3, C3, GT3, M31, M32, MR31 and MR32.

[1048] This utility model Figure 28A At least one embodiment of the driving circuit shown outputs two levels of driving signals.

[1049] Figure 28B yes Figure 28A The structural diagram of the first part B1 in the diagram. Figure 28C yes Figure 28A The structural diagram of the second part, B2.

[1050] like Figure 28B As shown, the first part B1 includes MIA, MIB, M0, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012;

[1051] like Figure 28C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21 and MR22.

[1052] This utility model Figure 29A At least one embodiment of the driving circuit shown is related to the present invention. Figure 22A The difference in at least one embodiment of the driving circuit shown is that:

[1053] Excluding PU4, MT4, C4, GT4, M41, M42, MR41 and MR42.

[1054] This utility model Figure 29A At least one embodiment of the driving circuit shown outputs three levels of driving signals.

[1055] Figure 29B yes Figure 29A The structural diagram of the first part B1 in the diagram. Figure 29C yes Figure 29A The structural diagram of the second part, B2.

[1056] like Figure 29B As shown, the first part B1 includes MI, M3, M4, M6, M7, M5, M8, M9, M10, M011 and M012;

[1057] like Figure 29C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31 and MR32.

[1058] This utility model Figure 30A At least one embodiment of the driving circuit shown is related to the present invention. Figure 29A The difference in at least one embodiment of the driving circuit shown is that:

[1059] Excluding PU3, MT3, C3, GT3, M31, M32, MR31 and MR32.

[1060] This utility model Figure 30A At least one embodiment of the driving circuit shown outputs two levels of driving signals.

[1061] The driving module described in this embodiment includes multiple stages of the aforementioned driving circuits.

[1062] Figure 30B yes Figure 30A The structural diagram of the first part B1 in the diagram. Figure 30C yes Figure 30A The structural diagram of the second part, B2.

[1063] like Figure 30B As shown, the first part B1 includes MI, M3, M4, M6, M7, M5, M8, M9, M10, M011 and M012;

[1064] like Figure 30C As shown, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21 and MR22.

[1065] like Figure 31 As shown, the first driving module can be located on the left side of the display area, and the second driving module can be located on the right side of the display area;

[1066] The first driving module may include a first-stage first driving circuit S11, a second-stage first driving circuit S21, a third-stage first driving circuit S31, and a fourth-stage first driving circuit S41.

[1067] The second drive module may include a first-stage second drive circuit S12, a second-stage second drive circuit S22, a third-stage second drive circuit S32, and a fourth-stage second drive circuit S42.

[1068] S11 is electrically connected to the first clock signal line CLK1, the third clock signal line CLK3, the fifth clock signal line CLK5, and the seventh clock signal line CLK7, respectively.

[1069] S21 is electrically connected to the ninth clock signal line CLK9, the eleventh clock signal line CLK11, the thirteenth clock signal line CLK13, and the fifteenth clock signal line CLK15, respectively.

[1070] S31 is electrically connected to the seventeenth clock signal line CLK17, the nineteenth clock signal line CLK19, the twenty-first clock signal line CLK21, and the twenty-third clock signal line CLK23, respectively.

[1071] S41 is electrically connected to the first clock signal line CLK1, the third clock signal line CLK3, the fifth clock signal line CLK5, and the seventh clock signal line CLK7, respectively.

[1072] The first drive output terminal of S11 is electrically connected to the first row of gate line G1, the second drive output terminal of S11 is electrically connected to the third row of gate line G3, the third drive output terminal of S11 is electrically connected to the fifth row of gate line G5, and the fourth drive output terminal of S11 is electrically connected to the seventh row of gate line G7.

[1073] The first drive output terminal of S21 is electrically connected to the ninth row of gate line G9, the second drive output terminal of S21 is electrically connected to the eleventh row of gate line G11, the third drive output terminal of S21 is electrically connected to the thirteenth row of gate line G13, and the fourth drive output terminal of S21 is electrically connected to the fifteenth row of gate line G15.

[1074] The first drive output terminal of S31 is electrically connected to the seventeenth row gate line G17, the sec...

Claims

1. A driving circuit, characterized in that, It includes an input circuit, N output control circuits, and N drive output circuits; N is a positive integer. The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal; The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N; The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

2. The driving circuit as described in claim 1, characterized in that, Both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or, The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

3. The driving circuit as described in claim 1, characterized in that, It also includes N energy storage circuits; The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal.

4. The driving circuit as described in claim 1, characterized in that, It also includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal; The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

5. The driving circuit as described in claim 1, characterized in that, It also includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal. The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node. The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

6. The driving circuit as described in claim 4 or 5, characterized in that, The driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; The second input circuit is electrically connected to the input terminal, the control node, and the first node, respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or, The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

7. The driving circuit as described in claim 6, characterized in that, The control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit. The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node. The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

8. The driving circuit as described in claim 6, characterized in that, The control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit; The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node. The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node; The third first node control circuit is electrically connected to the second second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node. The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

9. The driving circuit as described in claim 6, characterized in that, It also includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit; The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal. The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

10. The driving circuit as described in claim 6, characterized in that, It also includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit. The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal. The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

11. The driving circuit as described in claim 4, characterized in that, It also includes N output reset circuits; The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

12. The driving circuit as described in claim 5, characterized in that, It also includes N output reset circuits; The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

13. The driving circuit as described in claim 4, characterized in that, It also includes a carry-out output circuit, a carry-out control circuit, and a carry-out energy storage circuit; The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node. The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal. The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

14. The driving circuit as described in claim 13, characterized in that, Both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal; or, The transistors included in the input circuit and the transistors included in the carry-out control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal.

15. The driving circuit as described in claim 5, characterized in that, It also includes a carry-out output circuit, a carry-out control circuit, and a carry-out energy storage circuit; The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node. The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal. The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

16. The driving circuit as described in claim 15, characterized in that, Both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the first control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the second control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal; or... Both the transistors in the input circuit and the transistors in the carry-out control circuit are p-type transistors. The difference between the threshold voltage of the transistor whose gate is electrically connected to the first control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor whose gate is electrically connected to the second control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

17. The driving circuit as described in claim 1, characterized in that, The input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node; The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; The gate of the nth second transistor is electrically connected to the second control voltage terminal, the first terminal of the nth second transistor is electrically connected to the nth output control node, and the second terminal of the nth second transistor is electrically connected to the first node.

18. The driving circuit as described in claim 6, characterized in that, The control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or... The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

19. The driving circuit as described in claim 4, characterized in that, The second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor; The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node; The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal. The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

20. The driving circuit as described in claim 5, characterized in that, The second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor. The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node; The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal. The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node; The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal. The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal. The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

21. The driving circuit as described in claim 7, characterized in that, The first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor; The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node. The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

22. The driving circuit as described in claim 8, characterized in that, The first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor. The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node. The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal. The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node. The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

23. The driving circuit as described in claim 9, characterized in that, The first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor; The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node. The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

24. The driving circuit as described in claim 10, characterized in that, The first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor; The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node. The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

25. The driving circuit as described in claim 11, characterized in that, The nth output reset circuit includes an nth output reset transistor; The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

26. The driving circuit as described in claim 12, characterized in that, The nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor; The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal. The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

27. The driving circuit as described in claim 13, characterized in that, The carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; the carry energy storage circuit includes a carry capacitor; The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal. The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal. The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node. The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

28. The driving circuit as described in claim 15, characterized in that, The carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor; the carry energy storage circuit includes a carry capacitor. The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal. The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal. The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal. The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node. The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node. The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

29. The driving circuit as described in claim 3, characterized in that, The nth drive output circuit includes an nth drive output transistor, and the nth energy storage circuit includes an nth output capacitor; The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal. The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

30. A drive module, characterized in that, It includes multiple levels of drive circuits as described in any one of claims 1 to 29.

31. A display device, characterized in that, Includes the drive module as described in claim 30.

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