Semiconductor device

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate, a first well, a second well, an alignment mark, and an isolation layer. The semiconductor substrate includes a first fin and a second fin. The first well is in the semiconductor substrate, with the first fin in the first well, and the first well is doped with a first dopant having a first conductivity type. A second well is in the semiconductor substrate with a second fin in the second well doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material. The isolation layer is located above the first fin, the second fin, the semiconductor substrate and the alignment mark.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electrical appliances, such as personal computers, mobile phones, digital cameras, and other electronic devices. Typically, semiconductor devices are manufactured by sequentially arranging insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern each material layer to form circuit components and elements.

[0003] The semiconductor industry continuously increases the density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, enabling more electronic components to be integrated into a given area. However, with the reduction of the minimum feature size, additional problems must be addressed. Utility Model Content

[0004] In one embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a first well, a second well, an alignment mark, and an isolation layer. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is located in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is located in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material. The isolation layer is located above the first fin, the second fin, the semiconductor substrate, and the alignment mark.

[0005] In another embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a first well, a second well, and an alignment mark. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is located in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is located in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, and the first material is doped with both the first and second dopants.

[0006] In another embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a first well, a second well, and an alignment mark. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is located in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is located in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, the first material being doped with the first dopant, and the second material being undoped. Attached Figure Description

[0007] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0008] Figure 1 A three-dimensional view of an example of a nanofield-effect transistor (nanoFET) is illustrated according to some embodiments;

[0009] Figure 2 , Figure 3A , Figure 3B and Figures 4 to 9 A schematic diagram illustrating an intermediate stage in a method for fabricating a nanoFET trap and alignment marks according to some embodiments;

[0010] Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B and Figure 29C A schematic diagram illustrating an intermediate stage in a method for fabricating a nanoFET according to some embodiments.

[0011] [Symbol Explanation]

[0012] 10:Substrate

[0013] 10A: Alignment Mark Area

[0014] 10N: N-class region

[0015] 10P: P-class area

[0016] 10S: Main upper surface

[0017] 12, 14: Covering layer

[0018] 16: Trench

[0019] 18,30: Implanted veil

[0020] 24: P-type trap

[0021] 26,32: Opening

[0022] 28: P-type ion implantation process

[0023] 36: N-type ion implantation technology

[0024] 38: N-type traps

[0025] 40: Alignment Mark

[0026] 51, 51A, 51B, 51C: First semiconductor layer

[0027] 52, 52A, 52B, 52C: First nanostructure

[0028] 53, 53A, 53B, 53C: Second semiconductor layer

[0029] 54, 54A, 54B, 54C: Second nanostructures

[0030] 55: Nanostructures

[0031] 64: Multi-layer stacking

[0032] 66: Fins

[0033] 68: STI Zone

[0034] 70: Dummy Dielectric Layer

[0035] 71: Dummy Dielectric

[0036] 72: Dummy gate layer

[0037] 74: Cover Layer

[0038] 76: Dummy gate

[0039] 78: Curtain

[0040] 80: First spacer layer

[0041] 81: First spacer

[0042] 82: Second spacer layer

[0043] 83: Second spacer

[0044] 86: First concave part

[0045] 88: Side wall recess

[0046] 90: First inner spacer

[0047] 92: Epitaxial Source / Drain Region

[0048] 94: Contact Etching Termination Layer

[0049] 96: First interlayer dielectric

[0050] 98:Second recess

[0051] 100: Gate dielectric layer

[0052] 102: Gate electrode

[0053] 104: Gate Mask

[0054] 106: Interlayer dielectric

[0055] 108: The third concave part

[0056] 110: Silicification zone

[0057] 112,114: Contact Detailed Implementation

[0058] The following disclosure provides numerous different embodiments or examples for implementing various features of the described subject matter. Specific examples of elements and configurations are described below to simplify this specification. Of course, these are merely examples and not limiting. For instance, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or reference letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0059] Spatial relative terms such as “below,” “under,” “bottom,” “above,” and “top” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0060] As detailed below, embodiments disclosed herein describe a dopant implantation process for forming P-wells and / or N-wells in a substrate, a process that can be used to form transistors (e.g., nanofield-effect transistors, fin field-effect transistors (FinFETs), planar transistors, etc.). The techniques described herein involve the use of a hard implantation mask in the implantation of P-wells and / or N-wells. A hard implantation mask can avoid or reduce shrinkage during high-temperature processing and can improve the dopant distribution of P-wells and / or N-wells in the lateral direction, thus improving the junction between adjacent P-wells and N-wells, which can be desirable for transistors with small critical dimensions of P-wells or N-wells. In some embodiments, the material of the hard mask may also form alignment marks, and the material of the hard mask may contain or not contain dopants therein, allowing the alignment marks to have a variety of tunable properties that are sensitive to specific processing devices. Several embodiments are described below in a specific context, namely, a die containing nanofield-effect transistors. However, several embodiments are applicable to dies containing other types of transistors, such as replacing or incorporating nanofield-effect transistors with FinFETs, planar transistors, etc.

[0061] Figure 1A three-dimensional view of an example of a nanofield-effect transistor (e.g., a nanosheet field-effect transistor, etc.) is illustrated according to some embodiments. The nanofield-effect transistor includes a nanostructure 55 (e.g., a nanosheet, etc.) above fins 66 on a substrate 10, wherein the nanostructure 55 serves as a channel region for the nanosheet field-effect transistor. The nanostructure 55 may comprise P-type nanostructures, N-type nanostructures, or combinations thereof. An isolation region 68 is disposed between adjacent fins 66, and the fins 66 may protrude over adjacent isolation regions 68. Even though, as is done herein, the isolation region 68 is described / depicted as separate from the substrate 10, the term "substrate" may refer solely to the substrate or a combination of a semiconductor substrate and an isolation region. Additionally, even though the bottom of the fins 66 is depicted as having a single continuous material with the substrate 10, the bottom of the fins 66 and / or the substrate 10 may comprise a single material or multiple materials. In this context, the fins 66 refer to the portion extending between adjacent isolation regions 68.

[0062] The gate dielectric layer 100 is above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite side of the gate dielectric layer 100 and the gate electrode 102.

[0063] Figure 1 The following figures illustrate reference cross-sections used in the figure. Cross-section A-A' runs along the longitudinal axis of the gate dielectric layer 102 and, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the nanofield-effect transistor. Within the range of process variations, cross-section B-B' is generally perpendicular to cross-section A-A' and generally parallel to the longitudinal axis of the fins 66 of the nanofield-effect transistor and, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanofield-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the source / drain regions of the nanofield-effect transistor. For clarity, the following figures refer to these reference cross-sections.

[0064] Some of the embodiments discussed herein are discussed in the context of nanoscale field-effect transistors formed using a post-gate process. In other embodiments, a pre-gate process may also be used. Furthermore, some embodiments contemplate other devices used, such as planar field-effect transistors or FinFETs.

[0065] Figures 2 to 29C The illustration depicts several intermediate stages in the fabrication of nanofield-effect transistors according to some embodiments. Figure 2 , Figure 3A , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13 , Figure 14A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A and Figure 29A Draw Figure 1 The reference section A-A' is shown in the figure. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 19C , Figure 20B , Figure 20D , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B and Figure 29B Draw Figure 1 The reference section B-B' is shown in the figure. Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 20C , Figure 21C , Figure 26C , Figure 27C , Figure 28C and Figure 29C Draw Figure 1 The reference section C-C' is shown in the figure. Figure 11B , Figure 12B and Figure 28D Draw cross sections parallel to sections A-A' and B-B' but located at different positions within the structure, such as the positions where alignment marks are formed.

[0066] Figures 2 to 9 The illustration depicts methods for forming wells and alignment marks in a substrate according to some embodiments. This disclosure considers additional processing procedures. First, refer to... Figure 2 According to some embodiments, a substrate 10 and a mask layer 12 formed on the substrate 10 are illustrated. The substrate 10 may be, for example, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 10 may be a wafer, such as a silicon wafer. Figure 2The accompanying figures illustrate a portion of the wafer to better illustrate some of the features of the embodiments. Similar structures and processes can be applied to larger portions of the wafer. Generally, the SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer, for example, can be a buried oxide (BOX) layer or a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically silicon or glass, but other types of substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrate 10 may include silicon, germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide, or combinations thereof. In some embodiments, the mask layer 12 may include silicon oxide. The mask layer 12 may be formed from a surface layer of the oxide substrate 10 or by any deposition method, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), etc. The mask layer 12 may comprise silicon oxide or other suitable materials. In some embodiments, the mask layer 12 protects the underlying substrate 10 from or reduces damage during subsequent implantation processes. In some embodiments, the mask layer 12 may be omitted.

[0067] In some embodiments, substrate 10 includes an N-class region 10N, a P-class region 10P, and an alignment mark region 10A. The N-class region 10N may be a region for fabricating an N-class metal-oxide-semiconductor (NMOS) device. The P-class region 10P may be a region for fabricating a P-class metal-oxide-semiconductor (PMOS) device. The alignment mark region 10A may be a region for fabricating alignment marks. Alignment marks are used in a process to align substrate 10 (e.g., a wafer) to the appropriate orientation or location.

[0068] According to some embodiments, a mask layer 14 with a pattern of alignment marks is formed on a mask layer 12. According to some embodiments, the mask layer 14 can be formed using spin coating, CVD, PECVD, ALD, physical vapor deposition (PVD), etc. The mask layer may comprise silicon nitride, silicon oxynitride, titanium nitride, silicon carbide, silicon oxide, or combinations thereof. In some embodiments, the patterned mask layer 14 incorporates suitable lithography and etching techniques.

[0069] After the mask layer 14 is formed, an etching process can be performed to etch the mask layer 12 and the substrate 10 through the mask layer 14, thereby forming trenches 16 on the substrate 10 and the mask layer 12, such as... Figure 3AAs shown. In some embodiments, the depth D of the trenches 16 in the substrate 10 at the main upper surface 10S of the substrate 10 is in the range of about 100 nm to about 150 nm, for example, about 120 nm. Each trench 16 may have a width of about 1 micrometer to about 2 micrometers, for example, about 1.5 micrometers. The mask layer 14 may be removed after the trenches 16 are formed. In some embodiments, the mask layer 14 is removed by an etching process such as dry etching or wet etching. The trenches and / or any material formed therein may form alignment marks. Although Figure 3A Only three trenches 16 are shown in the figure, but the number and arrangement of trenches 16 are not limited thereto. For example, according to some embodiments, the top view of the alignment mark area 10A of the substrate 10 is as follows. Figure 3B As shown. The implantation mask 18 can be formed of a material that can substantially block ions during the implantation process. For example, the implantation mask 18 can be a hard mask material with sufficient thickness, such as silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. The implantation mask 18 can be formed by a suitable deposition technique, such as spin coating, CVD, PECVD, ALD, PVD, etc.

[0070] Reference Figure 5 An implantation mask 18 can be patterned to form an opening 26 within it. The opening 26 exposes the N-type region 10N and alignment marks 10A. The patterned implantation mask 18 may incorporate suitable lithography and etching techniques. For example, one or more photoresist layers (not shown) may be deposited on the implantation mask 18 and patterned using a suitable lithography process. Then, an etching process is performed on the patterned photoresist layers on the implantation mask 18 to form the opening 26 within it. Acceptable processes, such as ashing, can be used to remove the photoresist layers.

[0071] According to some embodiments, after forming the implantation mask 18, one or more P-type ion implantation processes 28 are performed to lightly dope the substrate 10, thereby forming one or more P-type wells 24 in the substrate 10. The P-type wells 24 can provide active regions for forming NMOS devices in the substrate 10. In some embodiments, the material of the implantation mask 18 in the trench 16 and the substrate 10 of the alignment marking region 10A is also doped with P-type dopants, which may include boron, indium, etc., or combinations thereof. In some embodiments, the P-type ion implantation process 28 includes multiple carpet implantation processes to achieve the desired doping distribution. For example, energies in the range of about 180 keV to about 240 keV and about 1 × 10⁻¹⁰ per square centimeter are available. 12 From one atom to approximately 1 × 10 13 The first P-type ion implantation process uses a dose of one atom. This first P-type atom implantation process can provide P-type regions (not shown) in a substrate that can serve as a deep P-type well. It is available with energies ranging from approximately 1 keV to approximately 100 keV and approximately 1 × 10⁻⁶ kilovolts per square centimeter. 13From one atom to approximately 1 × 10 14 A second P-type ion implantation process is performed using a dose of one atom. This second P-type atom implantation process provides a P-type region (not shown separately) in a substrate that can serve as a shallow P-type well. Even though only two P-type ion implantation processes have been described above as examples, more P-type ion implantation processes can be applied to achieve the desired dopant distribution. The P-type dopant concentration in the material of P-type well 24 and implantation mask 18 can be equal to or less than 1 × 10⁻⁶. 16 cm -3 For example, in about 1×10 15 cm -3 Up to approximately 5×10 15 cm -3 Within the range.

[0072] The first and second P-type implantation processes can be thermal implantation processes, for example, at temperatures exceeding approximately 150 degrees Celsius, such as between approximately 200 and approximately 450 degrees Celsius. Thermal implantation helps reduce gap defects generated within the substrate 10 during the implantation process. Unlike photoresist materials, the rigid masking material of the implantation mask 18 can remain unshrunk or deformed (or at least to a significantly smaller degree compared to photoresist materials) and thus retain its pattern and critical dimensions after one or more thermal implantation processes. Therefore, by using the implantation mask 18, the lateral boundaries of the P-type well 24 can be precisely controlled. Annealing can be performed to repair implantation damage and revitalize implanted impurities. Annealing can be performed at temperatures ranging from approximately 1000 to approximately 1100 degrees Celsius, such as 1050 degrees Celsius, for a duration of approximately 1 second to approximately 20 seconds, such as approximately 10 seconds.

[0073] Reference Figure 6 After the P-type well 24 is formed, an etching process is performed to remove the implantation mask 18 above the main upper surface 10S of the substrate 10. In some embodiments, the etching process may partially etch the material of the implantation mask 18 in the trench 16. The implantation mask 18 may not be completely removed by etching due to loading effects. For example, the remaining material of the implantation mask 18 in the trench 16 may have a thickness T of about 0.5 micrometers to 1 micrometer. The etching process may be an acceptable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a timed etching process, and the recess depth or thickness T may be controlled by the time of the etching process.

[0074] Reference Figure 7According to some embodiments, an implantation mask 30 is formed on the mask layer 12 and fills the trench 16. For example, a portion of the material of the implantation mask 30 may be in the trench 16 and above the material of the implantation mask 18. The implantation mask 30 is formed of a material that can substantially block ions during the implantation process. The implantation mask 30 may be a hard mask material with sufficient thickness, such as silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. The implantation mask 30 may be formed of a different material than the implantation mask 18, even if similar materials are used. The implantation mask 30 may be formed by a suitable deposition technique, such as spin coating, CVD, PECVD, ALD, PVD, etc.

[0075] Reference Figure 8 According to some embodiments, the implantation mask 30 is patterned to form an opening 32 in the implantation mask 30. The opening 32 exposes the P-type region 10P and the alignment mark region 10A. The patterned implantation mask 30 may incorporate suitable lithography and etching techniques. For example, one or more photoresist layers (not shown) may be deposited on the implantation mask 30 and patterned using a suitable lithography process. Then, an etching process is performed on the patterned photoresist layer on the implantation mask 18 to form the opening 32 in the implantation mask 30. Acceptable processes, such as ashing processes, may be used to remove the photoresist layer.

[0076] According to some embodiments, after forming the implantation mask 30, one or more N-type ion implantation processes 36 are performed to lightly dope the substrate 10, thereby forming one or more N-type wells 38 in the substrate 10. The N-type wells 38 can provide active regions for forming PMOS devices in the substrate 10. In some embodiments, the materials of the implantation mask 30 in the trench 16 and the substrate 10 in the alignment mark region 10A are also doped with N-type dopants, which may include phosphorus, arsenic, antimony, etc., or combinations thereof. In some embodiments, the N-type ion implantation process 36 includes multiple carpet implantation processes to achieve the desired doping distribution. For example, energies in the range of about 180 keV to about 240 keV and about 1 × 10⁻¹⁰ per square centimeter are available. 12 From one atom to approximately 1 × 10 13 The first N-type ion implantation process uses a dose of one atom. This first N-type atom implantation process can provide N-type regions (not shown) in substrates that can serve as deep N-type wells. It can be used with energies ranging from approximately 1 keV to approximately 150 keV and approximately 1 × 10⁻¹⁰ per square centimeter. 13 From one atom to approximately 1 × 10 14A second N-type ion implantation process is performed at a dose of one atom. This second N-type atom implantation process provides N-type regions (not shown separately) in a substrate that can serve as shallow N-type wells. Even though only two N-type ion implantation processes have been described above as examples, more N-type ion implantation processes can be applied to achieve the desired dopant distribution. The N-type dopant concentration in the material of the implantation mask 30 in the N-type well 38 and trench 16 can be equal to or less than 1 × 10⁻⁶. 16 cm -3 For example, in about 1×10 15 cm -3 Up to approximately 5×10 15 cm -3 Within the range. In some embodiments, the N-type well 38 abuts against the P-type well 24.

[0077] The first and second N-type implantation processes can be thermal implantation processes, for example, at temperatures exceeding approximately 150 degrees Celsius, such as between approximately 200 and approximately 450 degrees Celsius. Thermal implantation processes can help reduce gap defects generated within the substrate 10 during the implantation process. Unlike photoresist materials, the rigid masking material of the implantation mask 30 can remain unshrunk or deformed (or at least to a significantly smaller degree compared to photoresist materials) and thus retain its pattern and critical dimensions after one or more thermal implantation processes. Therefore, by using the implantation mask 30, the lateral boundaries of the N-type well 38 can be precisely controlled. Annealing can be performed to repair implantation damage and revitalize implanted impurities. Annealing can be performed at temperatures ranging from approximately 1000 to approximately 1100 degrees Celsius, such as 1050 degrees Celsius, for a duration of approximately 1 second to approximately 20 seconds, such as approximately 10 seconds.

[0078] Reference Figure 9 After the N-type well 38 is formed, at least one etching process is performed to remove the implantation mask 30 and mask layer 12 on the main upper surface 10S of the substrate 10. For example, the implantation mask 30 and mask layer 12 may be removed by separate etching processes. Alternatively, when the materials of the implantation mask 30 and mask layer 12 are similar, the implantation mask 30 and mask layer 12 may be removed together by a single etching process. In some embodiments, the material of the implantation mask 30 in the trench 16 is also partially or completely removed by the etching process. Any residual material of the implantation mask 30 will be flush with or below the main upper surface 10S of the substrate 10. The etching process may be an acceptable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a timed etching process, and the depth of the recess or the residual thickness of the implantation mask 30 in the trench 16 may be controlled by the timing of the etching process.

[0079] The material formation of the implantation mask 18 and implantation mask 30 in trench 16 can align the alignment marks 40 of the wafer in subsequent processes. The lower portion of the alignment marks 40 can be formed of the material of the implantation mask 18, and the upper portion of the alignment marks 40 can be formed of the material of the implantation mask 30. In some embodiments, the lower portion of the alignment marks 40 is doped with both P-class and N-class dopants, and the upper portion of the alignment marks 40 is doped with N-class dopants. Alternatively, in some embodiments, the alignment marks 40 are doped with only one type of dopant. For example, the opening 26 of the implantation mask 18 may not expose the alignment mark region 10A, so the alignment marks 40 are only doped with N-class dopants. Alternatively, the opening 32 of the implantation mask 30 may not expose the alignment mark region 10A, so the lower portion of the alignment marks 40 is only doped with P-class dopants, and the upper portion of the alignment marks 40 is undoped. In some embodiments, the substrate 10 adjacent to the alignment mark 40 in the alignment mark region 10A may be doped with dopants of the same type and concentration as the alignment mark 40. Figures 2 to 9 For illustrative purposes, a P-class well 24 is illustrated before the N-class well 38. In some embodiments, the N-class well 38 is formed before the P-class well 24, and the conductivity type of the dopant in the alignment mark 40 is opposite to that discussed in the embodiments above. For example, the lower part of the alignment mark 40 may be doped with both N-class and P-class dopant or only with N-class dopant, and the upper part of the alignment mark 40 may be doped with only P-class dopant or undoped.

[0080] even though Figures 2 to 9 Alignment mark 40 is drawn with reference to section A-A'. Alignment mark 40 may be formed in other locations, such as sections B-B' or C-C', or sections parallel to sections A-A' or B-B'. Furthermore, even if alignment mark 40 is not drawn on... Figure 1 In the illustrated nanoFET device, alignment marks 40 may be in the device region of substrate 10 and remain in the IC wafer after substrate 10 is diced; alternatively, alignment marks 40 may be in the dicing region or other non-device region and may not be present in the IC wafer after substrate 10 is diced. For illustrative purposes, in the following figures (e.g., from...) Figure 10 (Begin), align the individual markings with the marked area 10A, such as Figure 11B , Figure 12B and Figure 28D However, they are not shown separately in the accompanying drawings that show the reference section A-A'.

[0081] Additional process steps can be performed to fabricate nano-FETs. (See reference...) Figure 10A multilayer stack 64 is formed on the substrate 10. The multilayer stack 64 includes alternating first semiconductor layers 51A, 51B, and 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes and in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region for a nanoFET in a P-class region 10P. Alternatively, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region for a nanoFET in an N-class region 10N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nanoFET in an N-class region 10N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nanoFET in a P-class region 10P.

[0082] In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions in both the N-class region 10N and the P-class region 10P of the nanoFET. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions in both the N-class region 10N and the P-class region 10P of the nanoFET. In such embodiments, the N-class region 10N and the P-class region 10P may have the same material composition (e.g., silicon or other semiconductor materials) and may be formed simultaneously. Figures 29A to 29C The diagram illustrates a structure obtained from such an embodiment, wherein the channel regions in the P-class region 10P and the N-class region 10N contain, for example, silicon.

[0083] As an example, the multilayer stack 64 is illustrated as comprising three layers: a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may comprise any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as CVD, ALD, vapor phase epitaxy (VPE), molecular beam epitaxy (MLE), etc. In several embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for P-type nanoFETs, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for N-type nanoFETs, such as silicon, silicon carbide, etc. As an example, the multilayer stack 64 is illustrated such that the bottom semiconductor layer is suitable for a P-type nanoFET. In some embodiments, the multilayer stack 64 may be formed such that the bottom semiconductor layer is suitable for an N-type nanoFET. The first semiconductor layer 51 and the second semiconductor layer 53 may be doped in situ or using one or more implantation processes.

[0084] The first semiconductor material and the second semiconductor material can be materials that are highly etch-sensitive to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed in the N-type region 10N without significantly removing the second semiconductor layer 53 of the second semiconductor material, and the second semiconductor layer 53 can be patterned to form the channel region of the N-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed in the P-type region 10P without significantly removing the first semiconductor layer 51 of the first semiconductor material, and the first semiconductor layer 51 can be patterned to form the channel region of the P-type nanoFET.

[0085] Reference Figure 11A According to some embodiments, fins 66 are formed in a region of the substrate 10 and nanostructures 55 are formed in a multilayer stack 64. The fins 66 protrude from the main upper surface 10S of the substrate 10, and the range of the fins 66 is in the range of about 50 nanometers to about 70 nanometers. In some embodiments, the nanostructures 55 and fins 66 may be formed in the multilayer stack 64 and the substrate 10 respectively by means of trenches in the multilayer stack 64 and the substrate 10. In some embodiments, reference is made to... Figure 11B The alignment mark 40 may be recessed into the substrate 10 when forming the fin 66 in the P-type region 10P and the N-type region 10N. For example, at least a portion of the material of the implantation mask 30 is etched. Therefore, the top surface of the alignment mark 40 may be lower than or flush with the main upper surface 10S of the substrate 10. The material remaining in the implantation mask 30 in the trench 16 may have a thickness T2, and the thickness T2 is thinner than the thickness T1 of the material of the implantation mask 18 in the trench 16. For example, the thickness T2 may be less than about 0.5 micrometers.

[0086] The etching process for forming the fins 66 and nanostructures 55 can be any acceptable etching process, such as reactive ion etching (RIE), neutral particle beam etching (NBE), etc., or combinations thereof. The etching process can be anisotropic. Etching the multilayer stack 64 to form the nanostructures 55 can further define first nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructures 52) from the first semiconductor layer 51 and second nanostructures 54A, 54B, and 54C from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 can be further collectively referred to as nanostructures 55. Figure 11A The diagram illustrates that two fins are formed in each of the N-type region 10N and the P-type region 10P. In other embodiments, different numbers of fins may be formed in each region.

[0087] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography processes, including dual patterning and multi-patterning processes. Generally, dual or multi-patterning processes combine lithography and self-alignment processes to produce patterns with smaller perimeters than, for example, a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 66.

[0088] As an example, Figure 11A The fins 66 in the N-type and P-type regions are illustrated to have substantially equal widths. In some embodiments, the width of the fins 66 in the N-type region 10N may be greater than or thinner than the width of the fins 66 in the P-type region 10P. Furthermore, although each fin 66 and nanostructure 55 is illustrated to have a uniform width, in other embodiments, the fins 66 and / or nanostructure 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 10. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0089] exist Figure 12A and Figure 12B In some embodiments, a shallow trench isolation (STI) region 68 is formed between adjacent fins 66 and above alignment marks 40. The STI region 68 may be formed by depositing an insulating material on the substrate 10, fins 66, and nanostructure 55, between adjacent fins 66 and above alignment marks 40. The insulating material may be an oxide, such as silicon oxide, nitrides, etc., or combinations thereof, and may be formed by high-density plasma CVD (HDP-CVP), flow-through CVD (FCVD), etc., or combinations thereof. Other insulating materials formed using acceptable processes may also be used. In an example embodiment, the insulating material is silicon oxide formed by FCVD. After the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Even though the insulating material is shown as a single layer, multiple layers may be used in some embodiments. For example, in some embodiments, a pad (not shown separately) may be formed first along the main upper surface 10S of the substrate 10, the fins 66, and the nanostructure 55. Next, the filling material discussed above can be formed on the pad.

[0090] Next, a removal process is performed to remove excess insulating material from the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical planarization (CMP), etch-back processes, combinations thereof, etc., can be used. The planarization process exposes the nanostructure so that the top surface of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0091] Next, the insulating material is recessed to form STI regions 68. The insulating material is recessed such that the upper portion of the fins 66 in the N-type region 10N and the P-type region 10P protrudes between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 may have a flat surface, a raised surface, a recessed surface (such as a dish-shaped form), or a combination thereof, as illustrated. The top surface of the STI regions 68 may be formed into a flat, raised, or recessed state by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the insulating material (e.g., etching the insulating material at a rate greater than that of the fins 66 and the nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

[0092] In some embodiments, refer to Figure 12B The STI region 68 includes a filling groove 16 and covers a portion of the alignment mark 40. The alignment mark 40 will be covered by the STI region 68 and will remain substantially unmodified in subsequent processes. In some embodiments, both the material of the implantation mask 30 and the STI region are formed of oxides. If the implantation mask 30 is formed by PECVD and the STI region is formed by FCVD, the implantation mask 30 has a higher density than the STI region 68.

[0093] The above-mentioned process is about Figure 10 , Figure 11A and Figure 12A The description is merely an example of how the fins 66 and nanostructures 55 are formed. In some embodiments, the fins 66 and / or nanostructures 55 may be formed using masking and epitaxial growth processes. For example, a dielectric layer may be formed on the main upper surface 10S of the substrate 10, and trenches may be etched through the dielectric layer to expose the underlying substrate 10. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may comprise alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments, the epitaxial structure is epitaxially grown, and the epitaxially grown material may be doped in situ during growth or doped using one or more implantation processes.

[0094] Furthermore, the first semiconductor layer 51 (and the formed nanostructure 52) and the second semiconductor layer 53 (and the formed nanostructure 54) are illustrated and discussed herein for illustrative purposes only as containing the same material in the P-type region 10P and the N-type region 10N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials or formed in different orders in the P-type region 10P or the N-type region 10N.

[0095] exist Figure 13 In this structure, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of: amorphous silicon, polycrystalline silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by PVD, CVD, sputtering deposition, or other techniques using the selected material. The dummy gate layer 72 can be made of other materials having high etch selectivity for etch isolation layers. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the N-class region 10N and the P-class region 10P. Note that the dummy dielectric layer 70 is illustrated only to cover the fin 66 and nanostructure 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0096] Figures 14A to 26C Several additional steps in manufacturing the apparatus of the embodiment are illustrated. Figure 14A and Figure 14B , curtain layer 74 (see Figure 13 The mask 78 can be patterned using acceptable lithography and etching techniques. The pattern of the mask 78 can be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover the corresponding channel regions of the fins 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 and its adjacent dummy gates 76. The dummy gates 76 may also have a length direction, generally perpendicular to the length direction of the corresponding fin 66.

[0097] exist Figure 15A and Figure 15BThe first spacer layer 80 and the second spacer layer 82 are respectively formed on Figure 14A and Figure 14B On the illustrated structure, the first spacer layer 80 and the second spacer layer 82 are then patterned as spacers for forming self-aligned source / drain regions. Figure 15A and Figure 15B In this structure, a first spacer layer 80 is formed on the upper surface of the STI region 68, the upper surface and sidewalls of the fin 66, the nanostructure 55, the mask 78, the dummy gate 76, and the sidewalls of the dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be silicon oxide, silicon nitride, silicon oxynitride, etc., and is formed using thermal oxidation or deposition techniques such as CVD or ALD. The second spacer layer 82 can be formed from a material with a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited using CVD, ALD, etc.

[0098] After the first spacer layer 80 is formed and before the second spacer layer 82 is formed, a lightly doped source / drain (LDD) region (not shown separately) implantation process can be performed. In embodiments with different device types, for example, a mask can be formed on an N-type region 10N, exposing a P-type region 10P, and a suitable type (e.g., P-type) of impurity can be implanted into the exposed fins 66 and nanostructures 55 in the N-type region 10N. The mask can then be removed. The N-type impurity can be any of the aforementioned N-type impurities, and the P-type impurity can be any of the aforementioned P-type impurities. The lightly doped source / drain region can have a density of approximately 1 × 10⁻⁶ cm². 15 Up to approximately 1×10 19 Impurity concentration in the range of individual atoms. Tempering processes can be used to repair implantation damage and reactivate implanted impurities.

[0099] exist Figure 16A and Figure 16BThe first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As detailed below, the first spacer 81 and the second spacer 83 enable self-alignment of the subsequently formed source and drain regions and protect the sidewalls of the fin 66 and / or nanostructure 55 in subsequent processes. The etching of the first spacer layer 80 and the second spacer layer 82 can be performed using a suitable etching process, such as an isotropic etching process (e.g., wet etching), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when patterning the second spacer layer 82, and that the second spacer layer 82 can act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 16A As shown. Next, the second spacer 83 acts as a mask when etching the exposed portion of the first spacer layer 80, forming as shown. Figure 16A The first spacer 81 is shown.

[0100] like Figure 16A As illustrated, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or nanostructure 55, as shown in Figure 8B. In some embodiments, the second spacer layer 82 may be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0101] It is worth noting that the above description broadly outlines the process for forming spacers and LDD regions. Other processes or sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be employed (e.g., the first spacer 81 may be formed before the deposition of the second spacer layer 82), additional spacers may be formed or removed, and so on. Furthermore, N-class and P-class devices may be formed using different structures or steps.

[0102] exist Figure 17A and Figure 17B According to some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 10. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 10. Figure 17AAs illustrated, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In various embodiments, the fins 66 may be etched such that the bottom surface of the first recess 86 is below the top surface of the STI region 68, etc. The first recess 86 may be formed by etching the fins 66, nanostructures 55, and substrate 10 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask a portion of the fins 66, nanostructures 55, and substrate 10 during the etching process used to form the first recess. Each layer of the nanostructure 55 and / or the fins 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching after the first recess has reached a desired depth.

[0103] exist Figure 18A and Figure 18B In the process, the sidewall portions of the multilayer stack 64 formed of a first semiconductor material exposed by the first recess 86 (e.g., the first nanostructure 52) are etched to form a sidewall recess 88 in the N-class region 10N, and the sidewall portions of the multilayer stack 64 formed of a second semiconductor material exposed by the first recess 86 (e.g., the second nanostructure 54) are etched to form a sidewall recess 88 in the P-class region 10P. Although the sidewall recess 88 is in Figure 20B The middle section is depicted as flat, but the sidewalls can be recessed or raised. The sidewalls can be etched using an isotropic etching process, such as wet etching. The P-type region 10P can be protected with a mask (not shown) and etched with an etchant selective to the first semiconductor material to etch the first nanostructure 52, so that the second nanostructure 54 and the substrate 10 remain relatively unetched compared to the first nanostructure 52 in the N-type region 10N. Similarly, the N-type region 10N can be protected with a mask (not shown) and etched with an etchant selective to the second semiconductor material to etch the second nanostructure 54, so that the first nanostructure 52 and the substrate 10 remain relatively unetched compared to the second nanostructure 54 in the P-type region 10P. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewalls of the first nanostructure 52 in the N-type region 10N, and a wet or dry etching process using hydrogen fluoride or other fluorine-based etchants can be used to etch the sidewalls of the second nanostructure 54 in the P-type region 10P.

[0104] exist Figures 19A to 19C In the middle, a first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 can deposit an inner spacer layer (not shown separately) in Figure 20A and Figure 20BThe structure is formed on the diagram. The first inner spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As detailed below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the N-class region 10N and the second nanostructure 54 in the P-class region 10P will be replaced by the corresponding gate and gate structures.

[0105] The inner spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The inner spacer layer may contain materials such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as low-k materials with a k-value less than about 3.5. The inner spacer layer can be anisotropically etched to form the first inner spacer 90. Although the outer wall of the first inner spacer 90 is shown flush with the sidewall of the second nanostructure 54 in the N-type region 10N, the outer wall of the first inner spacer 90 may extend over or recess from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0106] Furthermore, even if the outer wall of the first inner spacer 90 is in Figure 19B The first inner spacer 90 is depicted as flat; its outer wall may be recessed or convex. For example, Figure 19C An embodiment is illustrated with sidewall recesses of the first nanostructure 52, outer wall recesses of the first inner spacer 90, and the first inner spacer 90 recessed from the second nanostructure 54 in the N-type region 10N. An embodiment is also illustrated with sidewall recesses of the second nanostructure 54, outer wall recesses of the first inner spacer 90, and the first inner spacer 90 recessed from the second nanostructure 54 in the P-type region 10P. The inner spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent the formation of subsequent source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as...) Figures 20A to 20C (Description) Damage in subsequent etching processes, such as the etching process used to form the gate structure.

[0107] exist Figures 20A to 20C In this configuration, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the source / drain regions 92 can apply stress to the second nanostructure 54 in the N-type region 10N and the first nanostructure 52 in the P-type region 10P to improve performance. Figure 20BThe illustration shows that epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first inner spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 to maintain an appropriate lateral distance so that the epitaxial source / drain regions 92 are not short-circuited by the gate subsequently formed by the formed nanoFET.

[0108] For example, the epitaxial source / drain region 92 in the N-class region 10N of an NMOS region can be formed by masking, for example, the P-class region 10P of a PMOS region. Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 of the N-class region 10N. The epitaxial source / drain region 92 can contain any material suitable for an N-class nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can contain a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphide-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can include a surface rising from the upper surface of the opposing nanostructure 55 and can have a small facet.

[0109] For example, the epitaxial source / drain region 92 in the P-class region 10P of a PMOS region can be formed by masking, for example, the N-class region 10N of an NMOS region. Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 of the P-class region 10P. The epitaxial source / drain region 92 can contain any material suitable for a P-class nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can contain a material to which compressive strain is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also contain a surface rising from the upper surface of the opposing nanostructure 55 and can have a small facet.

[0110] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 10 can be implanted with dopants to form the source / drain region, similar to the aforementioned process for forming a lightly doped source / drain region and the subsequent annealing process. The source / drain region can have approximately 1 × 10⁻⁶ cm². 19 Up to approximately 1×10 21 Impurity concentration between atoms. The N-type and / or P-type impurities in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in-situ during growth.

[0111] The epitaxial process used to form epitaxial source / drain regions 92 in the N-class region 10N and P-class region 10P results in small planes on the upper surface of the epitaxial source / drain regions 92 extending laterally outward through the sidewalls of the nanostructure 55. These small planes cause adjacent epitaxial source / drain regions 92 of the same nanoFET to fuse, such as... Figure 20A Illustration. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as... Figure 20C As shown in the drawing. Figure 20A and Figure 20C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to block epitaxial growth. In other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 81 to further block epitaxial growth. In other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material such that the epitaxial growth region extends to the surface of the STI region 68.

[0112] The epitaxial source / drain region 92 may comprise one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 comprises three semiconductor material layers, a first nanomaterial layer 92A may be deposited, a second nanomaterial layer 92B may be deposited on the first nanomaterial layer 92A, and a third nanomaterial layer 92C may be deposited on the second nanomaterial layer 92B.

[0113] Figure 20D The diagram illustrates the sidewalls of the first nanostructure 52 in the N-type region 10N and the sidewalls of the second nanostructure 54 in the P-type region 10P, with the outer sidewall of the first inner spacer 90 recessed, and the first inner spacer 90 recessed from the sidewalls of both the second nanostructure 54 and the first nanostructure 52. Figure 20D As illustrated, the epitaxial source / drain region 92 can be formed by contacting the first inner spacer 90 and can extend through the sidewalls of the second nanostructure 54 in the N-type region 10N and the sidewalls of the first nanostructure 52 in the P-type region 10P.

[0114] exist Figures 21A to 21C In the middle, the first interlayer dielectric (ILD) 96 is deposited on... Figure 14A , Figure 20B , Figure 20AThe structure shown ( Figures 15A to 20D The process remains unchanged. Figure 14A (Illustrated cross-section). The first interlayer dielectric 96 may be formed of a dielectric material and deposited by any suitable method, such as CVD, PECVD, or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by acceptable processes may also be used. In some embodiments, a contact etch stop layer (CESL) 94 is deposited between the first interlayer dielectric 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The contact etch stop layer 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., with a different etch rate than the material of the first interlayer dielectric 96 thereon.

[0115] exist Figures 22A to 22B In this process, a planarization process, such as CMP, can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first interlayer dielectric 96 are flush within process tolerances. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first dielectric 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0116] exist Figure 23A and Figure 23B In the process, the dummy gate 76 is removed, if present, by one or more etching steps, through a mask 78, resulting in the formation of a second recess 98. A portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy dielectric layer 60 are removed using an anisotropic dry etching process. For example, the etching process may include selectively etching the dummy gate 76 reactive gas at a rate faster than the first interlayer dielectric 96 or the first spacer 81. Each second recess 98 is located above and / or exposes the nanostructure 55, which serves as a channel region for the subsequently completed nanoFET. The portion of the nanostructure 55 serving as the channel region is disposed between two adjacent epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 can be used as an etch stop layer during the etching of the dummy gate 76. The dummy dielectric layer 60 may be removed subsequently after the removal of the dummy gate 76.

[0117] exist Figure 24A and Figure 24BIn this process, the first nanostructure 52 in the N-type region 10N and the second nanostructure 54 in the P-type region 10P are removed to extend the second recess 98. The first nanostructure 52 can be formed by forming a mask (not shown) on the P-type region 10P and performing an isotropic etching process, such as wet etching, using an etchant selectively applied to the first nanostructure 52. The second nanostructure 54, the substrate 10, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52 in the N-type region 10N.

[0118] The second nanostructure 54 in the P-type region 10P can be formed by creating a mask (not shown) on the N-type region 10N and performing an isotropic etching process, such as wet etching, using an etchant selectively applied to the first nanostructure 52. The second nanostructure 54, the substrate 10, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride or other fluorine-based etchants can be used to remove the second nanostructure 54 in the P-type region 10P.

[0119] In other embodiments, the channel regions in both the N-class region 10N and the P-class region 10P can be formed simultaneously, for example, by removing the first nanostructure 52 in both the N-class region 10N and the P-class region 10P, or by removing the second nanostructure 54 in both the N-class region 10N and the P-class region 10P. In such embodiments, the channel regions of the N-class nanoFET and the P-class nanoFET can have the same material composition, such as silicon, silicon-germanium, etc. Figure 29A , Figure 29B and Figure 29C The diagram illustrates a structure obtained from such an embodiment, wherein the channel regions in the P-type region 10P and the N-type region 10N are provided by a second nanostructure 54 and contain, for example, silicon.

[0120] exist Figure 25A and Figure 25B In the second recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the N-class region 10N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 10 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the P-class region 10P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 10 and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer may also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the first spacer 81, and the STI region 68.

[0121] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In the N-class region 10N and the P-class region 10P, the gate dielectric layer 100 may be the same or different. The method of forming the gate dielectric layer 100 may include atomic beam deposition (MBD), ALD, PECVD, etc.

[0122] Gate electrodes 102 are deposited on the gate dielectric layer 100 and fill the remaining portion of the second recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers of the same material. For example, although... Figure 25A and Figure 25B A single-layer gate electrode 102 is illustrated. The gate electrode 102 may include any number of pad layers, any number of work function tuning layers, and a fill layer. Any combination of layers constituting the gate electrode 102 may be deposited on N-class regions 10N between adjacent second nanostructures 54 and between the second nanostructures 54 and the substrate 10, and on P-class regions 10P between adjacent first nanostructures 52.

[0123] The formation of the gate dielectric layer in the N-class region 10N and the P-class region 10P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed with the same material and / or has a different number of layers, and / or the gate electrode 102 in each region can be formed separately, such that the gate electrode 102 can be made of different materials and / or have a different number of layers. When separate processes are used, multiple masking steps can be used to mask and expose suitable areas.

[0124] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, with the excess portion on the top surface of the first interlayer dielectric 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0125] exist Figures 26A to 26CIn this configuration, the gate structure (including the gate dielectric layer 100 and its corresponding gate electrode 102) is recessed, such that the recess is formed directly between the gate structure and the opposite portion of the first spacer 81. The gate mask 104, comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., fills the recess. A planarization process is then performed to remove excess dielectric material extending onto the first interlayer dielectric 96. The gate contacts (e.g., contact 114, in conjunction with...) are then formed. Figure 28A and Figure 28B (Discussion) The upper surface of the recessed gate electrode 102 is contacted through the gate shroud 104.

[0126] like Figures 26A to 26C Further illustration shows that the second interlayer dielectric 106 is deposited on the first interlayer dielectric 96 and the gate mask 104. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0127] exist Figures 27A to 27C The second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed using an anisotropic etching process, such as RIE, NBE, etc. In some embodiments, the third recess 108 can be etched using a first etching process through the second interlayer dielectric 106 and the first interlayer dielectric 96, a second etching process through the gate mask 104, and a third etching process through the contact etch stop layer 94. The mask, such as photoresist, can be formed and patterned on the second interlayer dielectric 106 to mask portions of the second interlayer dielectric 106 in the first and second etching processes. In some embodiments, the etching process may over-etch, thereby extending the third recess 108 into the epitaxial source / drain region 92 and / or gate structure, and the bottom surface of the third recess 108 may be flush with (e.g., at the same height, or at the same distance from the substrate) or lower (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 29BThe third recess 108 exposes the epitaxial source / drain region 92 and the gate structure on the same cross-section. In several embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed on different cross-sections, thus reducing the risk of short circuits at the subsequently formed contacts. After the third recess 108 is formed, a silicide region 110 is formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is first deposited with a metal (not shown) that can react with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium), such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, on the epitaxial source / drain region 92, followed by a thermal annealing process to form the silicide region 110. Unreacted portions of the metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon-germanide region (e.g., a region containing silicide and germanide). In one embodiment, the silicide region 110 contains TiSi and has a thickness in the range of 2 nm to 10 nm.

[0128] Next, in Figures 28A to 28C In the third recess 108, contacts 112 and 114 (also referred to as contact fillers) are formed. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler layer. For example, in some embodiments, contacts 112 and 114 each comprise a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., the gate structure and / or silicide 110 in the illustrated embodiment). Contact 114, electrically coupled to the gate structure, may be referred to as a gate contact, while contact 112, electrically coupled to the silicide 110, may be referred to as a source / drain contact. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material 118 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second interlayer dielectric 106. The structure of alignment mark region 10A is illustrated in... Figure 28D Additional processes can be performed, including back-to-line (BEOL) processes, cutting substrate 10 to separate IC chips, etc., which are not specifically shown here.

[0129] Figures 29A to 29C A cross-sectional view of an apparatus according to some alternative embodiments is shown. Figure 29A Draw Figure 1 The reference section A-A' is shown in the figure. Figure 29B Draw Figure 1 The reference section B-B' is shown in the figure. Figure 29C Draw Figure 1 The reference section C-C' is shown in the drawing. Figures 29A to 29C In the middle, similar reference numbers correspond Figures 28A to 28C Similar components are formed using similar processes. However, Figures 29A to 29C In this configuration, the channel regions in both the N-class region 10N and the P-class region 10P contain the same material. For example, a second nanostructure 54 containing silicon provides the channel regions for the P-class nanoFET in the P-class region 10P and the N-class nanoFET in the N-class region 10N. Figure 29A The structure leading to the 29C can be achieved, for example, by simultaneously removing the first nanostructure 52, depositing the gate dielectric layer 100 and the gate electrode 102 (e.g., a gate electrode suitable for a P-class nanoFET) near the second nanostructure 54 in the P-class region 10P, and depositing the gate dielectric layer 100 and the gate electrode 102 (e.g., a gate electrode suitable for an N-class nanoFET) near the second nanostructure 54 in the N-class region 10N. In such an embodiment, as explained above, the material of the epitaxial source / drain region 92 can be different in the N-class region 10N and the P-class region 10P.

[0130] These embodiments offer several advantages. For example, the techniques described above, such as the rigid masking of the thermal implantation process, can help control the side boundaries of the P-type well 24 and the N-type well, thereby reducing the potential overlap between adjacent P-type wells 24 and N-type wells 38, improving the interface between the P-type wells 24 and N-type wells 38, and preventing leakage current from the P-type well 24 or N-type well 38.

[0131] In one embodiment, a semiconductor device includes a semiconductor substrate, a first well, a second well, an alignment mark, and an isolation layer. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material. The isolation layer is located above the first fin, the second fin, the semiconductor substrate, and the alignment mark. In one embodiment, the first material is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof, and the second material is different from the first material and is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. In one embodiment, the semiconductor device further includes a semiconductor channel region stack extending above the first fin. In one embodiment, the alignment mark has a top surface below a major upper surface of the semiconductor substrate. In one embodiment, the insulating layer extends below the main upper surface of the semiconductor substrate. In one embodiment, the first material is doped with a first dopant and a second dopant. In one embodiment, the second material is doped with a second dopant. In one embodiment, the first material is doped with the first dopant, and the second material is undoped. In one embodiment, both the first and second materials are doped with only the second dopant.

[0132] In another embodiment, a method of manufacturing a semiconductor device includes forming trenches in a semiconductor substrate, forming a first patterned mask over the semiconductor substrate, wherein the first patterned mask includes a first material filling the trenches, implanting a first dopant through the first patterned mask to form a first well in the semiconductor substrate, the first dopant having a first conductivity type, removing the first patterned mask above a main upper surface of the semiconductor substrate and partially removing the first material in the trenches, forming a second patterned mask over the semiconductor substrate, wherein the second patterned mask includes a second material filling the trenches and covering the first material, and implanting a first dopant through the first patterned mask to form a first well in the semiconductor substrate. A second patterned mask is used to implant a second dopant to form a second well in a semiconductor substrate. The second dopant has a second conductivity type different from the first conductivity type. After the second well is formed, the second patterned mask above the main upper surface of the semiconductor substrate is removed. After removing the second patterned mask, at least a portion of the second material remains in the trench. The semiconductor substrate is etched to form a first fin and a second fin, wherein the first fin is located in the first well and the second fin is located in the second well. An insulating layer is formed above the semiconductor substrate, wherein the insulating layer runs along the sidewalls of the first fin and the sidewalls of the second fin and covers the second material in the trench. In one embodiment, etching the semiconductor substrate to form the first fin and the second fin includes etching at least a portion of the second material in the trench. In one embodiment, the insulating layer fills the trench and contacts the second material. In one embodiment, implanting the first dopant through the first patterned mask includes implanting the first dopant into the trench with the first material. In one embodiment, implanting the second dopant through the second patterned mask includes implanting the second dopant into the trench with the first material and the second material. In one embodiment, the first material is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. In one embodiment, the second material is different from the first material and is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof.

[0133] In another embodiment, a method of manufacturing a semiconductor device includes forming a trench in a substrate; forming a first hard mask above a main upper surface of the substrate and within the trench, wherein the first hard mask includes a first opening exposing a first region of the substrate; performing a first implantation process through the first opening of the first hard mask to form a first well in the first region; etching the first hard mask while retaining a portion of the first hard mask; forming a second hard mask above the main upper surface of the substrate and above a portion of the first hard mask within the trench, wherein the second hard mask includes a second opening to expose a second portion of the substrate; etching the second hard mask to at least remove the second hard mask above the main upper surface; depositing a first epitaxial layer and a second epitaxial layer alternately stacked on the substrate and above the second hard mask in the trench; and etching the stack and the substrate to form a first fin in the first well, a second fin in the second well, a first nanostructure stack above the first fin, and a second nanostructure stack above the second fin. In one embodiment, the second hard mask is etched simultaneously with the etching of the substrate and the stack. In one embodiment, the method of manufacturing a semiconductor device further includes forming an isolation layer adjacent to the first fin and the second fin and filling the trench. In one embodiment, the first rigid mask and the second rigid mask are formed of different materials.

[0134] In one embodiment, a semiconductor device includes a semiconductor substrate, a first well, a second well, an alignment mark, and an isolation layer. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is located in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is located in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, and the first material is doped with both the first and second dopants.

[0135] In one embodiment, a semiconductor device includes a semiconductor substrate, a first well, a second well, alignment marks, and an isolation layer. The semiconductor substrate includes a first fin and a second fin. The first well is located in the semiconductor substrate, wherein the first fin is located in the first well, and the first well is doped with a first dopant having a first conductivity type. The second well is located in the semiconductor substrate, wherein the second fin is located in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type. The alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, the first material being doped with the first dopant, and the second material being undoped.

[0136] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other methods and structures for achieving the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor substrate, the semiconductor substrate comprising a first fin and a second fin; A first well is located in the semiconductor substrate, wherein the first fin is in the first well, and the first well is doped with a first dopant having a first conductivity type; A second well is located in the semiconductor substrate, wherein the second fin is in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type; An alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material; and An insulating layer is located above the first fin, the second fin, the semiconductor substrate, and the alignment mark.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a semiconductor channel region stack extending above the first fin.

3. The semiconductor device as claimed in claim 1, characterized in that, The alignment mark has a top surface below a main upper surface of the semiconductor substrate.

4. The semiconductor device as claimed in claim 3, characterized in that, The insulating layer extends below the main upper surface of the semiconductor substrate.

5. A semiconductor device, characterized in that, Include: A semiconductor substrate, the semiconductor substrate comprising a first fin and a second fin; A first well is located in the semiconductor substrate, wherein the first fin is in the first well, and the first well is doped with a first dopant having a first conductivity type; A second well, located in the semiconductor substrate, wherein the second fin is in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type; and An alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, and the first material is doped with the first dopant and the second dopant.

6. The semiconductor device as claimed in claim 5, characterized in that, The second material is doped with the second dopant.

7. A semiconductor device, characterized in that, Include: A semiconductor substrate, the semiconductor substrate comprising a first fin and a second fin; A first well is located in the semiconductor substrate, wherein the first fin is in the first well, and the first well is doped with a first dopant having a first conductivity type; A second well, located in the semiconductor substrate, wherein the second fin is in the second well, and the second well is doped with a second dopant having a second conductivity type different from the first conductivity type; and An alignment mark is located in the semiconductor substrate, wherein the alignment mark includes a lower portion formed of a first material and an upper portion formed of a second material different from the first material, the first material being doped with a first dopant and the second material being undoped.

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