Test circuit board
By integrating the connection interface and test module into a single test circuit board, and separating the test function circuit and ground circuit into layers, the interference problem of electrostatic discharge testing on signal circuits is solved, achieving safer and more economical testing.
Patent Information
- Application Number
- CN202423067194.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2026-03-06
- Estimated Expiration
- 2034-12-11
AI Technical Summary
Existing electrostatic discharge (ESD) tests can easily affect other signal circuits on the main circuit board of electronic products, leading to scrapping, increasing testing costs, and affecting testing safety.
Design a test circuit board that integrates the connection interface and the test module into one unit. Perform electrostatic discharge testing through the test module. The test function circuit and the ground circuit are set on different wiring layers to avoid interference of electrostatic discharge pulses to other signal circuits.
It effectively avoids interference from electrostatic discharge pulses to other signal circuits, reduces the scrap cost of test circuit boards, and makes testing safer.
Smart Images
Figure CN223977293U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and more particularly to a test circuit board. Background Technology
[0002] ESD testing, or electrostatic discharge testing, is a method used to evaluate the performance stability and immunity of electronic devices or components when subjected to electrostatic discharge. ESD testing simulates electrostatic discharge conditions that devices might encounter in real-world use, ensuring that the devices can operate normally under ESD events and will not be damaged by static electricity.
[0003] Currently, existing electrostatic discharge (ESD) tests are all performed directly through the interface of the main circuit board of electronic products. During the test, this can easily affect other signal circuits on the main circuit board, causing the main circuit board to be scrapped, increasing the cost of ESD testing, and affecting the safety of ESD testing. Summary of the Invention
[0004] This application provides a test circuit board that can avoid affecting other signal circuits during testing, reduce testing costs, and make testing safer.
[0005] To solve the above-mentioned technical problems, the embodiments of this application adopt the following technical solutions:
[0006] In a first aspect, this application provides a test circuit board, including a connection interface and a test module;
[0007] The connection interface communicates with the test module.
[0008] The connection interface is configured to connect to the test equipment and transmit the electrostatic discharge pulses sent by the test equipment to the test module to perform electrostatic discharge testing on the test module.
[0009] In some embodiments, the test module includes a test circuit and a multilayer circuit board, with the test circuit disposed on the multilayer circuit board.
[0010] In some embodiments, the multilayer circuit board includes a first wiring layer and a second wiring layer.
[0011] In some embodiments, the test circuit includes a test function circuit and a ground circuit.
[0012] In some embodiments, the test function circuitry is disposed on the first wiring layer.
[0013] In some embodiments, the ground circuit is disposed on the second wiring layer.
[0014] In some embodiments, the first wiring layer is close to the front side of the multilayer circuit board, and the second wiring layer is close to the back side of the multilayer circuit board.
[0015] In some embodiments, the test function circuit includes a protection diode, the input of which is connected to a connection interface, and the output of which is connected to a ground circuit.
[0016] In some embodiments, the connection interface includes a VGA interface, a network interface, a data interface, a Type-C interface, or a Serial Advanced Technology Accessory (SATI) interface.
[0017] In some embodiments, the test function circuit includes a VGA interface test function circuit, a network interface test function circuit, a data interface test function circuit, a Type-C interface test function circuit, or a Serial Advanced Technology Accessory (SATIA) interface test function circuit.
[0018] The beneficial effects of this application's embodiments are as follows: Unlike existing technologies, this application provides a test circuit board including a connection interface and a test module. The connection interface is communicatively connected to the test module. The connection interface is configured to connect to a test device, transmitting electrostatic discharge pulses sent by the test device to the test module for electrostatic discharge testing. This solution integrates multiple connection interfaces and test modules into a single test circuit board, enabling the test circuit board to characterize the electrostatic discharge testing of the main circuit board of an electronic product. Compared to directly performing ESD testing on the interfaces of the main circuit board of an electronic product, which can easily cause signal interference or render the main circuit board unusable, this solution, by testing the aforementioned test circuit board, effectively avoids interference from electrostatic discharge pulses to other signal circuits, reduces the cost of scrapping test circuit boards during electrostatic discharge testing, and makes the testing safer. Attached Figure Description
[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0020] Figure 1 This is a schematic diagram of the structure of the test circuit board device provided in this embodiment of the utility model;
[0021] Figure 2 This is a schematic diagram of the test circuit provided in an embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram of the structure of the multilayer circuit board provided in this embodiment of the utility model;
[0023] Figure 4This is a schematic diagram of the test function circuit provided in an embodiment of the present invention;
[0024] Figure 5 This is a circuit diagram of the VGA interface testing function circuit provided in this embodiment of the utility model;
[0025] Figure 6 This is a circuit diagram of the network interface testing function circuit provided in this embodiment of the utility model;
[0026] Figure 7 This is a circuit diagram of the Type-C interface testing function circuit provided in this embodiment of the utility model;
[0027] Figure 8 This is a circuit diagram of the serial advanced technology accessory interface test function circuit provided in this embodiment of the utility model;
[0028] Figure 9 This is a circuit diagram of the data interface testing function circuit provided in this embodiment of the utility model. Detailed Implementation
[0029] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.
[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0031] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. In addition, the terms "first," "second," and "third" used herein do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.
[0032] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.
[0033] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0034] Given the current operating environment of electronic devices, port protection circuits are typically installed at the ports of these devices to protect them from external interference and overvoltage. These external interferences and overvoltages can originate from electrostatic discharge (ESD), electrical noise, voltage surges, and other sources. During product manufacturing, port protection circuits are usually tested to ensure their functionality. ESD testing is the test used to evaluate the resistance of electronic devices or components to electrostatic discharge. ESD testing involves applying a predefined electrostatic discharge pulse to the device under test using a specific testing device, simulating electrostatic discharge events that may be encountered in actual use, to verify the reliability and safety of the product when subjected to electrostatic shock.
[0035] Existing ESD testing involves directly connecting the test equipment to the main circuit board of the device under test (DUT). During testing, electrostatic energy can easily enter the circuit, causing power lines to induced static electricity and resulting in ESD anomalies. Furthermore, the dense wiring on the DUT's main circuit board can easily affect other signal lines during ESD testing, potentially rendering the main circuit board unusable and increasing the cost of ESD testing.
[0036] In view of this, the present invention provides a test circuit board, please refer to... Figure 1 The test circuit board 100 includes a connection interface 110 and a test module 120. The input terminal of the connection interface 110 is used to connect to the test equipment 200, and the output terminal of the connection interface 110 is communicatively connected to the test module. The connection interface 110 receives electrostatic discharge pulses from the test equipment 200 to simulate discharge conditions, and sends the received electrostatic discharge pulses to the test module 120 to perform electrostatic discharge testing on the test module 120 and confirm whether the function of the test module 120 is complete and error-free.
[0037] By integrating the connection interface 110 and the test module 120 into a test circuit board 100, the test circuit board 100 can characterize the electrostatic discharge (ESD) test of the main circuit board of an electronic product. Compared to directly performing ESD testing on the interface of the main circuit board of the electronic product, testing the test circuit board 100 can effectively avoid interference from ESD pulses to other signal circuits, reduce the cost of scrapping the test circuit board due to ESD testing, and make ESD testing safer.
[0038] The test module 120 includes a test circuit 121 and a multilayer circuit board 122, with the test circuit 121 disposed on the multilayer circuit board 122. The test circuit 121 includes a test function circuit 1211 and a ground circuit 1212. The multilayer circuit board 122 includes a first wiring layer 1221 and a second wiring layer 1222. The test function circuit 1211 is disposed on the first wiring layer 1221, and the ground circuit 1212 is disposed on the second wiring layer 1222. Figure 2 As shown, one end of the test function circuit 1211 is connected to the connection interface 110 to receive the electrostatic discharge pulse sent by the connection interface 110. The other end of the test function circuit 1211 is connected to the ground circuit 1212 to transmit the received electrostatic discharge pulse to the ground circuit 1212. The ground circuit 1212 guides the electrostatic discharge pulse sent by the test function circuit 1211 to the ground.
[0039] By placing the test function circuit 1211 on the multilayer circuit board 122, the test function circuit 1211 can be isolated from the ground circuit 1212. On the one hand, this can prevent electrostatic discharge pulses from affecting other signal lines during ESD testing. On the other hand, placing the test function circuit 1211 and the ground circuit 1212 on the first wiring layer 1221 and the second wiring layer 1222 respectively makes the line spacing between the test function circuit 1211 and the ground circuit 1212 larger, providing sufficient space for the test circuit board 100 and the ability to withstand excessive voltage and current.
[0040] In some embodiments, the first wiring layer 1221 is located near the front side of the multilayer circuit board 122, and the second wiring layer 1222 is located near the back side of the multilayer circuit board 122, such as... Figure 3 As shown. By placing the test function circuit 1211 on the first wiring layer 1221 and the ground circuit 1212 on the second wiring layer 1222, the test circuit board 100 becomes more accessible, facilitating component soldering. Furthermore, the ground layer can serve as a reference plane, reducing noise and providing better signal integrity.
[0041] In some embodiments, please refer to Figure 4The test function circuit 1211 includes a protection diode 12111. The input terminal of the protection diode 12111 is connected to the interface 110 to receive electrostatic discharge pulses sent by the interface 110. The output terminal of the protection diode 12111 is connected to the ground circuit 1212 to send the received electrostatic discharge pulses to the ground circuit 1212, so as to prevent the overvoltage and overcurrent caused by the electrostatic discharge pulses from damaging the test circuit board 100.
[0042] Connection interface 110 connects to test equipment 200. Test equipment 200 sends electrostatic discharge pulses to connection interface 110 to simulate processes such as friction, contact, and separation between objects. The output terminal of connection interface 110 is connected to test function circuit 1211 located on the first wiring layer 1221 to send the received electrostatic discharge pulses to test function circuit 1211. Test function circuit 1211 includes a protection diode 12111. One end of the protection diode 12111 is connected to connection interface 110, and the other end is connected to ground circuit 1212 located on the second wiring layer 1222. The protection diode 12111 receives the electrostatic discharge pulses sent by connection interface 110 and quickly conducts, transmitting the electrostatic discharge pulses to ground circuit 1212. Ground circuit 1212 transmits the received electrostatic discharge pulses to ground to ensure that other signal lines are protected from external interference and overvoltage.
[0043] By integrating the connection interface 110 and the test module 120 into a test circuit board 100, interference with other signal lines can be avoided when performing ESD testing on the test circuit board 100, reducing the cost of scrapped test circuit boards during ESD testing and making the test safer. Furthermore, by placing the test function circuit 1211 and the ground circuit 1212 on the first wiring layer 1221 and the second wiring layer 1222 respectively, not only can the test function circuit 1211 and the ground circuit 1212 be effectively isolated, but the traces of the test function circuit 1211 and the ground circuit 1212 also have a larger trace spacing, providing sufficient space for the test circuit board 100 and the ability to withstand excessive voltage and current.
[0044] In some embodiments, please refer to Figure 5The connection interface 110 includes a VGA interface 111, the protection diode 12111 includes a VGA interface 111 protection diode 12111a, and the test function circuit 1211 includes a VGA interface test function circuit 1211a. One end of the VGA interface protection diode 12111a is connected to pins V1, V2, V3, V9, V12, V13, V14, and V15 of the VGA interface 111, respectively. The other end of the VGA interface protection diode 12111a is connected to the ground circuit 1212. Pins V5, V6, V7, V8, V10, X1, and X2 of the VGA interface 111 are grounded. The test equipment 200 sends an electrostatic discharge pulse to the VGA interface 111. The VGA interface 111 sends the received electrostatic discharge pulse to the VGA interface protection diode 12111a through a pin connected to the VGA interface protection diode 12111a. After receiving the electrostatic discharge pulse, the VGA interface protection diode 12111a quickly turns on and sends the electrostatic discharge pulse to the ground circuit 1212. The ground circuit 1212 quickly guides the received electrostatic discharge pulse to the ground line to prevent it from affecting other signal lines.
[0045] In some embodiments, please refer to Figure 6 The connection interface 110 includes a network interface 112, the protection diode 12111 includes a network interface protection diode 12111b, and the test function circuit 1211 includes a network interface test function circuit 1211b. One end of the network interface protection diode 12111b is connected to the first, second, third, fourth, fifth, sixth, seventh, and eighth pins of the network interface 112, respectively, and the other end of the network interface protection diode 12111b is connected to the ground circuit 1212. The G1, G2, G3, and G4 pins of the network interface 112 are grounded. The test device 200 sends an electrostatic discharge pulse to the network interface 112. The network interface 112 sends the received electrostatic discharge pulse to the network interface protection diode 12111b through a pin connected to the network interface protection diode 12111b. After receiving the electrostatic discharge pulse, the network interface protection diode 12111b quickly turns on and sends the electrostatic discharge pulse to the ground circuit 1212. The ground circuit 1212 quickly guides the received electrostatic discharge pulse to the ground line to prevent it from affecting other signal lines.
[0046] In some embodiments, please refer to Figure 7The connection interface 110 includes a Type-C interface 113, the protection diode 12111 includes a Type-C interface protection diode 12111c, and the test function circuit 1211 includes a Type-C interface test function circuit 1211c. One end of the Type-C interface protection diode 12111c is connected to pins A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, B2, B3, B4, B5, B6, B7, B8, B9, B10, and B11 of the Type-C interface 113, respectively. The other end of the Type-C interface protection diode 12111c is connected to the ground circuit 1212. Pins A1, A12, B1, B12, X1, X2, X3, X4, X5, and X6 of the Type-C interface 113 are grounded. The test equipment 200 sends an electrostatic discharge pulse to the Type-C interface 113. The Type-C interface 113 sends the received electrostatic discharge pulse to the Type-C interface protection diode 12111c through a pin connected to the Type-C interface protection diode 12111c. After receiving the electrostatic discharge pulse, the Type-C interface protection diode 12111c quickly conducts and sends the electrostatic discharge pulse to the ground circuit 1212. The ground circuit 1212 quickly guides the received electrostatic discharge pulse to the ground line to prevent it from affecting other signal lines.
[0047] In some embodiments, please refer to Figure 8The connection interface 110 includes a Serial Advanced Technology Accessory (SATA) interface 114, the protection diode 12111 includes a SATA protection diode 12111d, and the test function circuit 1211 includes a SATA test function circuit 1211d. One end of the SATA protection diode 12111d is connected to the second, third, fifth, and sixth pins of the SATA interface 114, respectively, and the other end of the SATA protection diode 12111d is grounded. The first, fourth, seventh, eighth, and ninth pins of the SATA interface 114 are grounded. Test equipment 200 sends an electrostatic discharge pulse to Serial Advanced Technology Accessories (SADA) interface 114. SADA interface 114 sends the received electrostatic discharge pulse to SADA protection diode 12111d via a pin connected to SADA protection diode 12111d. Upon receiving the electrostatic discharge pulse, SADA protection diode 12111d quickly conducts and sends the electrostatic discharge pulse to ground circuit 1212. Ground circuit 1212 quickly guides the received electrostatic discharge pulse to ground to prevent it from affecting other signal lines.
[0048] In some embodiments, please refer to Figure 9 The connection interface 110 includes a data interface 115, the protection diode 12111 includes a data interface protection diode 12111e, and the test function circuit 1211 includes a data interface test function circuit 1211e. One end of the data interface protection diode 12111e is connected to the first, second, third, fourth, fifth, and sixth pins of the data interface 115, and the other end is connected to the ground circuit 1212. The test device 200 sends an electrostatic discharge pulse to the data interface 115. The data interface 115 sends the received electrostatic discharge pulse to the data interface protection diode 12111e through the pin connected to the data interface protection diode 12111e. After receiving the electrostatic discharge pulse, the data interface protection diode 12111e quickly conducts and sends the electrostatic discharge pulse to the ground circuit 1212. The ground circuit 1212 quickly guides the received electrostatic discharge pulse to the ground line to prevent it from affecting other signal lines.
[0049] In summary, this solution integrates the connection interface 110 and the test module 120 to obtain the test circuit board 100. By performing ESD testing on the test circuit board 100, ESD functional testing of the corresponding interface and the test module 120 is achieved. Compared to directly performing ESD testing on the interface of the main circuit board of the electronic product, which can easily cause signal interference or scrap the main circuit board, this solution, by testing the aforementioned test circuit board 100, can not only effectively avoid interference from electrostatic discharge pulses to other signal circuits, but also reduce the cost of scrapping the test circuit board due to ESD testing, making the testing safer. In addition, by placing the test function circuit 1211 and the ground circuit 1212 in the test module 120 on different wiring layers of the circuit board, the test function circuit 1211 and the ground circuit 1212 have better isolation and wider line spacing, providing the test circuit board 100 with more space and the ability to withstand excessive voltage and current.
[0050] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A test circuit board, characterized by, The test circuit board comprises a connection interface and a test module; The connection interface is in communication connection with the test module; The connection interface is configured to connect a test device, and transmit an electrostatic discharge pulse sent by the test device to the test module to perform electrostatic discharge test on the test module; The test module comprises a test circuit and a multilayer circuit board, and the test circuit is arranged on the multilayer circuit board.
2. The test circuit board of claim 1, wherein, The test circuit comprises a test function circuit and a ground circuit.
3. The test circuit board of claim 2, wherein, The test function circuit is arranged on the first wiring layer.
4. The test circuit board of claim 2, wherein, The ground circuit is arranged on the second wiring layer.
5. The test circuit board of any one of claims 1-4, wherein, The first wiring layer is close to the front surface of the multilayer circuit board, and the second wiring layer is close to the back surface of the multilayer circuit board.
6. The test circuit board of claim 2, wherein, The test function circuit comprises a protection diode, an input end of the protection diode is connected to the connection interface, and an output end of the protection diode is connected to the ground circuit.
7. The test circuit board of claim 2, wherein, The test function circuit comprises a VGA interface test function circuit, a network interface test function circuit, a data interface test function circuit, a Type-C interface test function circuit or a serial advanced technology attachment interface test function circuit.
8. The test circuit board of claim 7, wherein, The connection interface comprises a VGA interface, a network interface, a data interface, a Type-C interface or a serial advanced technology attachment interface.