Bus-based communication interface

Abstract

The utility model provides a bus-based communication interface, which solves the problems of higher cost of independent power supply of slaves and the like, and comprises a host, the host is connected with a plurality of slaves through a double-wire connecting cable, the host comprises a PC (Personal Computer) end and a local repeater, the double-wire connecting cable adopts a two-wire standard telephone wire, and the local repeater is connected with the PC end through a bus. The slave machine is a constant current receiver with two different currents. The utility model has the advantages of lower cost, good working stability and the like.

Description

Technical Field

[0001] This utility model belongs to the field of bus communication technology, specifically relating to a bus-based communication interface. Background Technology

[0002] In sensor data acquisition, bus technology improves efficiency through centralized management. Taking a smart factory as an example, hundreds of sensors are connected to a central controller via Modbus or PROFIBUS. The host polls each node according to priority, collecting data such as temperature and vibration in real time, and uploading it to a cloud analysis platform through a unified interface. This architecture not only reduces cabling but also supports modular expansion—adding a sensor only requires connecting it to the bus and configuring its address. Furthermore, the real-time performance and reliability of bus communication are enhanced through protocol optimization. For example, the CAN bus in automotive electronics ensures millisecond-level response between brake sensors and the ECU (Electronic Control Unit), while an error detection mechanism automatically retransmits damaged data to avoid system misjudgments. With the rise of edge computing, bus technology is converging with wireless transmission (such as LoRa), driving distributed sensor networks towards greater flexibility and intelligence. However, in practical applications, existing bus communication requires each slave device to have its own independent power supply, resulting in higher overall operating costs.

[0003] To address the shortcomings of existing technologies, people have conducted long-term explorations and proposed various solutions. For example, Chinese patent literature discloses an SPI bus communication system [201310647491.4], in which the host connects to an A / D converter, an E2PROM, and a slave device via a serial interface. The host and slave devices are microcontrollers, and the system also includes LED control drivers MAX7219 and HD7279, an integrated watchdog timer, and voltage monitoring. The SPI bus communication system of this invention uses a serial interface with the CPU, occupying only 4 I / O lines; it contains an internal decoder that can directly receive BCD or hexadecimal codes, and has two decoding modes to implement various control instructions such as LED digital tube bit addressing and segment addressing, blanking and blinking attributes; cyclic left shift and cyclic right shift instructions; and it contains an internal driver.

[0004] The above solution has solved the problem of sensor data transmission rate to some extent, but it still has many shortcomings, such as the high overall cost due to the independent power supply of the slave device. Summary of the Invention

[0005] The purpose of this invention is to address the above-mentioned problems by providing a reasonably designed bus-based communication interface that effectively reduces usage costs.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a bus-based communication interface, including a host, which is connected to multiple slave devices via a two-wire connection cable. The host includes a PC terminal and a local repeater. The two-wire connection cable uses a two-wire standard telephone line. The slave devices are constant current receivers with two different currents.

[0007] In the aforementioned bus-based communication interface, the host has a main transmitter and a main receiver.

[0008] In the aforementioned bus-based communication interface, the main transmitter has an inverter connected to the TX port and the inverter drives the bus BUSL. The output of the inverter in the main transmitter is connected to another non-inverting buffer, which in turn drives the bus BUSL.

[0009] In the aforementioned bus-based communication interface, the main receiver has a resistor R1 connected to the RX port and grounded, and the bus BUSL reads the signal.

[0010] In the aforementioned bus-based communication interface, the slave device has a bridge rectifier circuit composed of diodes D1, D2, D3, and D4. The bridge rectifier circuit is connected to the VDD port through a voltage regulator and connects the slave receiver and the slave transmitter.

[0011] In the aforementioned bus-based communication interface, the receiving unit includes a comparator or operational amplifier connected to the RX port, and the positive and negative input terminals of the comparator or operational amplifier are connected to the bus BUSL through resistors D3 and D4.

[0012] In the aforementioned bus-based communication interface, the transmitting unit includes an open-drain transistor D5 connected to the TX port.

[0013] In the aforementioned bus-based communication interface, the maximum length of the two-wire connection cable between the master and slave devices, as well as between slave devices, is 350m.

[0014] In the aforementioned bus-based communication interface, the number of slave devices ranges from 1 to 250, and the total length of the two-wire connection cable does not exceed 1000m.

[0015] In the aforementioned bus-based communication interface, the data rate of the two-wire connection cable is 300-11520Bd.

[0016] Compared with existing technologies, the advantages of this utility model are as follows: the dual-wire connection cable carries both signal communication and power transmission, eliminating the need for a separate power supply for the slave station, thereby reducing deployment costs; the non-polarity design, through a hardware-level automatic correction mechanism, fundamentally eliminates the construction complexity caused by polarity sensitivity, ensuring that system failures will not occur due to reverse polarity during installation, thereby improving construction efficiency and reducing error rates; and the signal transmission rate is improved by optimizing the current modulation communication mechanism and hardware acceleration. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of this utility model;

[0018] Figure 2 This is a waveform diagram of this utility model;

[0019] Figure 3 This is a circuit diagram of the host unit of this utility model;

[0020] Figure 4 This is a circuit diagram of the slave device of this utility model;

[0021] Figure 5 This is another circuit diagram of the slave device of this utility model;

[0022] In the diagram, the host is 1, the two-wire connecting cable is 2, and the slave is 3. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1 As shown, a bus-based communication interface includes a host 1, which is connected to multiple slave devices 3 via a two-wire cable 2. The host 1 includes a PC and a local repeater. The two-wire cable 2 uses a standard two-wire telephone line, carrying both communication signals and power transmission. The two cables simultaneously handle data exchange and energy transfer, eliminating the need for separate power lines for the slave devices 3. The slave devices 3 are constant current receivers with two different currents. They decode data by detecting two stable states of the bus current. The current direction does not affect signal interpretation; data decoding depends only on the current amplitude. During the current maintenance phase, they continuously acquire power through a rectifier bridge. The current changes both carry information and provide a window for energy transfer.

[0025] A Y-Bus system can consist of multiple so-called zones, each with its own group address, interconnected via zone controllers and higher-level networks. Each zone comprises multiple segments, which are connected by remote repeaters. However, typically, a Y-Bus system consists of only one segment, connected to a PC acting as the host via a local repeater. This local repeater converts the Y-Bus signal to an RS232 interface.

[0026] like Figure 2 As shown, bit transfer from master 1 to slave 3 is accomplished through voltage level shifting. A logic "1" (mark) corresponds to the nominal voltage Umax (repeater) at the output of the bus driver, which is part of master 1; when a logic "0" (space) is sent, the repeater reduces the bus voltage at its output by 2Umax to its nominal output Umax.

[0027] Bits sent from a slave device to a master device are encoded by modulating the current consumption of the slave device. A logic "1" is represented by a constant current (relative to voltage, temperature, and time) of up to Imin, while a logic "0" (space) is represented by an additional current consumption requirement of Imax from the slave device. The status current can be used to power the interface or possibly the instrument or sensor itself.

[0028] like Figure 2 As shown, sending space from the device causes the bus voltage on the repeater to drop slightly due to the output impedance.

[0029] The static state on the bus is logic "1", that is, the bus voltage on the repeater is Umax, and the maximum constant static current required by each slave device is Imin.

[0030] When there is no space to transmit from a device, the repeater on the drive bus will carry a constant current. Therefore, along with the cable resistance, the actual marked voltage of the slave device will be less than UmaxV, depending on the distance between the slave device and the repeater, and the total quiescent current of the slave device. Thus, the slave device cannot detect an absolute voltage level, but rather detects a voltage drop of 2Umax to indicate an interval. The repeater must adjust itself to accommodate the quiescent current level (mark) and interpret an increase in bus current of Imax as indicating an interval. This can only be achieved with acceptable complexity when the marked state is defined as Umax. This means that at any given time, transmission can only occur in one direction – from master 1 to slave 3, or from slave 3 to master 1 (half-duplex). Since the transmission voltage change in the master-slave direction is 2Umax, and the transmission current in the acknowledgment direction is at least Imax, a high degree of insensitivity to external interference is achieved, in addition to the remote power supply of slave 3.

[0031] like Figure 3As shown, host 1 has a main transmitting unit and a main receiving unit.

[0032] In addition, the main transmitter has an inverter connected to the TX port, which drives the BUSL bus. The output of the inverter in the main transmitter is connected to another non-inverting buffer, which in turn drives the BUSL bus. These two drivers work together to provide sufficient drive capability to ensure the integrity of the BUSL bus signal.

[0033] Simultaneously, the main receiving unit has a resistor R1 connected to the RX port and grounded, and the bus BUSL reads signals. The bus BUSL reads and returns a valid signal when the device signal is greater than the maximum operating current Imax.

[0034] like Figure 4-5 As shown, slave device 3 has a bridge rectifier circuit composed of diodes D1, D2, D3, and D4. Regardless of the polarity of the bus BUSL (alternating positive and negative voltages), the output always maintains a stable DC power supply. The bridge rectifier circuit is connected to the VDD port via a voltage regulator, connecting both the slave receiver and slave transmitter. Slave device 3 is designed as a constant current receiver with two different currents, so the current "absorbed" when the bus voltage changes by 1V must not exceed 0.2%. For transmission marking, a so-called unit load is specified, which consists of a constant current of maximum Imin. If slave device 3 requires more current, an appropriate number of additional unit loads must be used. During transmission, the current consumption of the slave device increases by Imax. To receive data, the slave device detects the maximum value Vmax of the bus voltage.

[0035] Clearly, the receiving section includes a comparator or operational amplifier connected to the RX port. The positive and negative input terminals of the comparator or operational amplifier are connected to the bus BUSL through resistors D3 and D4, and the output is a stable logic level.

[0036] Preferably, the transmitting unit includes an open-drain transistor D5 connected to the TX port. When the TX port needs to transmit a signal, the open-drain transistor D5, resistor R5, or constant current source acts as a bus load to pull the bus low, forming an Imax current, thus transmitting data.

[0037] Furthermore, the maximum length of the two-wire connection cable 2 between the host 1 and the slave 3, and between slave 3 and slave 3, is 350m.

[0038] Furthermore, the number of slave devices 3 is 1-250, and the total length of the dual-wire connecting cable 2 does not exceed 1000m.

[0039] In addition, the data rate of the two-wire connection cable 2 is 300-11520Bd.

[0040] In summary, the principle of this embodiment is as follows: through bus power supply technology, the slave device 3 obtains its working power from the communication line, eliminating the need for independent power supply wiring. Compared with traditional systems that require three or four wires, it can reduce cable costs by more than 50%, making it particularly suitable for large-scale distributed deployment scenarios. Through the hardware-level automatic correction mechanism, the construction complexity caused by polarity sensitivity is fundamentally eliminated. Its symmetrical design also provides greater flexibility for later system expansion, allowing for the dynamic addition or removal of nodes without stopping the system.

[0041] The specific embodiments described herein are merely illustrative examples illustrating the spirit of this utility model. Those skilled in the art to which this utility model pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of this utility model or exceeding the scope defined by the appended claims.

[0042] Although this document frequently uses terms such as "master unit 1," "two-wire connection cable 2," and "slave unit 3," the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this utility model; interpreting them as any additional limitation would contradict the spirit of this utility model.

Claims

1. A bus-based communication interface comprising a master (1) connected via a two-wire connection cable (2) to a plurality of slaves (3), characterized in that The host (1) comprises a PC end and a local repeater, the double-line connecting cable (2) adopts a two-line standard telephone line, and the slave (3) is a constant current receiver with two different currents.

2. The bus-based communication interface of claim 1, wherein, The host (1) has a main sending part and a main receiving part.

3. The bus-based communication interface of claim 2, wherein, The main sending part has an inverter connected with a TX port and driving a bus BUSL, and the output of the inverter of the main sending part is connected to another non-inverted buffer to drive the bus BUSL again.

4. The bus-based communication interface of claim 3, wherein, The main receiving part has a resistance R1 connected with a RX port and grounded, and the bus BUSL reads a signal.

5. The bus-based communication interface of claim 1, wherein, The slave (3) has a bridge rectifier circuit composed of diodes D1, D2, D3 and D4, the bridge rectifier circuit is connected with a VDD port through a voltage stabilizer, and the bridge rectifier circuit is connected with a slave receiving part and a slave sending part.

6. The bus-based communication interface of claim 5, wherein, The slave receiving part comprises a comparator or an operational amplifier connected with a RX port, and the positive and negative input ends of the comparator or the operational amplifier are connected with the bus BUSL through resistances D3 and D4.

7. The bus-based communication interface of claim 6, wherein, The slave sending part comprises an open-drain transistor D5 connected with a TX port.

8. The bus-based communication interface of claim 1, wherein, The maximum length of the double-line connecting cable (2) between the host (1) and the slave (3) and between the slave (3) and the slave (3) is 350 m.

9. The bus-based communication interface of claim 8, wherein, The number of the slave (3) is 1-250, and the total length of the double-line connecting cable (2) is not more than 1000 m.

10. The bus-based communication interface of claim 8, wherein, The data rate of the double-line connecting cable (2) is 300-11520 Bd.

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