Atomization board hardware circuit composed of 555 timer
By using a hardware circuit for the atomizing plate composed of a 555 timer and employing power filtering and three-legged inductor boost technology, the problems of miniaturization and stable mist output of the atomizing plate circuit have been solved, achieving stable mist output in an ultra-small space and meeting the application requirements of the medical, beauty and home fields.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-03-10
AI Technical Summary
There is room for improvement in the current atomizing plate circuits in terms of size reduction and stable mist output in ultra-small spaces, especially in applications in the medical, beauty and home fields where there are higher requirements for performance and stability.
The hardware circuit of the atomizing plate, which uses a 555 timer, includes a power interface circuit, a power filter circuit, a 555 timer and peripheral circuits, and a post-stage circuit. The power filter circuit generates a stable voltage, the 555 timer generates a stable square wave, and the voltage is boosted by a three-pin inductor before contacting the atomizing plate to achieve stable mist output.
Stable mist output is achieved in an ultra-small space with minimal and compact circuit components, meeting the application needs of medical, beauty, and home fields.
Smart Images
Figure CN223987083U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of atomizing plate circuit research technology, specifically an atomizing plate hardware circuit composed of a 555 timer. Background Technology
[0002] Nebulizers have wide applications in various fields such as medical, beauty, and home use. For example, in the medical field, they are used as an adjunct treatment for respiratory diseases such as asthma and colds; in the beauty field, they can be used for facial moisturizing and aromatherapy; and in the home, they can be used as humidifiers to increase indoor humidity and create a comfortable environment. These different applications place diverse demands on the performance, stability, and safety of atomizing plate circuits, driving the development of atomizing plate circuit design technology. In recent years, the continuous advancement of electronic technologies such as semiconductor devices, integrated circuits, and microprocessors has provided better technical support for atomizing plate circuit design. For example, high-performance microcontrollers can achieve precise control of the atomization process, including adjusting parameters such as atomization volume, atomization time, and operating frequency; new power amplifiers can improve driving capability and reduce energy consumption. However, there is still significant room for improvement in the current technology regarding the miniaturization of atomizing plate circuits and achieving stable mist output in ultra-small spaces. Utility Model Content
[0003] The purpose of this invention is to provide a hardware circuit for an atomizing plate composed of a 555 timer, so as to solve the problems mentioned in the prior art.
[0004] To achieve the above objectives, this utility model provides the following technical solution: a hardware circuit for an atomizing plate composed of a 555 timer, the circuit including a power interface circuit, a power filter circuit, a 555 timer and peripheral circuit, and a subsequent stage circuit; the power interface circuit is connected to the input terminal of the power filter circuit through a connector, the output terminal of the power filter circuit is connected to pins 8 and 4 of the 555 timer, and the 555 timer and peripheral circuit is connected to the gate (G) terminal of the NMOS transistor in the subsequent stage circuit.
[0005] In a more optimized configuration, the power interface circuit includes a connector CN1, a power supply VCC, and a ground GND, wherein pin 1 of connector CN1 is grounded, and pin 2 of connector CN1 is connected to the power supply VCC and the power filter circuit; the external wiring harness supplies power to the power filter circuit through CN1.
[0006] In a more optimized configuration, the power supply filter circuit includes capacitors C1, C2, and C3, which are connected in parallel. The first terminal of capacitor C1 is grounded and the second terminal is connected to VCC. The first terminal of capacitor C2 is grounded and the second terminal is connected to VCC. The first terminal of capacitor C3 is grounded and the second terminal is connected to VCC.
[0007] Using two 0805 capacitors and one 0603 capacitor in the power supply filter circuit can achieve a stable voltage and reduce the ripple of the subsequent circuit.
[0008] In a more optimized configuration, the 555 timer and its peripheral circuitry include a 555 timer U1, resistors R1, R2, and R3, and capacitors C4 and C5. The 555 timer U1 can be an NE555 model. Pin 1 of U1 is grounded; pin 2 is connected to the first terminal of capacitor C4 and the second terminal of resistor R2; pin 3 is connected to the first terminal of resistor R3; pin 4 is connected to pin 8, the first terminal of resistor R1, and the output terminal of the power supply filter circuit; pin 5 is connected to the first terminal of capacitor C5; pin 6 is connected to the second terminal of resistor R2; and pin 7 is connected to the first terminal of resistor R2 and the second terminal of resistor R1. The second terminal of capacitor C4 and capacitor C5 are grounded. The resistors and capacitors used in the 555 timer and its peripheral circuitry can generate a stable square wave.
[0009] In a more optimized configuration, the subsequent circuit includes a three-legged inductor L1, an NMOS transistor Q1, contact MARK1, and contact MARK2, wherein the NMOS transistor can be a CJ2310 model; pin 1 of the three-legged inductor L1 is connected to contact MARK1 and the second terminal of capacitor C2 in the power supply filter circuit, pin 2 is connected to the drain terminal of the NMOS transistor, and pin 3 is connected to contact MARK2; the source terminal of the NMOS transistor is grounded, and the gate terminal of the NMOS transistor is connected to the second terminal of R3 in the 555 timer and the peripheral circuit.
[0010] The subsequent circuit uses an NMOS transistor as a switch and a three-pin inductor to boost the voltage. When powered on, the output voltage of the three-pin inductor is the boosted voltage. The two contacts, MARK1 and MARK2, are used to contact the probe, which is connected to the atomizing plate, thus successfully producing mist.
[0011] Compared with the prior art, the beneficial effects of this utility model are:
[0012] This invention generates a stable voltage through a power supply filter circuit, generates a stable square wave using a 555 timer, and boosts the voltage using a three-pronged inductor before contacting a probe via contacts. The probe is then connected to the atomizing plate, thus successfully producing mist. The power supply filter circuit, the 555 timer, and the peripheral circuitry can generate a stable square wave, thereby producing stable mist. The entire mist-producing circuit uses the smallest and fewest circuit components, enabling stable mist production in an ultra-small space. Attached Figure Description
[0013] Figure 1 This is a circuit diagram of a hardware circuit for an atomizing plate composed of a 555 timer, according to the present invention.
[0014] Figure 2This is a circuit diagram of the power interface circuit of a hardware circuit for an atomizing plate composed of a 555 timer, according to this utility model.
[0015] Figure 3 This is a circuit diagram of the power supply filtering circuit of the atomizing plate hardware circuit composed of a 555 timer according to the present invention.
[0016] Figure 4 This utility model provides a circuit diagram of the 555 timer and its peripheral circuitry for an atomizing plate hardware circuit composed of a 555 timer.
[0017] Figure 5 This is a circuit diagram of the subsequent stage circuit of the atomizing plate hardware circuit composed of a 555 timer according to this utility model. Detailed Implementation
[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0019] like Figures 1-5 As shown, this utility model provides a technical solution: a hardware circuit for an atomizing plate composed of a 555 timer; as... Figure 1 As shown, the circuit includes a power interface circuit, a power filter circuit, a 555 timer and peripheral circuit, and a subsequent stage circuit. The power interface circuit is connected to the input terminal of the power filter circuit via a connector. The output terminal of the power filter circuit is connected to pins 8 and 4 of the 555 timer. The 555 timer and peripheral circuit is connected to the G terminal of the NMOS transistor in the subsequent stage circuit.
[0020] like Figure 2 As shown, the power interface circuit includes connector CN1, power supply VCC, and ground GND. Pin 1 of connector CN1 is grounded, and pin 2 of connector CN1 is connected to power supply VCC and power filter circuit. External wiring harnesses are connected to power filter circuit through CN1.
[0021] like Figure 3 As shown, the power supply filter circuit includes capacitors C1, C2, and C3, which are connected in parallel. The first terminal of capacitor C1 is grounded and the second terminal is connected to VCC. The first terminal of capacitor C2 is grounded and the second terminal is connected to VCC. The first terminal of capacitor C3 is grounded and the second terminal is connected to VCC.
[0022] Using two 22nF 0805 capacitors and one 100nF 0603 capacitor in the power supply filter circuit can achieve a stable voltage and reduce the ripple of the subsequent circuit.
[0023] like Figure 4 As shown, the 555 timer and peripheral circuit include a 555 timer U1, resistors R1, R2, and R3, and capacitors C4 and C5. The 555 timer U1 is an NE555 model. Pin 1 of U1 is grounded; pin 2 is connected to the first terminal of capacitor C4 and the second terminal of resistor R2; pin 3 is connected to the first terminal of resistor R3; pin 4 is connected to pin 8, the first terminal of resistor R1, and the output terminal of the power supply filter circuit; pin 5 is connected to the first terminal of capacitor C5; pin 6 is connected to the second terminal of resistor R2; and pin 7 is connected to the first terminal of resistor R2 and the second terminal of resistor R1. The second terminal of capacitor C4 and capacitor C5 are grounded.
[0024] The 555 timer and the resistors and capacitors used in the peripheral circuit can generate a stable square wave. The magnitude of the generated square wave can be obtained based on the resistance and capacitance values of the 555 timer and the peripheral circuit. The 555 timer and the peripheral circuit can generate a 100kHz square wave.
[0025] like Figure 5 As shown, the subsequent circuit includes a three-legged inductor L1, an NMOS transistor Q1, contact MARK1, and contact MARK2, wherein the NMOS transistor is a CJ2310 model; pin 1 of the three-legged inductor L1 is connected to contact MARK1 and the second terminal of capacitor C2 in the power supply filter circuit, pin 2 is connected to the drain terminal of the NMOS transistor, and pin 3 is connected to contact MARK2; the source terminal of the NMOS transistor is grounded; the gate terminal of the NMOS transistor is connected to the second terminal of R3 in the 555 timer and the peripheral circuit.
[0026] The subsequent circuit uses an NMOS transistor as a switch and a 25uh:800uh three-legged inductor to boost the voltage. When powered on, the output voltage of the three-legged inductor is the boosted voltage, which is 95-100V. The two contacts, MARK1 and MARK2, are used to contact the probe, which is connected to the atomizing plate, thus successfully producing mist.
[0027] Working principle: After the power is turned on, a stable voltage is obtained through the power filter circuit to reduce the ripple of the subsequent circuit. Then, a stable square wave is generated by the 555 timer and the resistors and capacitors used in the peripheral circuit. The voltage is then boosted by the three-pin inductor in the subsequent circuit and output to the contacts. The two contacts, MARK1 and MARK2, are used to contact the probe. The probe is connected to the atomizing plate, thus successfully producing mist.
[0028] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. An atomizing board hardware circuit consisting of a 555 timer, characterized in that: The circuit comprises a power interface circuit, a power filter circuit, a 555 timer and peripheral circuit and a post-stage circuit; the input end of the power interface circuit is connected with the power filter circuit, the output end of the power filter circuit is connected with the input end of the 555 timer and peripheral circuit, and the output end of the 555 timer and peripheral circuit is connected with the input end of the post-stage circuit.
2. The atomizing plate hardware circuit consisting of a 555 timer according to claim 1, characterized in that: The power interface circuit comprises a connector CN1, a power supply VCC and a ground GND, wherein the pin 1 of the connector CN1 is grounded, and the pin 2 of the connector CN1 is connected with the power supply VCC and the power filter circuit.
3. The atomizing board hardware circuit consisting of a 555 timer according to claim 2, characterized in that: The power filter circuit comprises a capacitor C1, a capacitor C2 and a capacitor C3; the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel, the first end of the capacitor C1 is grounded, the second end is connected with the power supply VCC, the first end of the capacitor C2 is grounded, the second end is connected with the power supply VCC, and the first end of the capacitor C3 is grounded, the second end is connected with the power supply VCC.
4. The atomizing plate hardware circuit comprised of a 555 timer according to claim 2, wherein: The 555 timer and peripheral circuit comprises a 555 timer U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C4 and a capacitor C5; the pin 1 of U1 is grounded, the pin 2 is connected with the first end of the capacitor C4 and the second end of the resistor R2, the pin 3 is connected with the first end of the resistor R3, the pin 4 is connected with the pin 8, the first end of the resistor R1 and the output end of the power filter circuit; the pin 5 is connected with the first end of the capacitor C5, the pin 6 is connected with the second end of the resistor R2, the pin 7 is connected with the first end of the resistor R2 and the second end of the resistor R1; the second end of the capacitor C4 is grounded, and the second end of the capacitor C5 is grounded.
5. The atomizing plate hardware circuit comprised of a 555 timer according to claim 2, wherein: The post-stage circuit comprises a three-pin inductor L1, an NMOS tube Q1, a contact MARK1 and a contact MARK2; the pin 1 of the three-pin inductor L1 is connected with the contact MARK1 and the second end of the capacitor C2 in the power filter circuit, the pin 2 is connected with the D end of the NMOS tube, and the pin 3 is connected with the contact MARK2; the S end of the NMOS tube is grounded, and the G end of the NMOS tube is connected with the second end of R3 in the 555 timer and peripheral circuit.