Receiving card Ethernet physical layer chip application circuit
By using the dual-port Ethernet physical layer chip YT8543, the circuit structure of the receiver card is simplified, solving the problems of complex circuits and large space occupation in the existing technology, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-03-10
AI Technical Summary
The existing Ethernet physical layer chip solution for receiver cards uses two independent chips, which results in complex circuitry, large space requirements, and inconvenient maintenance.
A dual-port Ethernet physical layer chip, YT8543, is used to input network signals through its two MAC ports and two RGMII ports, and to interact with the programmable logic chip FPGA, simplifying the circuit structure.
The circuit structure was optimized, reducing costs and space requirements.
Smart Images
Figure CN223987107U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic information technology, and in particular to an application circuit for an Ethernet physical layer chip of a receiver card. Background Technology
[0002] Currently, the vast majority of receiver cards on the market use two single-port Gigabit Ethernet physical layer chips. Because of these two independent chips, the power supply, clock, and function configuration signals need to be unified, which makes the circuit more complex, requires some repetitive processing, and makes later maintenance more troublesome. Furthermore, the larger number of components requires more space for PCB layout. Utility Model Content
[0003] The main purpose of this utility model is to propose a simple and low-cost Ethernet physical layer chip application circuit for receiver cards.
[0004] To achieve the above objectives, this utility model provides an application circuit for an Ethernet physical layer chip of a receiver card, including a dual-port Ethernet physical layer chip. The dual-port Ethernet physical layer chip includes two sets of MAC ports and two sets of RGMII ports. The two sets of MAC ports are used to input network port signals, and the two sets of RGMII ports are respectively connected to a programmable logic chip FPGA.
[0005] A further technical solution of this utility model is that the dual-port Ethernet physical layer chip is model YT8543.
[0006] A further technical solution of this utility model is that it also includes a clock input circuit for multiplying the RGMII signal. The clock signal of the clock input circuit is input to pin PIN67 of the dual-port Ethernet physical layer chip. The dual-port Ethernet physical layer chip is configured with ports CLKOUT0 and CLKOUT1 to output the 25MHz clock used by the programmable logic chip FPGA for operation.
[0007] A further technical solution of this utility model is that the two sets of RGMII ports of the dual-port Ethernet physical layer chip output two sets of RGMII signals to interact with the programmable logic chip FPGA, and configure the voltage and delay of the RGMII signals.
[0008] A further technical solution of this utility model is that the voltage of the RGMII signal is selected by configuring pins PIN45, PIN62 or PIN63 of the dual-port Ethernet physical layer chip.
[0009] A further technical solution of this utility model is that the dual-port Ethernet physical layer chip performs a coarse adjustment of the delay of TX and RX through pins PI N46 and PI N47.
[0010] A further technical solution of this utility model is that the address bits of the pins PIN30, PIN31 and PIN32 of the dual-port Ethernet physical layer chip are configured.
[0011] The dual-port Ethernet physical layer chip's pins PIN62 and PIN63 configure the running lights;
[0012] The network speed is configured via pin PIN49 of the dual-port Ethernet physical layer chip.
[0013] The dual-port Ethernet physical layer chip has pin PIN48 configured for sleep mode.
[0014] A further technical solution of this utility model is that the pin PI N34 of the dual-port Ethernet physical layer chip is configured for green Ethernet.
[0015] A further technical solution of this utility model is that the dual-port Ethernet physical layer chip is powered by an external power supply, wherein the power supply voltage is 3.3V or 1.1V, and the RGMII signal supports power supply of 3.3V, 2.5V, 1.8V or 1.5V.
[0016] A further technical solution of this utility model is that the two sets of MAC ports are connected to the MD I signal of an RJ45 or a network transformer.
[0017] The beneficial effects of the Ethernet physical layer chip application circuit of the receiver card of this invention are:
[0018] The present invention uses a dual-port Ethernet physical layer chip instead of two single-port Ethernet physical layer chips through the above technical solution. The signals from the two network ports are input into the two ports of the chip respectively. After data processing, the data is exchanged with the FPGA through the RGMII signal, which optimizes the circuit structure and reduces the cost. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0020] Figure 1This is a system block diagram of a preferred embodiment of the Ethernet physical layer chip application circuit of the receiver card of this utility model;
[0021] Figure 2 This is a schematic diagram of the circuit structure of the YT8543 chip;
[0022] Figure 3 This is a schematic diagram of the circuit structure of the external clock input circuit;
[0023] Figure 4 This is a schematic diagram of the output clock configuration;
[0024] Figure 5 This is a schematic diagram of the RGMII power supply configuration;
[0025] Figure 6 This is a schematic diagram of the RGMII de lay configuration;
[0026] Figure 7 This is a diagram illustrating the address bit configuration;
[0027] Figure 8 This is a schematic diagram of the running light configuration;
[0028] Figure 9 This is a diagram illustrating network speed configuration;
[0029] Figure 10 This is a diagram illustrating the sleep mode configuration;
[0030] Figure 11 This is a schematic diagram of a green Ethernet configuration;
[0031] Figure 12 This is a diagram of other configurations;
[0032] Figure 13 This is a schematic diagram of the power supply circuit;
[0033] Figure 14 This is a diagram of MAC signal connections;
[0034] Figure 15 This is a schematic diagram of FPGA-related signal connections.
[0035] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0036] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0037] This utility model proposes a method in which a dual-port receiver card Ethernet physical layer chip is used to replace two single-port Ethernet physical layer chips. The signals from the two network ports are input into the two ports of the chip respectively. After data processing, the data is exchanged with the programmable logic chip FPGA through the RGMII signal.
[0038] like Figure 1 As shown, a preferred embodiment of the Ethernet physical layer chip application circuit of the receiver card of this utility model includes a dual-port Ethernet physical layer chip. The dual-port Ethernet physical layer chip includes two sets of MAC ports and two sets of RGMII ports. The two sets of MAC ports are used to input network port signals, and the two sets of RGMII ports are respectively connected to a programmable logic chip FPGA.
[0039] In this embodiment, the dual-port Ethernet physical layer chip is model YT8543.
[0040] The YT8543 chip is not only simple in circuit structure and low in cost, but it is also a dual-port Ethernet physical layer chip with two sets of MAC and RGMII ports, supporting 10M / 100M / 1000M transmission and multiple correction functions.
[0041] The following section first explains the signal connections and configuration of the YT8543 chip.
[0042] like Figure 2 As shown, the use of the YT8543 chip is roughly similar to that of a single-port Ethernet physical layer chip, requiring the processing of power and MAC side, RGMII side, self-configuration and other related signals.
[0043] Regarding clock signal-related configurations, in this embodiment, the Ethernet physical layer chip application circuit of the receiver card further includes a clock input circuit for multiplying the RGMII signal. The clock signal of the clock input circuit is input to pins PIN66 and PIN67 of the dual-port Ethernet physical layer chip. The dual-port Ethernet physical layer chip is configured with ports CLKOUT0 and CLKOUT1 to output the 25MHz clock used by the programmable logic chip FPGA for operation.
[0044] The YT8543 chip requires an external 25MHz clock input to multiply the RGMII signal. The clock signal is input to pins PIN66 and PIN67 of the chip. Figure 3 As shown.
[0045] In addition, the YT8543 chip outputs the 25MHz clock used by the programmable logic chip FPGA through two ports, CLKOUT0 and CLKOUT1. Which port is used can be selected by configuring pins PIN29, PIN33, and PIN61. This embodiment uses CLKOUT1 as an example, and the relevant configuration is as follows: Figure 4 As shown.
[0046] In this embodiment, the two RGMII ports of the dual-port Ethernet physical layer chip output two sets of RGMII signals to interact with the programmable logic chip FPGA and configure the voltage and delay of the RGMII signals.
[0047] Specifically, in this embodiment, the relevant configuration of the RGMII signal is as follows:
[0048] The YT8543 chip has two sets of RGMII signals for data interaction with the FPGA programmable logic chip. The voltage and delay of these RGMII signals can be configured. The voltage of the RGMII signals can be selected by configuring pins 45, 62, and 63 of the dual-port Ethernet physical layer chip. The voltage can be provided by external 3.3V, 2.5V, 1.8V, and 1.5V, or by an internal LDO. This embodiment uses an external 3.3V as an example. Figure 5 As shown.
[0049] In this embodiment, the dual-port Ethernet physical layer chip can coarsely adjust the delays of TX and RX via pins PIN46 and PIN47, while fine-tuning can be achieved through software adjustments to the registers, such as... Figure 6 As shown.
[0050] In addition, in this embodiment, the YT8543 chip can also be configured with address bits, running lights, network speed, sleep mode, green Ethernet, etc.
[0051] Specifically, such as Figure 7 As shown, the pins PI N30, PI N31, and PI N32 of the dual-port Ethernet physical layer chip are configured with address bits.
[0052] like Figure 8 As shown, pins PI N62 and PI N63 of the dual-port Ethernet physical layer chip configure the running lights.
[0053] like Figure 9 As shown, pin PI N49 of the dual-port Ethernet physical layer chip configures the network speed.
[0054] like Figure 10 As shown, pin PI N48 of the dual-port Ethernet physical layer chip is used to configure the sleep mode.
[0055] like Figure 11 As shown, pin PI N34 of the dual-port Ethernet physical layer chip is configured for green Ethernet.
[0056] In addition, some other signals also require pull-up / pull-down configuration to function, such as Figure 12 As shown.
[0057] The following describes the power supply section of the Ethernet physical layer chip application circuit of the receiver card of this utility model.
[0058] In this embodiment, the dual-port Ethernet physical layer chip is powered by an external power supply, wherein the power supply voltage is 3.3V or 1.1V, and the RGMII signal supports power supply of 3.3V, 2.5V, 1.8V or 1.5V. The following description uses 3.3V as an example.
[0059] The 3.3V power supply domain includes AVDDH, ABDDHB, DVDDIO, DVDDH, and AVDDHX; the 1.1V power supply domain includes AVDDL, PLLVDDL, DVDDL, and AVDDLB. OR resistors are used to separate these domains for easier data measurement later. Decoupling capacitors are also added to ensure the stability of the chip's input power. The power supply schematic is shown below. Figure 13 As shown.
[0060] The following describes the external network portion of the Ethernet physical layer chip application circuit of the receiver card of this utility model.
[0061] First, for the MAC ports, the two sets of MAC ports of the YT8543 chip need to be connected to the MDI signals of the RJ45 or the network transformer. This embodiment uses the network transformer as an example. Each MAC port needs to correspond to the complete signal from the RJ45. The N and P signals of the MDI signal within the same group can be interchanged according to the specific layout. The specific connection is shown in the figures.
[0062] Secondly, regarding the RGMII port and clock, the YT8543 chip connects to the FPGA with two sets of RGMII signals, a clock signal, a reset signal, and an MDIO configuration signal. The input clock signal needs to be placed on the FPGA's CLK_IO, while the other signals can be placed on GPIO, as shown in the figures.
[0063] The beneficial effects of the Ethernet physical layer chip application circuit of the receiver card of this invention are:
[0064] The present invention uses a dual-port Ethernet physical layer chip instead of two single-port Ethernet physical layer chips through the above technical solution. The signals from the two network ports are input into the two ports of the chip respectively. After data processing, the data is exchanged with the FPGA through the RGMII signal, which optimizes the circuit structure and reduces the cost.
[0065] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the concept of the present utility model and using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present utility model.
Claims
1. A receiving card Ethernet physical layer chip application circuit, characterized in that, The double-port Ethernet physical layer chip includes two sets of MAC ports and two sets of RGMII ports, the two sets of MAC ports are used for inputting network port signals, and the two sets of RGMII ports are respectively connected with a programmable logic chip FPGA.
2. The receive card Ethernet physical layer chip application circuit of claim 1, wherein, The model of the double-port Ethernet physical layer chip is YT8543.
3. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, A clock input circuit for frequency multiplication of RGMII signals is further included, a clock signal of the clock input circuit is input to pins PIN66 and PIN67 of the double-port Ethernet physical layer chip, and ports CLKOUT0 and CLKOUT1 of the double-port Ethernet physical layer chip are configured to output a 25M clock used by the programmable logic chip FPGA.
4. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, Two sets of RGMII signals are output from the two sets of RGMII ports of the double-port Ethernet physical layer chip and are used for data interaction with the programmable logic chip FPGA, and the voltage and delay of the RGMII signals are configured.
5. The receive card Ethernet physical layer chip application circuit of claim 4, wherein, The voltage of the RGMII signals is selected by configuring pins PIN45, PIN62 or PIN63 of the double-port Ethernet physical layer chip.
6. The receive card Ethernet physical layer chip application circuit of claim 4, wherein, The double-port Ethernet physical layer chip coarsely adjusts the delay of TX and RX through pins PIN46 and PIN47.
7. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, Pins PIN30, PIN31 and PIN32 of the double-port Ethernet physical layer chip are configured for address bits. Pins PIN62 and PIN63 of the double-port Ethernet physical layer chip are configured for running lights. Pin PIN49 of the double-port Ethernet physical layer chip is configured for network rate. Pin PIN48 of the double-port Ethernet physical layer chip is configured for sleep mode.
8. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, Pin PIN34 of the double-port Ethernet physical layer chip is configured for green Ethernet.
9. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, The double-port Ethernet physical layer chip is powered by an external power supply, wherein the power supply voltage is 3.3V or 1.1V, and the RGMII signal supports 3.3V, 2.5V, 1.8V or 1.5V power supply.
10. The receive card Ethernet physical layer chip application circuit of claim 2, wherein, The two sets of MAC ports are connected with MDI signals of RJ45 or network transformers.