Hardware-level fault-tolerant method based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of TTE network fault tolerance, in particular to a hardware-level fault tolerance method based on an FPGA. The method comprises the following steps: respectively carrying out parallel preprocessing on a received TTE frame through a plurality of processing channels, then outputting a standardized bit stream, obtaining effective data through a voter, and simultaneously identifying and shielding a corresponding processing channel with a fault; and carrying out standardized integrity check, timestamp window check and physical layer link state monitoring on the voted effective TTE frame, and after the fault event is received, executing at least one of data error correction, clock switching, fault channel / link isolation and multistage recovery based on the fault type or / and severity level of the fault event. Through cooperation of hardware parallel processing and a special circuit, the fault detection and recovery speed reaches a microsecond level, a system of channel redundancy voting, multi-dimensional fault detection and hierarchical recovery is constructed, various faults are comprehensively shielded, and the anti-interference capability and operation stability of the network are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of TTE network fault tolerance technology, specifically to a hardware-level fault tolerance method based on FPGA. Background Technology

[0002] As a highly reliable network architecture that integrates time-triggered (TT) and event-triggered (ET) traffic, the fault tolerance mechanism of TTE networks is a core support for ensuring business continuity in critical fields such as industrial control and aerospace. However, existing TTE fault tolerance technologies mostly rely on software protocol stacks, which have inherent defects in multiple dimensions: On the one hand, the processing flow of traditional layered protocol stacks is complex and has huge overhead: TTE is based on Ethernet protocol stacks (such as TCP / IP), and data needs to go through multiple levels of encapsulation / decapsulation, such as application layer → transport layer → network layer → MAC layer. Each layer needs to add or remove VLAN tags, TTE synchronization frame headers and other header information. At the same time, data in multi-threaded environments needs to be copied repeatedly between user space and kernel space (such as the sk_buff cache overhead of Linux kernel protocol stack), and then the real-time time window check of the global time schedule (such as TTE scheduling matrix) is superimposed, which greatly increases the CPU load and directly leads to the unpredictability of terminal latency.

[0003] On the other hand, resource contention further exacerbates system instability: at the network link level, non-TT traffic (such as Best-Effort traffic) may block the TT data queue, causing scheduling jitter; at the CPU resource level, preemption by other processes such as background services will interfere with the execution time of TT tasks and disrupt the time-deterministic nature of time-triggered services.

[0004] More importantly, the fault response speed of existing fault-tolerance mechanisms is insufficient to meet the high real-time requirements: current TTEs mostly rely on periodic heartbeat messages to detect node or link faults. To avoid misjudgment, multiple heartbeat losses are usually required to trigger a fault alarm. If the heartbeat period is set to 100μs, at least 3 losses are required to determine the fault, and the detection delay has reached 300μs. In actual systems, in order to reduce heartbeat overhead, the heartbeat interval is often set to the millisecond level (e.g., 1ms). The fault detection delay needs to be superimposed with multiple timeout judgments (e.g., 3 times), and the final delay can increase to 3ms, which is far from meeting the stringent requirements of microsecond-level fault response.

[0005] To address the aforementioned issues, this invention proposes a hardware-level fault-tolerant solution based on FPGA. Through hardware architecture optimization, it enables rapid fault detection and recovery, balancing system reliability, real-time performance, and resource utilization. Summary of the Invention

[0006] The technical problem to be solved by this invention is to provide a hardware-level fault-tolerant method for TTE networks based on FPGA, which addresses the above-mentioned deficiencies of the prior art by achieving microsecond-level fault response through hardware-based parallel processing, multi-dimensional fault detection and hierarchical recovery strategies, thereby ensuring the continuity and integrity of TTE network data transmission.

[0007] The technical solution adopted by this invention to solve its technical problem is: to provide a hardware-level fault-tolerant method for TTE networks based on FPGA, including the following steps: The received TTE frames are preprocessed in parallel through multiple processing channels and then a standardized bit stream is output. A voter performs a bit-by-bit voting on the standardized bit streams of multiple processing channels, using multiple values ​​as valid data, while identifying and blocking the corresponding processing channels with faults. Standardized integrity verification, timestamp window checking, and physical layer link status monitoring are performed on valid TTE frames after voting. When an anomaly is detected, a corresponding fault event is generated. Upon receiving the fault event, based on the fault type and / or severity level of the fault event, at least one of the following is performed: data error correction, clock switching, fault channel / link isolation, and multi-level recovery. The normal operation of the data transmission path is restored quickly through hardware-based execution logic.

[0008] The preferred approach is that the processing channel performs preliminary data integrity verification, PTP timestamp alignment, and data formatting on the TTE frame during the preprocessing process, and outputs a standardized bit stream. The FPGA is equipped with three independent processing channels. The voter performs real-time bit-by-bit comparison of the standardized bit streams output by the three processing channels. It adopts a two-out-of-three voting rule and uses the majority value of the output results of the three processing channels as the valid data of the corresponding bit. It continuously detects the consistency of the three processing channels, and determines the processing channel whose output results are inconsistent with multiple values ​​as a faulty channel. It sends a shielding signal to the enable terminal of the faulty channel to isolate the faulty channel from the data transmission link.

[0009] A preferred embodiment is that the step of performing standardized integrity verification on the valid TTE frames after voting includes: After voting, the valid TTE frames are input into the CRC32 check circuit in byte stream order. The CRC32 check circuit calculates the CRC check value in real time based on the standard preset generator polynomial and performs a hardware-level comparison with the preset check code carried in the TTE frame header. If the CRC check value matches the preset check code, the data is deemed complete, and the data of the valid TTE frame is allowed to be transmitted downwards. If the CRC check value is inconsistent with the preset check code, it is determined to be a bit error or frame tampering abnormality, triggering an interrupt signal and generating the first fault event.

[0010] A preferred embodiment is that the step of performing a timestamp window check on the valid TTE frames after voting includes: The PTP receive timestamp of the TTE frame after voting is captured in real time, and the timestamp is aligned with the phase of the global clock through a digital delay phase-locked loop. The global scheduling table of the TTE network is pre-loaded, which includes the expected arrival time range and time window threshold of each frame. The expected arrival time parameter of the current frame is retrieved in real time to form a time window interval from the expected start time to the expected end time. The aligned PTP receiving timestamp is then compared with the time window interval in real time. If the PTP received timestamp falls within the time window interval, it is determined to be time compliant, and the time window threshold of the data stream to which the TTE frame belongs is updated; If the PTP received timestamp exceeds the upper limit of the time window interval or falls below the lower limit of the time window interval, it is determined to be a scheduling jitter, abnormal link delay, or frame loss risk. The time deviation value is recorded, an interrupt signal is triggered, and a second fault event is generated.

[0011] A preferred embodiment includes a physical layer chip connected to the FPGA via a physical link. The steps for processing the valid TTE frames after voting include: The physical link is initially in an idle state. When a valid signal is detected, it switches to a synchronization state and initiates the clock and data synchronization process. After clock locking and data frame synchronization are completed in the synchronization state, it enters the normal working state; In normal operation, the period of continuous valid signals is counted, and it is determined whether parameters such as signal amplitude meet the preset threshold. If the bit error rate is detected to exceed the threshold, it is determined to be in a fault state, a third fault event is generated, and the system switches to the warning state. In the early warning state, continuously monitor the fault status. If the fault status persists, enter the resynchronization state and initiate link resynchronization. In the resynchronization state, if resynchronization is successful, it returns to the normal working state; if it fails to recover within a timeout period, it switches to the fault state.

[0012] The better option is: The data error correction includes the following steps: executing the BCH error correction encoder to perform real-time error correction on bit errors or frame tampering anomalies determined in the standardized integrity check; after the error correction is completed, triggering the CRC32 check circuit to perform a secondary check on the repaired data; if the secondary check passes, the system will operate normally; if the secondary check fails, the fault level will be upgraded and fault channel / link isolation operation will be triggered. The clock switching steps include: when the main clock is detected to have no valid rising edge for a continuous period or the frequency offset exceeds the preset range, the clock switching process is immediately triggered; the local clock counter is frozen to maintain the continuity of time counting; then the backup clock is enabled, and the phase alignment between the backup clock and the global clock is completed through a digital delay phase-locked loop. After the clock sources of all time-related modules inside the FPGA are updated synchronously, the operation of the local clock counter is restored to ensure that the global time synchronization state is not interrupted.

[0013] The better option is: The steps for isolating the faulty channel / link include: Based on the fault event location, the corresponding fault channel or physical link is located, and isolation instructions are written to the switch's control register via the axi-lite bus. Cut off the power supply path of the physical layer chip corresponding to the faulty channel / link to physically isolate the faulty object; If the faulty object is a processing channel, the corresponding processing channel will be automatically blocked, and the output of valid data will be adjusted synchronously. If the faulty object is a physical link, the system will immediately switch to the backup redundant link and update the transmission path parameters of the corresponding data stream in the TTE network global scheduling table.

[0014] A preferred embodiment is that the multi-level recovery steps include: A fast recovery finite state machine is constructed, which continuously receives fault events under normal conditions; When a fault event is detected, the system enters the fault detection state, and, based on the fault type and / or severity level, determines and classifies it into correctable and uncorrectable errors. If the judgment result is a correctable error, data error correction is performed; after the error correction is completed, the system enters the recovery verification state to complete the validity verification; after the validity verification is passed, the system runs normally. If the judgment result is an uncorrectable error, the fault channel / link isolation is triggered; after the isolation is completed, the system enters the system reconstruction state to perform system reconstruction operations. During the reconstruction process, clock switching or link switching adaptation is completed synchronously. After the reconstruction verification is successful, the system returns to normal operation.

[0015] One preferred approach is to include FPGA resource performance optimization management, which includes the following steps: through the collaborative design of pipelined parallel processing, on-chip hierarchical memory architecture, clock gating and dynamic power consumption adjustment, the FPGA resource utilization, data transmission latency and power consumption are optimized while ensuring microsecond-level fault detection and recovery performance.

[0016] The better option is: The pipelined parallel processing includes breaking down the TTE frame preprocessing, integrity verification, data voting, and fault recovery process into multi-level continuous processing stages. Through pipelined task allocation and delay balancing of critical processing paths, each processing stage is executed in parallel in sequence. The tiered storage access includes constructing a three-level tiered storage unit, which comprises a first-level storage module, a second-level storage module, and a third-level storage module. The first-level storage module stores the metadata of the currently processed TTE frame, the second-level storage module stores the TTE network global scheduling table and data stream status information, and the third-level storage module is used for large-capacity temporary buffering of TTE frames. The data access path is shortened by prioritizing on-chip storage access over external storage interaction. The dynamic clock control includes real-time monitoring of the working status and performing a clock shutdown operation on idle modules that are not processing tasks. The adaptive power consumption adjustment includes real-time monitoring of task load and operating temperature, and dynamic adjustment of operating voltage and frequency according to load changes; when a sudden high load task is detected, it switches to performance priority mode and shuts down the clock supply of non-core processing modules; when the operating temperature reaches the preset temperature threshold, it performs frequency reduction operation and shuts down some redundant processing mechanisms, enables heat dissipation adaptation strategy, and gradually restores the original operating configuration after the temperature returns to the normal range.

[0017] The beneficial effects of this invention are as follows: Compared with the prior art, this invention achieves fault detection and recovery speeds at the microsecond level through hardware-based parallel processing and dedicated circuitry, and constructs a system for channel redundancy voting, multi-dimensional fault detection, and hierarchical recovery, comprehensively shielding various faults and significantly improving network anti-interference capabilities and operational stability; furthermore, the core processes are implemented in hardware using FPGA, avoiding additional software overhead and CPU resource competition, balancing high throughput and low power consumption, and achieving a balance between performance and efficiency; finally, the hierarchical recovery strategy adapts to different fault types and levels, enabling rapid repair of simple errors and precise isolation of severe faults, reducing redundancy costs and improving robustness. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a flowchart illustrating the hardware-level fault-tolerant method for TTE networks based on FPGA of the present invention. Figure 2 This is a schematic diagram of the FPGA framework of the present invention; Figure 3 This is a schematic diagram of the process for channel processing and voting in this invention; Figure 4 This is a schematic diagram of the process of performing standardized integrity verification on valid TTE frames after voting according to the present invention; Figure 5 This is a schematic diagram of the process of performing timestamp window checks on valid TTE frames after voting according to the present invention. Figure 6 This is a schematic diagram of the process of monitoring the physical layer link status of valid TTE frames after voting according to the present invention. Figure 7 This is a flowchart illustrating the data error correction process of this invention; Figure 8 This is a schematic diagram of the clock switching process of the present invention; Figure 9 This is a flowchart illustrating the fault channel / link isolation process of the present invention; Figure 10 This is a schematic diagram of the multi-level recovery process of the present invention; Figure 11 This is a flowchart illustrating the FPGA resource performance optimization management process of this invention. Detailed Implementation

[0019] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] like Figure 1 and Figure 2 As shown, the present invention provides a preferred embodiment of a hardware-level fault-tolerant method for TTE networks based on FPGA.

[0021] A hardware-level fault-tolerant method for TTE networks based on FPGA includes the following steps: Step S10: After parallel preprocessing of the received TTE frames through multiple processing channels, a standardized bit stream is output. A voter performs bit-by-bit voting on the standardized bit streams of the multiple processing channels, using multiple values ​​as valid data, while identifying and blocking the corresponding processing channels with faults; Step S20: Standardized integrity verification, timestamp window checking, and physical layer link status monitoring are performed on the valid TTE frames after voting. When an abnormality is detected, a corresponding fault event is generated; Step S30: After receiving the fault event, based on the fault type and / or severity level of the fault event, at least one of data error correction, clock switching, fault channel / link isolation, and multi-level recovery is performed to quickly restore the normal operation of the data transmission path through hardware-based execution logic.

[0022] In this embodiment, regarding multi-channel parallel preprocessing and voting fault tolerance, the present invention constructs multiple independent processing channels within the FPGA to form a parallel processing architecture, preferably three processing channels. Each processing channel independently receives externally input TTE frames and synchronously performs preprocessing operations. The preprocessing process revolves around the data standardization goal, ensuring that the output data format of each channel is uniform and comparable, providing a basis for subsequent voting. After preprocessing, the data from each channel is output in the form of a standardized bitstream and transmitted to the hardware voter integrated within the FPGA.

[0023] The hardware voter performs real-time bit-by-bit voting on the standardized bitstreams of multiple processing channels, employing a "multiple-value valid" voting logic. This means that the bit value that appears most frequently in the output results of all channels is considered valid data for that bit, and a reliable valid TTE frame is formed through the hardware voter's output. During the voting process, the hardware voter synchronously monitors the output consistency of each processing channel: if the output result of a processing channel is consistently inconsistent with the output results of the majority of processing channels, it is determined that the processing channel is faulty. A shielding signal is then sent to its enable terminal, isolating the faulty processing channel from the data transmission link to prevent faulty data from affecting subsequent transmissions. Simultaneously, the remaining normal channels continue to maintain data processing and transmission functions, achieving channel-level redundancy and fault tolerance.

[0024] In this embodiment, regarding multi-dimensional fault detection and fault event generation, a triple fault detection mechanism is constructed for valid TTE frames after voting. Comprehensive monitoring is carried out from three dimensions: data integrity, transmission timing compliance, and physical layer link stability, to ensure accurate fault identification and timely feedback. Specifically, standardized integrity verification, timestamp window checking, and physical layer link status monitoring are performed on valid TTE frames after voting.

[0025] In the standardized integrity verification, the focus is on the data integrity of TTE frames. Valid TTE frames are verified using a dedicated hardware verification circuit (see below for details) to check for anomalies such as bit errors and frame tampering during data transmission or processing, ensuring the reliability of the data itself. In the timestamp window check, based on the time-triggered characteristics of the TTE network, hardware timestamp capture and comparison logic is used to verify whether the arrival time of valid TTE frames meets the global scheduling requirements, and to promptly identify timing-related faults such as scheduling jitter, abnormal link delays, or frame loss risks. In the physical layer link status monitoring, the operating status of the physical links on which TTE frame transmission depends is monitored in real time, including key indicators such as link signal quality and connectivity, to identify physical layer anomalies such as signal loss and electrical faults.

[0026] When any of the above detection mechanisms detects an anomaly, a corresponding fault event is immediately generated. The fault event contains core information such as the fault type, the associated objects of the fault, and the timing of the fault occurrence, providing a basis for decision-making in subsequent recovery operations.

[0027] In this embodiment, regarding hardware-based graded recovery and path normalization, the FPGA integrates an intelligent recovery control unit. The intelligent recovery control unit receives fault events generated by various fault detection mechanisms in real time. Based on the fault type carried in the fault event, such as data error, timing abnormality, link failure, clock failure, etc., and the fault severity level, such as minor correctable error, severe uncorrectable error, etc., a graded recovery strategy is executed.

[0028] The recovery operation encompasses various methods, including data error correction, clock switching, faulty channel / link isolation, and multi-level recovery. The specific recovery method is dynamically selected by the intelligent recovery control unit based on the actual fault situation: for minor, correctable faults, data is quickly repaired through hardware error correction logic; for clock-related faults, a backup clock source is switched to maintain time synchronization; for faulty channels or links that severely affect transmission, physical isolation is performed and a switch to redundant resources is initiated; for complex faults, a multi-level recovery process is used to achieve system reconstruction and functional restoration. All recovery operations are implemented through FPGA hardware logic, requiring no software intervention and possessing rapid hardware execution characteristics, ensuring fault response and recovery are completed within microseconds, quickly restoring the normal operation of data transmission paths, and minimizing the impact of faults on TTE network services.

[0029] Therefore, fault detection and recovery speeds are significantly improved. By employing hardware-based parallel processing, dedicated fault detection circuits, and hardware recovery logic, the processing latency limitations of software protocol stacks are eliminated, with fault detection and recovery times controlled at the microsecond level, far superior to traditional millisecond-level response schemes, meeting the stringent real-time requirements of critical fields. Furthermore, fault tolerance and reliability are enhanced. A full-link fault-tolerant system based on channel-level redundant voting, multi-dimensional fault detection, and hierarchical recovery is constructed. Hardware-level redundancy and monitoring are implemented from data processing and fault identification to recovery execution, effectively shielding various faults such as channel failures, data errors, and link anomalies, significantly improving the anti-interference capability and operational stability of the TTE network. Additionally, the FPGA-based hardware implementation avoids the additional overhead of software processing. At the same time, through parallel architecture and dedicated circuit design, CPU resource consumption and system power consumption are reduced while ensuring fault tolerance performance, achieving an optimized balance between performance and resource consumption. Finally, the core logic is implemented through FPGA hardware, independent of specific software platforms or operating systems, and can be adapted to TTE network architectures in different scenarios. It also supports flexible configuration of parameters such as the number of processing channels, fault detection accuracy, and recovery strategies to meet diverse application needs. It is suitable for critical fields such as industrial control, aerospace, and automotive electronics where real-time performance and reliability are extremely important.

[0030] like Figure 2 and Figure 3 As shown, the present invention provides a preferred embodiment of processing channel processing and voting.

[0031] During the preprocessing process, each processing channel performs preliminary data integrity verification (S111) of the TTE frame, PTP timestamp alignment (S112), and data formatting (S113), outputting a standardized bit stream. Three independent processing channels are built within the FPGA. The hardware voter enters step S12, performing real-time bit-by-bit comparison of the standardized bit streams output by the three processing channels. A two-out-of-three voting rule is adopted, and the majority value among the output results of the three processing channels is used as the valid data for the corresponding bit. The consistency of the three processing channels is continuously monitored. Processing channels whose output results are inconsistent with multiple values ​​are identified as faulty channels, and a shielding signal is sent to the enable terminal of the faulty channel to isolate it from the data transmission link.

[0032] In this embodiment, regarding the multi-channel parallel preprocessing mechanism, three completely independent processing channels are constructed within the FPGA chip. These three channels are isolated from each other in hardware architecture, including independent signal receiving interfaces, data processing logic units, power supply chains, and clock drive modules. This ensures that a failure in one processing channel will not propagate to other channels, providing a reliable hardware foundation for subsequent redundant voting. Each processing channel synchronously performs preprocessing operations on the received TTE frames. To standardize the data, the preprocessing process sequentially completes three key steps: preliminary data integrity verification, PTP timestamp alignment, and data formatting. The final output is a standardized bitstream with a unified format that can be directly compared.

[0033] In the initial data integrity check, the frame header identifier, frame length, and checksum field of the received TTE frames are preliminarily checked to quickly filter out invalid frames with obvious frame structure errors, abnormal lengths, or failed header checks, preventing invalid data from entering subsequent processing and reducing system redundancy overhead. In the PTP timestamp alignment, each processing channel has built-in independent timestamp capture and calibration logic to capture the PTP timestamp information carried by the TTE frames in real time, and perform phase calibration and deviation compensation on the timestamps captured by each processing channel based on the FPGA's internal global reference clock, ensuring that the timestamp data output by the three processing channels has a unified time base and eliminating the impact of timing deviations between channels on subsequent voting. In the data formatting process, the TTE frame data that has undergone the above initial checks and timestamp alignment are reassembled and encoded according to a preset unified data format, including frame header field standardization, data segmentation by fixed bit width, and unified encoding of control fields, so that the bit streams output by the three processing channels are completely consistent in data structure, field definition, and bit width specifications, meeting the comparison requirements of bit-by-bit voting.

[0034] In this embodiment, regarding the 2-out-of-3 hardware voting and fault channel isolation, the standardized bitstreams output from the three processing channels are synchronously input to the hardware voter integrated within the FPGA. The hardware voter, implemented with pure hardware logic, possesses sub-microsecond real-time voting capabilities, ensuring data reliability screening is completed without introducing additional latency. The hardware voter performs real-time bit-by-bit comparison and executes the 2-out-of-3 voting rule. For the standardized bitstreams output from the three processing channels, it performs real-time comparisons bit-by-bit in sequence, counting the frequency of each bit's value (e.g., 0 and 1) across the three processing channels. The value with the most frequent occurrences is determined as the valid data for that bit. All valid data bits are combined to form the final valid TTE frame, which is output to the subsequent fault detection stage. While performing the voting operation, the consistency of the output from the three processing channels is continuously monitored. If, during the voting process of multiple consecutive data frames, the output bitstream of a certain processing channel is consistently inconsistent with multiple values ​​from the other two channels, it is determined that the channel has a hardware fault or data processing anomaly, and the fault channel isolation mechanism is triggered.

[0035] The fault channel isolation is achieved through hardware enable signal control. The hardware voter sends a high-level shielding signal to the enable terminal of the faulty processing channel, cutting off the signal output path of the processing channel and preventing it from participating in subsequent data voting and transmission processes. At the same time, the hardware voter automatically adjusts the voting logic, executing a "two-out-of-one" voting rule based on the output of the remaining two normal processing channels. That is, the consistent value of the two channels is considered valid data, ensuring that the system can still maintain normal data processing and transmission functions after isolating the faulty channel, achieving seamless shielding of channel-level faults and ensuring the continuity and reliability of TTE network data transmission.

[0036] like Figures 4 to 6 As shown, the present invention provides a preferred embodiment for performing standardized integrity verification, timestamp window checking, and physical layer link status monitoring on valid TTE frames after voting.

[0037] refer to Figure 4 The step of performing standardized integrity verification on the valid TTE frames after voting includes: Step S211: After voting, the valid TTE frames are input into the CRC32 check circuit in byte stream order. The CRC32 check circuit calculates the CRC check value in real time based on the standard preset generator polynomial and performs a hardware-level comparison with the preset check code carried in the TTE frame header. Step S212: If the CRC check value matches the preset check code, the data is determined to be complete, and the data of the valid TTE frame is allowed to be transmitted downwards. Step S213: If the CRC check value does not match the preset check code, it is determined to be a bit error or frame tampering abnormality, triggering an interrupt signal and generating the first fault event.

[0038] In this embodiment, to ensure that no bit errors or frame tampering occur during the transmission or processing of valid TTE frames after voting, a standardized CRC32 verification mechanism is adopted. The verification process is executed in real time and efficiently through a hardware-based CRC32 verification circuit.

[0039] Valid TTE frames after voting are input synchronously to the dedicated CRC32 check circuit integrated within the FPGA in the form of a continuous byte stream, following the transmission order. The CRC32 check circuit constructs its hardware logic based on the generator polynomial preset in the IEEE 802.3 standard, employing a parallel processing architecture design. It can complete the CRC check value calculation for multi-byte data within a single clock cycle, avoiding the accumulation of latency caused by serial processing and ensuring the parallel and synchronous execution of the check process and the data transmission process. After the CRC32 check circuit starts, it performs real-time continuous calculations on the input byte stream data, dynamically generating the CRC check value of the current TTE frame. Simultaneously, the CRC32 check circuit extracts the standard checksum pre-calculated and carried at the sending end from the preset field in the TTE frame header. It then performs a hardware-level real-time comparison between the real-time calculated CRC checksum and the extracted preset checksum—this comparison is implemented entirely through pure hardware logic gates, requiring no software intervention, ensuring immediate feedback of the comparison results.

[0040] In step S212, if the real-time calculated CRC check value is completely consistent with the preset check code carried in the frame header, it is determined that the data integrity of the valid TTE frame has not been damaged and there are no abnormalities such as bit errors or frame tampering. The CRC32 check circuit outputs a "check passed" signal, allowing the data of the valid TTE frame to continue to be transmitted to the downstream timestamp window check stage and enter the subsequent processing flow.

[0041] In step S213, if the real-time calculated CRC check value is inconsistent with the preset check code, it is directly determined that the valid TTE frame has a bit error, such as bit flipping caused by signal interference during transmission, or abnormal frame tampering, such as illegal data modification. The CRC32 check circuit immediately triggers a hardware interrupt signal and automatically generates a first fault event. The first fault event includes core information such as fault type, fault-related frame identifier, check deviation information, and fault occurrence timestamp, which is synchronously transmitted to the intelligent recovery control unit to provide accurate decision-making basis for subsequent data error correction or fault isolation operations.

[0042] Here is an implementation case: Suppose that the frame identifier of a data stream in a TTE network is “Frame_001” (used to uniquely distinguish different TTE frames). The standard CRC32 check code of this frame is “0x12345678” pre-calculated at the sending end and carried in the frame header. When the frame is input into the CRC32 check circuit after multi-channel voting, a bit in the frame data is flipped due to slight signal interference during transmission. At this time, the CRC32 check circuit calculates the check value as "0x12345679" in real time, which is inconsistent with the preset check code "0x12345678" in the frame header. The first fault event is then generated. Its core content is as follows: the fault type is data integrity abnormality (bit error), the fault associated frame identifier is Frame_001, the check deviation information is calculated, the difference between the check value (0x12345679) and the preset check code (0x12345678) is 0x00000001, the corresponding data 8th bit is flipped (which can be derived by reverse deduction through the check logic), and the fault occurrence timestamp is 1698765432100 (based on the global clock, unit: ns). After the first fault event is synchronously transmitted to the intelligent recovery control unit through the FPGA internal hardware signal link, the control unit can make a quick decision based on the event content: if it is clear that the fault is a bit error in "Frame_001" and the erroneous bit has been located, it is a minor fault that can be corrected. There is no need to perform fault isolation. The BCH error correction engine is directly triggered to flip and repair the 8th bit of the frame. After the repair is confirmed by a second verification, normal transmission can be restored. The entire decision-making and execution process does not require software intervention and achieves microsecond-level response.

[0043] refer to Figure 5 The step of performing a timestamp window check on the valid TTE frames after voting includes: Step S221: Capture the PTP receive timestamp of the TTE frame after voting in real time, and align the timestamp with the global clock phase using a digital delay-locked loop; Step S222: Pre-load the global scheduling table of the TTE network, which includes the expected arrival time range and time window threshold of each frame, and retrieve the expected arrival time parameter of the current frame in real time to form a time window interval from the expected start time to the expected end time. Compare the aligned PTP receive timestamp with the time window interval in real time; Step S223: If the PTP receive timestamp falls within the time window interval, it is determined to be time compliant, and the time window threshold of the data stream to which the TTE frame belongs is updated; Step S224: If the PTP receive timestamp exceeds the upper limit of the time window interval or is lower than the lower limit of the time window interval, it is determined to be a scheduling jitter, abnormal link delay, or frame loss risk. Record the time deviation value, trigger an interrupt signal, and generate a second fault event.

[0044] In this embodiment, the timestamp window checking mechanism accurately verifies the transmission timing of valid TTE frames after voting, promptly identifying timing-related faults such as scheduling jitter and abnormal link delays, ensuring that data transmission meets global scheduling requirements.

[0045] First, upon entering the timestamp check stage, the valid TTE frame after voting is immediately captured in real-time by the dedicated timestamp capture module within the FPGA, which captures the PTP timestamp information carried in the frame. The timestamp capture module operates synchronously with the TTE frame's transmission link, ensuring accurate extraction of the preset PTP timestamp field from the frame header, containing both second- and nanosecond-level time information, as the frame data is fully received, thus avoiding timestamp capture delays or omissions. Second, due to timing deviations in various processing channels and signal delays in the transmission link, the captured PTP timestamp may have a phase deviation from the FPGA's internal global clock. Therefore, a digital delay-locked loop (DLL) circuit is used to perform phase alignment processing on the captured PTP timestamp: using the FPGA's high-precision internal global reference clock as a benchmark, the DLL's phase detection and delay compensation logic calibrates the PTP timestamp's phase offset in real-time, eliminating the effects of timing differences between channels and link delays. This ensures that the final output timestamp data has a unified and accurate time reference, providing a reliable timing basis for subsequent time window comparisons.

[0046] Furthermore, a time window interval is constructed. Before the TTE network operates, a global scheduling table is pre-stored in the on-chip high-speed storage unit of the FPGA. This global scheduling table contains core scheduling parameters such as the expected arrival time range of TTE frames corresponding to all data streams and the time window threshold. The expected arrival time range is calculated based on the frame transmission period and transmission path delay budget determined during the network planning phase. The time window threshold is flexibly configured according to the real-time requirements of the data streams; for example, higher-priority data streams are configured with narrower time windows, while lower-priority data streams are configured with relatively looser time windows. During timestamp checking, based on the data stream identifier of the currently received TTE frame, such as the stream ID field in the frame header, the expected arrival time parameter corresponding to that data stream is retrieved in real time from the global scheduling table. A fixed-length time window interval is constructed with the expected start time and expected end time as boundaries. For example, if the expected arrival time of a TTE frame for a certain data stream is 1000ns and the configured time window threshold is ±50ns, then the constructed time window interval is 950ns~1050ns. Only TTE frames arriving within this interval are considered time-compliant.

[0047] Furthermore, the real-time timestamp comparison and result determination involves comparing the PTP received timestamp, which has been phase-aligned by a digital delay phase-locked loop, with the constructed time window interval in real time at the hardware level. The comparison logic is implemented by pure hardware circuitry to ensure that there is no software delay in the comparison process and to meet the microsecond-level response requirements. If the value of the PTP received timestamp falls within the preset time window interval, such as 950ns~1050ns in the example above, then the transmission timing of the TTE frame is determined to be compliant, indicating that there is no significant jitter in the current network scheduling and the link delay is within the normal range. At this point, the time window threshold of the data stream to which the TTE frame belongs is automatically updated. Based on the deviation between the actual arrival time and the expected arrival time, the time window range of the next frame is dynamically fine-tuned. For example, if the actual arrival time is 980ns, slightly lower than the expected 1000ns, the time window range of the next frame can be fine-tuned to 940ns~1040ns, achieving adaptive optimization of the time window and improving the adaptability to slight network jitter. If the value of the PTP received timestamp exceeds the upper limit of the time window range, such as exceeding 1050ns in the above example, or is lower than the lower limit of the range, such as being lower than 950ns, a timing anomaly is determined to exist. Possible fault types include network scheduling jitter, abnormal link delay, or frame loss risk. At this time, the time deviation value is immediately recorded, that is, the difference between the actual PTP received timestamp and the midpoint of the time window range. For example, if the actual arrival time is 1080ns, the deviation value is +30ns, triggering a hardware interrupt signal and generating a second fault event.

[0048] The second fault event includes core information such as fault type, associated data stream identifier, actual PTP timestamp, time deviation value, and time window interval parameters, which are synchronously transmitted to the intelligent recovery control unit to provide accurate timing data support for subsequent recovery operations such as clock calibration, link status adjustment, or schedule optimization.

[0049] refer to Figure 6 It also includes a physical layer chip connected to the FPGA via a physical link. The step of monitoring the physical layer link status of the valid TTE frames after voting includes: Step S231: The physical link is initially in an idle state. When a valid signal is detected, it switches to a synchronization state and starts the clock and data synchronization process. Step S232: After clock locking and data frame synchronization are completed in the synchronization state, it enters the normal working state. Step S233: In the normal working state, the period of continuous valid signals is counted, and it is determined whether parameters such as signal amplitude meet the preset threshold. If the bit error rate is detected to exceed the threshold, it is determined to be in a fault state, a third fault event is generated, and it switches to the warning state. Step S234: In the warning state, the fault state is continuously monitored. If it remains in a fault state, it enters the resynchronization state and starts link resynchronization. Step S235: In the resynchronization state, if resynchronization is successful, it returns to the normal working state. If it does not recover after a timeout, it switches to the fault state.

[0050] In this embodiment, regarding the physical layer link status monitoring mechanism, in order to ensure the reliability of the physical carrier for TTE frame transmission, a physical layer chip is set up that is directly connected to the FPGA via a physical link. At the same time, a link status monitoring state machine is built inside the FPGA. Through multi-state transition logic, the operating status of the physical link is monitored throughout its entire life cycle, and physical layer anomalies such as signal loss, electrical faults, and excessive bit error rate are identified in real time.

[0051] In step S231, the initial idle state and synchronization state are triggered. The initial state of the physical link is idle, at which time the physical link is not transmitting valid TTE frame data. The link status monitoring module inside the FPGA continuously monitors the input signal of the physical link. On the one hand, it monitors whether there is a valid carrier signal conforming to the TTE protocol specification, and on the other hand, it checks whether the basic amplitude and frequency of the signal meet the minimum communication requirements. When the monitoring module confirms that it has captured a continuous and stable valid signal, it determines that the physical link is about to start data transmission, and the physical link state switches from idle state to synchronization state. At the same time, the clock synchronization and data synchronization processes are triggered. The clock synchronization module starts frequency and phase calibration to ensure that the FPGA receiving clock is consistent with the physical layer chip's transmitting clock. The data synchronization module then begins to identify the frame synchronization signal of the TTE frame, laying the foundation for accurate subsequent data parsing.

[0052] In step S232, the synchronization state calibration switches to the normal operating state. In the synchronization state, the link status monitoring module and the physical layer chip work together to complete dual synchronization calibration. First, clock locking: a digital phase-locked loop circuit accurately tracks the clock signal transmitted through the physical link, eliminating clock jitter and phase offset, achieving strict synchronization between the transmitting and receiving clocks. Second, data frame synchronization: by identifying the synchronization identifier field in the TTE frame header, the starting position and byte boundaries of the frame data are determined, ensuring that the FPGA can parse the data within the frame in the correct order. When both the clock locking accuracy and the data frame synchronization success rate meet preset standards, such as clock phase deviation ≤ 1ns and frame synchronization recognition accuracy 100%, the physical link is determined to have stable transmission conditions. The physical link state switches from the synchronization state to the normal operating state, allowing the valid TTE frames after voting to be transmitted through the physical link.

[0053] In step S233, normal operation monitoring and fault warning are triggered. When the physical link is in normal operation, the status monitoring module starts real-time monitoring mode. This includes two aspects: first, continuous effective signal cycles, which are counted by a counter to determine the number of consecutive valid TTE frames transmitted in the physical link, indirectly reflecting the connectivity stability of the physical link; and second, signal quality parameters, including electrical characteristics such as signal amplitude, signal-to-noise ratio, and signal rise / fall slope, as well as the real-time bit error rate (BER) calculated based on the number of error bits during frame transmission. All monitoring parameters are compared in real-time with preset thresholds. If electrical parameters such as signal amplitude are within the threshold range and the BER is lower than the preset threshold, the link is determined to be in normal operation, maintaining normal operation and continuously transmitting data. If the real-time BER exceeds the preset threshold, such as due to link interference or physical layer chip aging causing a surge in error bits, the physical link is directly determined to be in a fault state, and a third fault event is immediately generated, including fault type: physical layer BER exceeding the limit, link identifier, current BER value, signal quality parameters, etc. Simultaneously, a hardware interrupt is triggered, and the physical link state switches from normal operation to warning state.

[0054] In step S234: Warning state monitoring and resynchronization are initiated. After the physical link enters the warning state, the status monitoring module does not interrupt data transmission but enters a high-frequency monitoring mode to continuously track the changing trends of bit error rate and signal quality. On the one hand, it records the fluctuation of bit error rate in real time to determine whether the fault is caused by transient interference; on the other hand, it recalibrates the signal amplification factor, filtering parameters, and other configurations of the physical layer chip, attempting to eliminate minor faults through parameter optimization. If the bit error rate still does not drop below the threshold after a preset monitoring period, and the fault state persists, the fault is determined to be a persistent anomaly, such as a loose physical link or signal attenuation. At this time, the link state switches from the warning state to the resynchronization state, and the link resynchronization process is initiated, that is, clock calibration, frame synchronization identification, and other operations are re-executed. At the same time, a resynchronization command is sent to the physical layer chip to collaboratively complete the comprehensive reset of the physical link parameters.

[0055] In step S235, the resynchronization result is determined and the fault state is switched. In the resynchronization state, the status monitoring module strictly monitors the execution effect of the resynchronization process. If the clock re-locks stably within the preset resynchronization timeout period, the data frame is successfully synchronized, and the bit error rate drops below the threshold, the resynchronization is deemed effective, and the link state returns from the resynchronization state to the normal working state, restoring stable data transmission. If the resynchronization is not completed within the timeout period, such as multiple attempts to clock calibration still failing to lock, frame synchronization recognition failing, or the bit error rate continuing to exceed the standard after resynchronization, a serious physical link fault is determined, such as link breakage or physical layer chip failure. The link state switches from the resynchronization state to the fault state. At this time, the third fault event will update the fault level to "serious fault" and transmit it synchronously to the intelligent recovery control unit, triggering subsequent fault link isolation and redundant link switching operations to prevent the fault link from affecting the overall data transmission.

[0056] like Figures 7 to 10 As shown, the present invention provides a preferred embodiment of data error correction, clock switching, fault channel / link isolation, and multi-level recovery.

[0057] refer to Figure 7 The data error correction includes the following steps: Step S311: Execute the BCH error correction encoder to perform real-time error correction on bit errors or frame tampering anomalies determined in the standardized integrity check; Step S312: After the error correction is completed, trigger the CRC32 check circuit to perform a secondary check on the repaired data. If the secondary check passes, the system will operate normally; Step S313: If the secondary check fails, upgrade the fault level and trigger the fault channel / link isolation operation.

[0058] In this embodiment, data error correction is a rapid recovery method for repairable faults such as bit errors and frame tampering anomalies identified in the standardized integrity verification process. Through a hardware-based BCH error correction engine and a secondary verification closed-loop design, it achieves accurate repair and reliability verification of data errors, ensuring that the repaired data meets transmission requirements.

[0059] In step S311, the BCH hardware-based real-time error correction is executed. When the intelligent recovery control unit receives the first fault event generated by the standardized integrity check, it immediately triggers the hardware-based BCH error correction encoder integrated within the FPGA to start the real-time error correction process. The BCH error correction encoder adopts a hardware logic architecture with configurable error correction capabilities. It can adaptively match the corresponding error correction strategy according to the check deviation information carried in the fault event. For single-bit errors, the erroneous bit is directly located and flipped for repair through single-cycle parallel operation. For multi-bit errors, multiple rounds of check and repair logic are executed based on the extended error correction polynomial to ensure that all correctable erroneous bits are accurately corrected.

[0060] The error correction process is entirely driven by hardware logic, requiring no software intervention, and can be executed in parallel with the data transmission process. Error correction latency is controlled at the nanosecond level, avoiding additional transmission delays introduced by error correction operations and ensuring the real-time requirements of the TTE network. Simultaneously, the BCH error correction encoder records error correction logs in real time during the error correction process, including the location of the erroneous bit, error type (single bit / multiple bits), and the timing of the repair operation, providing data support for subsequent secondary verification and fault tracing.

[0061] In step S312, after the BCH error correction encoder completes data repair, it immediately triggers the CRC32 check circuit through hardware signal to start the secondary check process. The secondary check adopts the same check standard as the standardized integrity check. The repaired data is re-input into the CRC32 check circuit in byte stream order. Based on the same IEEE802.3 standard, a polynomial is generated to calculate a new CRC check value in real time. Then, it is compared with the preset check code carried in the TTE frame header at the hardware level.

[0062] If the secondary verification result shows that the newly calculated CRC check value is completely consistent with the preset check code, it is determined that the data error has been successfully corrected, and the integrity of the corrected data meets the transmission requirements. At this time, the CRC32 verification circuit outputs a secondary verification pass signal. After receiving the signal, the intelligent recovery control unit controls the data transmission link to return to normal. The corrected valid TTE frame continues to be transmitted to the downstream links, returning to normal operation. The entire error correction-recovery process requires no manual intervention, achieving seamless fault repair.

[0063] In step S313, if the secondary verification result shows that the newly calculated CRC check value is still inconsistent with the preset check code, it is determined that there is an uncorrectable error in the data. At this time, the intelligent recovery control unit immediately executes the fault escalation mechanism, upgrades the original fault level to a serious uncorrectable error, and simultaneously triggers the fault channel / link isolation operation.

[0064] Isolation operations are executed precisely according to the fault-related objects. If the fault event identification error originates from a certain processing channel, a shielding signal is sent to the enable terminal of that processing channel to cut off its data output path, isolating the faulty channel from the transmission link. At the same time, the voting logic is adjusted to adapt to the remaining normal channels. If the fault event identification error originates from the physical transmission link, an isolation instruction is written to the switch control register via the AXI-Lite bus to cut off the power supply path of the corresponding physical layer chip, achieving physical isolation of the faulty link and triggering the switching of the backup redundant link to ensure the continuity of data transmission. Both fault escalation and isolation operations are executed rapidly through hardware logic to ensure that error propagation is blocked within microseconds, guaranteeing the overall stability of the system. The AXI-Lite bus is a lightweight and simplified version of the AXI (Advanced Extensible Interface) bus protocol family, designed specifically for low-speed, low-bandwidth control data transmission. It is the mainstream bus protocol in the FPGA / SoC (System-on-a-Chip) field for control operations such as register configuration and status reading within and between chips.

[0065] refer to Figure 8 The clock switching steps include: Step S321: When the main clock is detected to have no valid rising edge for a continuous period or the frequency offset exceeds the preset range, the clock switching process is immediately triggered; the local clock counter is frozen to maintain the continuity of time counting; Step S322: Subsequently, the backup clock is enabled, and the phase alignment between the backup clock and the global clock is completed through a digital delay phase-locked loop. After synchronously updating the clock sources of all time-related modules inside the FPGA, the operation of the local clock counter is restored to ensure that the global time synchronization state is not interrupted.

[0066] In this embodiment, to address the risk of time synchronization interruption caused by master clock failure or anomaly, a hardware-based fast switching mechanism based on a dual-clock architecture is used to monitor the clock status in real time, protect the counter from freezing, and calibrate and update the backup clock, ensuring that the global time synchronization status remains uninterrupted.

[0067] In step S321, an independent clock health monitoring module is built inside the FPGA. The clock health monitoring module continuously monitors the operating status of the master clock at a preset sampling frequency. First, it monitors the effective rising edge of the master clock by capturing the rising edge trigger event of the master clock signal in real time through an edge detection circuit. If no effective rising edge that meets the preset amplitude and time interval requirements is detected continuously, the module will detect the rising edge. Second, it monitors the frequency stability of the master clock by counting the actual operating frequency of the master clock in real time through a frequency counter and comparing it with the preset standard frequency. If the frequency offset exceeds the preset range, the master clock frequency is determined to be abnormal.

[0068] When any of the above-mentioned anomalies is detected, the clock health monitoring module immediately outputs a clock anomaly trigger signal. Upon receiving the signal, the intelligent recovery control unit immediately triggers the clock switching process. To avoid time counting gaps during clock switching, after the switching process starts, a local clock counter freeze operation is first performed: the current count value of the local clock counter is latched by hardware logic to keep the counter state unchanged, ensuring that subsequent backup clocks can continue counting based on this frozen value, maintaining the continuity and integrity of time data, and avoiding problems such as timestamp errors and scheduling table execution anomalies caused by clock switching.

[0069] In step S322, after the local clock counter freezes, the intelligent recovery control unit quickly switches the clock source via a hardware multiplexer, disabling the main clock signal output and simultaneously enabling a preset backup clock source. The backup clock and the main clock use independent crystal oscillators and driver circuits to ensure that they are not affected by a main clock failure. To ensure that the backup clock is consistent with the FPGA's internal global time reference, a phase alignment process based on a digital delay-locked loop is initiated. Using the FPGA's internal high-precision global reference clock as a reference, the phase detector of the digital delay-locked loop compares the phase difference between the backup clock and the global reference clock in real time. The phase offset of the backup clock is dynamically adjusted through a delay compensation circuit until the phase deviation between the backup clock and the global reference clock drops below a preset threshold, achieving precise phase alignment between the two.

[0070] After phase alignment is complete, the intelligent recovery control unit sends clock source update signals to all time-related modules within the FPGA, including the timestamp capture module, scheduler execution module, and fault detection timing module, synchronously switching the clock input of each module to the calibrated backup clock. Once all modules have completed the clock source switch and are operating stably, a local clock counter recovery operation is performed: based on the count value at the time of freezing, the count continues to increment using the backup clock as a reference, ensuring seamless time counting. The entire clock switching process is driven by hardware logic without software intervention. The switching latency is controlled at the microsecond level, and through operations such as counter freezing and phase alignment, the global time synchronization state is ensured to remain uninterrupted before and after the switch. Core clock-dependent functions such as TTE frame timestamp capture and scheduler execution are unaffected, ensuring the stable and reliable time triggering characteristics of the TTE network.

[0071] refer to Figure 9 The steps for isolating the faulty channel / link include: Step S331: Based on the fault event location, locate the corresponding fault channel or physical link and write an isolation command to the switch's control register via the axi-lite bus; Step S332: Cut off the power supply path of the physical layer chip corresponding to the fault channel / link to physically isolate the faulty object; Step S333: If the faulty object is a processing channel, automatically block the corresponding processing channel and synchronously adjust the output of valid data; Step S334: If the faulty object is a physical link, immediately switch to the backup redundant link and update the transmission path parameters of the corresponding data stream in the TTE network global scheduling table.

[0072] In this embodiment, fault channel / link isolation is a key recovery method for dealing with serious uncorrectable errors. It quickly isolates the faulty object from the transmission link while ensuring the continuity of normal data transmission and preventing the fault from spreading and causing overall system failure.

[0073] In step S331, after the intelligent recovery control unit receives various fault events, such as the first fault event, the second fault event, and the third fault event, it first parses the core identification information carried in the fault event, including the fault type, the fault associated object ID, the fault location, and other data. Based on this information, it accurately locates the corresponding fault processing channel or physical transmission link.

[0074] After location is established, the intelligent recovery control unit sends targeted isolation commands to the switch's control register via the FPGA's internal Axi-Lite bus. These isolation commands are encoded in a standardized format and include key parameters such as the fault object type identifier, fault object ID, and isolation execution timing, ensuring the switch can accurately identify the isolation target and execution requirements. The Axi-Lite bus features low transmission latency and high control precision, enabling real-time issuance and confirmation of isolation commands, laying the foundation for rapid subsequent isolation. Upon receiving the command, the switch parses the command content through its internal control logic, identifies the hardware control node corresponding to the fault object to be isolated, and awaits the execution of subsequent isolation operations.

[0075] In step S332, after the isolation instruction is parsed, a physical isolation operation is immediately triggered. For the physical layer chip corresponding to the faulty object, a control signal is output through the port control register of its MAC layer to cut off the power supply path of the physical layer chip. After the power supply path is cut off, the signal transmission and reception functions of the fault handling channel or physical link are completely disabled, and the faulty object can no longer participate in data transmission or processing. This achieves physical-level blocking of the fault and effectively avoids problems such as fault data propagation and signal interference from affecting the operation of other normal channels or links.

[0076] The physical isolation process employs hardware-level rapid switching control, requiring no software driver intervention. Isolation operation latency is controlled at the microsecond level, ensuring rapid blocking before the fault escalates and guaranteeing the overall stability of the system. Simultaneously, the switch sends an isolation completion confirmation signal to the intelligent recovery control unit, indicating that the isolation operation has been successfully executed and providing a triggering basis for subsequent adaptation and adjustments.

[0077] In step S333, if the faulty object is a processing channel identified by the type identifier in the fault event, after physical isolation is completed, the intelligent recovery control unit synchronously performs an adaptation adjustment operation. On the one hand, it continuously sends a shielding signal to the enable control terminal of the faulty processing channel to ensure that it is always in a disabled state and will not be reconnected to the transmission link due to accidental triggering. On the other hand, it dynamically adjusts the voting logic of the hardware voter. The original voting logic is based on the three-out-of-three rule of the three processing channels. After isolating the faulty channel, the voter automatically switches to the two-out-of-two voting rule based on the remaining two normal processing channels. That is, the value that is consistent with the output results of the two channels is taken as the valid data. If the outputs of the two channels are consistent, the data is directly output. If a temporary deviation occurs, the valid data is determined based on the historical transmission stability weight, so as to ensure that the stable output of valid data can still be maintained even when one channel is reduced.

[0078] Meanwhile, the operation status of the remaining two processing channels is monitored in real time, and their output consistency is continuously checked. If one of the channels is found to be faulty, the voting logic can be further adjusted or the redundant channel can be triggered to ensure the continuity and reliability of data processing.

[0079] In step S334, if the faulty object is a physical link, it is confirmed by the type identifier in the fault event. After the physical isolation of the faulty link is completed, the intelligent recovery control unit immediately triggers the backup redundant link switching process: the data transmission path is quickly switched from the faulty link to the preset backup redundant link through the hardware multiplexer. The backup redundant link and the original faulty link use independent physical media, physical layer chips and transmission paths to ensure that the problem of the faulty link will not affect the normal operation of the backup link.

[0080] After the switchover is complete, the intelligent recovery control unit synchronously updates the transmission path parameters of the corresponding data stream in the TTE network global scheduling table: replacing the identifier of the original faulty link with the identifier of the backup redundant link, and updating timing parameters such as the expected arrival time range and time window threshold of the data stream. This ensures that subsequent steps such as timestamp window checks can make accurate judgments based on the updated parameters. The parameter update operation is performed directly in the high-speed on-chip memory of the FPGA and takes effect immediately after the update, ensuring that the data stream transmission after the switchover meets the global scheduling requirements and avoiding secondary failures such as timing anomalies.

[0081] The entire fault channel / link isolation process is executed through a closed-loop hardware logic. From fault location, command issuance, physical isolation to adaptation and adjustment, there is no software intervention throughout the process, ensuring that fault blocking and service recovery are completed within microseconds, minimizing the impact of faults on TTE network data transmission.

[0082] refer to Figure 10 The multi-level recovery steps include: Step S341, building a fast recovery finite state machine, which continuously receives fault events under normal conditions; Step S342, when a fault event is detected, entering a fault detection state, and determining and distinguishing between correctable and uncorrectable errors based on the fault type and / or severity level; Step S343, if the determination result is a correctable error, performing data error correction; after error correction, entering a recovery verification state to complete validity verification, and returning to normal operation after passing validity verification; Step S344, if the determination result is an uncorrectable error, triggering fault channel / link isolation; after isolation, entering a system reconstruction state to perform system reconstruction operations, synchronously completing clock switching or link switching adaptation during reconstruction, and returning to normal operation after reconstruction verification.

[0083] In this embodiment, the multi-level recovery mechanism is a comprehensive recovery solution for complex faults. By building a fast recovery finite state machine, it dynamically executes differentiated recovery strategies based on fault type and severity level, realizing full-scenario fault recovery from simple error repair to complex system reconstruction, and ensuring that the TTE network can quickly resume normal operation under various fault conditions.

[0084] In step S341, a hardware-based fast recovery finite state machine is built inside the FPGA. This fast recovery finite state machine uses pure hardware logic to implement state transitions, eliminating software scheduling delays and providing microsecond-level response capabilities. The initial state of the fast recovery finite state machine is the normal state. In this state, the fast recovery finite state machine continuously receives various fault events generated from standardized integrity verification, timestamp window checks, and physical layer link status monitoring via a dedicated signal link within the FPGA. These events include first fault events, second fault events, and third fault events. Simultaneously, it collects real-time operational status feedback information from various functional modules, such as processing channels, verification circuits, and clock modules.

[0085] To ensure the complete reception and rapid parsing of fault events, the rapid recovery finite state machine incorporates an event cache and parsing unit. The event cache unit employs a first-in, first-out (FIFO) architecture to temporarily store multiple concurrently generated fault events, preventing event loss. The parsing unit analyzes core fields in fault events in real time, including fault type, fault severity level, fault-related object identifiers, and fault occurrence sequence, providing comprehensive data support for subsequent fault determination. Under normal conditions, the rapid recovery finite state machine simultaneously monitors the overall system operation status, ensuring that all modules work collaboratively and normally. Upon receiving a fault event or abnormal status feedback, it immediately initiates the fault response process.

[0086] In step S342, when the fast recovery finite state machine detects a fault event or abnormal state feedback, it immediately switches from the normal state to the fault detection state, entering the fault analysis and judgment stage. In this state, the fast recovery finite state machine performs a multi-dimensional comprehensive judgment on the fault based on the parsed fault event information and a preset fault judgment rule base: Fault type subdivision: Faults are precisely classified into specific types such as data errors (e.g., bit errors, frame tampering), timing errors (e.g., scheduling jitter, abnormal latency), link errors (e.g., link failure, excessive bit error rate), clock errors (e.g., abnormal master clock), and channel errors (e.g., processing channel failure); Severity level assessment: Based on the degree of impact of the fault on system operation, faults are divided into three levels: minor faults (which can be recovered by simple repair and do not affect core functions), moderate faults (which require switching redundant resources and temporarily affect local functions), and severe faults (which may cause data transmission interruption and require system reconstruction).

[0087] Based on the fault type and severity level, the fault is ultimately determined as either correctable or uncorrectable. Correctable faults mainly include single-bit errors, minor timing deviations, and transient link interference, which can be quickly repaired through hardware error correction and parameter calibration. Uncorrectable faults mainly include multi-bit errors (exceeding error correction capabilities), severe channel faults, link breaks, and complete master clock failure, which require isolating the faulty object and reconstructing the system architecture for recovery. The entire fault detection and determination process is completed through parallel hardware logic, with determination latency controlled at the nanosecond level, ensuring the immediacy of fault response.

[0088] In step S343, if the fast recovery finite state machine determines that the fault is a correctable error, the data error correction process is immediately triggered, and the fast recovery finite state machine switches from the fault detection state to the error correction state. The error correction process is executed using a hardware-based BCH error correction encoder. Based on the error type and location identified in the fault event, an adaptive error correction strategy is matched: for single-bit errors, the erroneous bit is directly located and flipped for repair through single-cycle parallel computation; for non-data errors such as minor timing deviations, repair is achieved by calibrating timestamp parameters and adjusting time window thresholds.

[0089] After the error correction operation is completed, the fast recovery finite state machine switches from the error correction state to the recovery verification state, initiating the validity verification process. The verification process employs a dual verification mechanism: first, a secondary data integrity verification, using a CRC32 check circuit to verify the repaired data and confirm the absence of residual errors; second, functional recovery verification, monitoring the operational status of the corresponding functional modules to confirm their restored normal working capabilities. If both verifications pass, the fault is considered successfully repaired, and the fast recovery finite state machine returns from the recovery verification state to the normal state, resuming normal system operation. If, during the verification process, errors are found to be incompletely repaired, the fast recovery finite state machine automatically escalates the fault level, reclassifying it as an uncorrectable error and proceeding to the subsequent fault isolation and reconstruction process.

[0090] In step S344, if the fast recovery finite state machine determines that the fault is an uncorrectable error, the fault channel / link isolation process is immediately triggered. The fast recovery finite state machine switches from the fault detection state to the isolation state. For the fault handling channel, its data output path is cut off by shielding the signal, and the voting logic is adjusted to adapt to the remaining normal channels. For the faulty physical link, the power supply of the corresponding physical layer chip is cut off, and the system quickly switches to the backup redundant link to achieve physical blocking of the faulty object and replacement of redundant resources.

[0091] After the isolation operation is completed, the finite state machine is quickly restored to switch from the isolated state to the system reconfiguration state, and the system reconfiguration operation is initiated. The reconfiguration process revolves around restoring the complete functionality of the system and ensuring the continuity of data transmission. First, hardware resources are reconfigured, and the internal processing resources, storage resources, and clock resources of the FPGA are reallocated to ensure that the remaining normal resources can meet the core functional requirements of the system. Second, parameter configuration is updated, and parameters such as transmission paths and time window thresholds in the global scheduling table, as well as the working configuration parameters of each module, are updated synchronously to adapt to the reconfigured hardware architecture. Third, synchronization mechanism adaptation is performed, and clock synchronization, data synchronization, and other mechanisms are recalibrated according to the reconfigured hardware environment. If the clock source or link is changed during the reconfiguration process, clock switching or link switching adaptation operations are performed synchronously to ensure global time synchronization and data transmission timing compliance.

[0092] After system reconstruction is completed, the rapid recovery finite state machine initiates the reconstruction verification process. By monitoring indicators such as data transmission continuity, the collaborative working status of each module, and fault recurrence, it confirms whether the system has returned to normal. If the verification passes, the rapid recovery finite state machine returns from the system reconstruction state to the normal state, and the system resumes stable operation. If the verification fails, the rapid recovery finite state machine continues to optimize the reconstruction plan or triggers a higher level of redundancy backup mechanism until the system returns to normal, maximizing the service continuity of the TTE network.

[0093] like Figure 11 As shown, the present invention provides a preferred embodiment of FPGA resource performance optimization management.

[0094] It also includes FPGA resource performance optimization management, including the following steps: Step S40, through the collaborative design of pipelined parallel processing, on-chip hierarchical memory architecture, clock gating and dynamic power consumption adjustment, to optimize FPGA resource utilization, data transmission latency and power consumption while ensuring microsecond-level fault detection and recovery performance.

[0095] Regarding step S41, the pipelined parallel processing includes breaking down the TTE frame preprocessing, integrity verification, data voting, and fault recovery process into multi-level continuous processing stages. Through pipelined task allocation and latency balancing of critical processing paths, each processing stage is executed sequentially in parallel. Regarding step S42, the hierarchical storage access includes constructing a three-level hierarchical storage unit, comprising a first-level storage module, a second-level storage module, and a third-level storage module. The first-level storage module stores the metadata of the currently processed TTE frame; the second-level storage module stores the TTE network global scheduling table and data flow status information; and the third-level storage module is used for large-capacity TTE frame access. The system includes: caching; prioritizing on-chip memory access over external memory interaction to shorten data access paths; regarding step S43, the dynamic clock control includes real-time monitoring of the operating status and performing clock shutdown operations on idle modules without task processing; regarding step S44, the adaptive power consumption adjustment includes real-time monitoring of task load and operating temperature, dynamically adjusting the operating voltage and frequency according to load changes; when a sudden high-load task is detected, switching to performance-priority mode and shutting down the clock supply to non-core processing modules; when the operating temperature reaches a preset temperature threshold, performing frequency reduction and shutting down some redundant processing mechanisms, enabling a heat dissipation adaptation strategy, and gradually restoring the original operating configuration after the temperature returns to the normal range.

[0096] In this embodiment, to achieve an optimized balance between resource utilization, data transmission latency, and power consumption while ensuring microsecond-level fault detection and recovery performance, an integrated resource performance optimization management system is implemented, which includes pipelined parallel processing, hierarchical storage access, dynamic clock control, and adaptive power consumption adjustment.

[0097] In step S41, the entire process logic of TTE frame from reception to fault recovery is broken down into five independent continuous processing stages: preprocessing, integrity verification, data voting, fault detection, and fault recovery. Each stage implements data buffering and transfer through hardware register groups, thus constructing an efficient pipelined parallel processing architecture.

[0098] In terms of task allocation, a pipelined task scheduling strategy is adopted. When the first frame of TTE data completes the preprocessing stage and enters the integrity verification stage, the second frame of TTE data simultaneously enters the preprocessing stage. Subsequent frames flow into each processing stage in sequence, realizing parallel processing of multiple frames of data and significantly improving data throughput. Simultaneously, to address the critical path latency differences in each processing stage, latency balancing is implemented through methods such as inserting balancing registers and optimizing the cascaded logic gate structure. For example, for the logically complex and latency-intensive integrity verification stage, parallel computation logic is used to shorten the processing time of a single frame; for the latency-efficient voting stage, register buffering is used to match the rhythm with other stages, ensuring that the entire pipeline is unblocked and wait-free, with each processing step executing efficiently and in parallel in sequence, avoiding a decrease in overall processing efficiency due to latency in a single step. This completely eliminates the efficiency bottleneck of traditional serial processing, compressing the entire processing latency of a single frame of TTE data to the microsecond level while ensuring the processing accuracy of each step, and significantly increasing the system's data processing capacity to meet the transmission requirements of high-bandwidth TTE networks.

[0099] In step S42, to address the issues of high latency and high resource consumption in external storage access, this invention constructs a three-level hierarchical storage unit, with all storage resources integrated on the FPGA chip. Through differentiated storage allocation and priority access strategies, data access efficiency is maximized.

[0100] The first-level storage module is constructed using a high-speed register file, primarily storing TTE frame metadata currently being processed at each pipeline stage, including frequently accessed data such as frame identifiers, processing status, and temporary verification results. The register file features nanosecond-level read / write latency, enabling real-time data access and meeting the stringent requirements of pipelined parallel processing for data access speed. The second-level storage module, built on on-chip BRAM, stores core configuration data such as the TTE network global scheduling table, status information of each data stream, and fault determination rule base. This module supports high-bandwidth parallel read / write, with data access latency controlled within 10ns. Furthermore, through data block storage and index optimization, it ensures rapid retrieval of scheduling table parameters and status information, providing efficient data support for timestamp window checks, fault determination, and other processes. Regarding the third-level storage module, a large-capacity cache is constructed using on-chip URAM, primarily for temporarily storing large amounts of data such as complete TTE frame data to be processed, processing logs, and fault event caches. URAM combines large capacity with high speed, preventing processing interruptions caused by data overflow. Furthermore, by replacing traditional external DDR storage interaction with on-chip memory access, the data access path is shortened from the external bus to the on-chip logical link, significantly reducing access latency and resource overhead.

[0101] The three-tiered storage unit achieves collaborative management through a hardware storage controller. It automatically allocates storage tiers and optimizes access paths based on data type and access frequency, ensuring the efficiency of data access and storage security for all types of data. At the same time, it reduces the system's dependence on external storage resources and improves overall stability.

[0102] In step S43, to reduce unnecessary power consumption, a dynamic clock control strategy is adopted. This involves real-time monitoring of the operating status of each functional module to achieve intelligent switching control of the clock signal. The FPGA integrates a module status monitoring unit, which collects the task load status of each functional module, such as processing channels, verification circuits, storage modules, and recovery control units, in real-time, on a clock cycle basis. This includes whether there are data processing tasks, whether the module is in a waiting state, and whether the current task has been completed. For modules with no processing tasks and that are idle for extended periods (such as an unused backup processing channel or an idle storage partition control module), the status monitoring unit outputs a clock shutdown signal through a clock gating circuit, cutting off the clock supply to the module and stopping unnecessary operations. Only the power supply to the core status register is maintained, thus avoiding redundant power consumption caused by meaningless clock flips.

[0103] When the module receives a new task instruction, the status monitoring unit immediately triggers a clock recovery signal. The clock gating circuit quickly restores the clock supply, and the module rapidly enters the working state under clock drive. The delay of the entire clock switching process is negligible and does not affect the real-time response performance of the system. This can reduce ineffective power consumption by more than 30% while ensuring the normal operation of core functions, achieving an optimized balance between performance and power consumption.

[0104] In step S44, to address power consumption requirements under different task loads and operating environments, an adaptive power management mechanism is employed. The Dynamic Power Management Unit (DPMU) monitors the system's operating status in real time, enabling intelligent adaptation of voltage, frequency, and redundancy mechanisms. The DPMU monitors the system's task load in real time and dynamically adjusts the FPGA's operating voltage and frequency based on load changes. Under low-load scenarios, it reduces the operating voltage and frequency to maintain basic system functions with minimal power consumption. Under normal load scenarios, it adopts a balanced voltage and frequency configuration, balancing performance and power consumption. When a sudden high-load task is detected, it automatically switches to a performance-priority mode, increasing the operating voltage and frequency while simultaneously shutting down the clock supply to non-core processing modules. This concentrates resources and power consumption on core processes such as data processing, fault detection, and recovery execution, ensuring the system maintains microsecond-level response speeds even under high loads.

[0105] Furthermore, the dynamic power management unit synchronously monitors the operating temperature of the FPGA chip, collecting real-time temperature data of the chip's core area via a built-in temperature sensor. When the temperature reaches a preset threshold, it is determined to be a high-temperature risk state, immediately executing a frequency reduction operation to decrease the chip's computing speed and reduce heat generation; simultaneously, some unnecessary redundant processing mechanisms are shut down to further reduce power consumption and heat generation, and a thermal adaptation strategy is activated. Once the temperature sensor detects that the chip temperature has dropped to the normal range, the dynamic power management unit gradually restores the original operating voltage, frequency, and redundancy mechanism configurations, ensuring that the system maximizes performance within a safe temperature range. This ensures real-time performance and reliability under high-load scenarios while avoiding power waste under low-load scenarios, effectively preventing chip damage due to high temperatures and extending the device's lifespan.

[0106] The above description is merely the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the claims of the present invention are covered by the present invention.

Claims

1. A hardware-level fault-tolerant method for TTE networks based on FPGA, characterized in that, Including the following steps: The received TTE frames are preprocessed in parallel through multiple processing channels and then a standardized bit stream is output. A voter performs a bit-by-bit voting on the standardized bit streams of multiple processing channels, using multiple values ​​as valid data, while identifying and blocking the corresponding processing channels with faults. Standardized integrity verification, timestamp window checking, and physical layer link status monitoring are performed on valid TTE frames after voting. When an anomaly is detected, a corresponding fault event is generated. Upon receiving the fault event, based on the fault type and / or severity level of the fault event, at least one of the following is performed: data error correction, clock switching, fault channel / link isolation, and multi-level recovery. The normal operation of the data transmission path is restored quickly through hardware-based execution logic.

2. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that: During the preprocessing process, each processing channel performs preliminary verification of the data integrity of the TTE frame, PTP timestamp alignment, and data formatting, and outputs a standardized bit stream. The FPGA is equipped with three independent processing channels. The voter performs real-time bit-by-bit comparison of the standardized bit streams output by the three processing channels. It adopts a two-out-of-three voting rule and uses the majority value of the output results of the three processing channels as the valid data of the corresponding bit. It continuously detects the consistency of the three processing channels, and determines the processing channel whose output results are inconsistent with multiple values ​​as a faulty channel. It sends a shielding signal to the enable terminal of the faulty channel to isolate the faulty channel from the data transmission link.

3. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that, The steps for performing standardized integrity verification on the valid TTE frames after voting include: After voting, the valid TTE frames are input into the CRC32 check circuit in byte stream order. The CRC32 check circuit calculates the CRC check value in real time based on the standard preset generator polynomial and performs a hardware-level comparison with the preset check code carried in the TTE frame header. If the CRC check value matches the preset check code, the data is deemed complete, and the data of the valid TTE frame is allowed to be transmitted downwards. If the CRC check value is inconsistent with the preset check code, it is determined to be a bit error or frame tampering abnormality, triggering an interrupt signal and generating the first fault event.

4. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that, The step of performing a timestamp window check on the valid TTE frames after voting includes: The PTP receive timestamp of the TTE frame after voting is captured in real time, and the timestamp is phase-aligned with the global clock through a digital delay phase-locked loop. The global scheduling table of the TTE network is pre-loaded, which includes the expected arrival time range and time window threshold of each frame. The expected arrival time parameter of the current frame is retrieved in real time to form a time window interval from the expected start time to the expected end time. The aligned PTP receiving timestamp is then compared with the time window interval in real time. If the PTP received timestamp falls within the time window interval, it is determined to be time compliant, and the time window threshold of the data stream to which the TTE frame belongs is updated; If the PTP received timestamp exceeds the upper limit of the time window interval or falls below the lower limit of the time window interval, it is determined to be a scheduling jitter, abnormal link delay, or frame loss risk. The time deviation value is recorded, an interrupt signal is triggered, and a second fault event is generated.

5. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that, A physical layer chip connected to the FPGA via a physical link is also provided. The step of monitoring the physical layer link status of the valid TTE frames after voting includes: The physical link is initially in an idle state. When a valid signal is detected, it switches to a synchronization state and initiates the clock and data synchronization process. After clock locking and data frame synchronization are completed in the synchronization state, it enters the normal working state; In normal operation, the period of continuous valid signals is counted, and it is determined whether parameters such as signal amplitude meet the preset threshold. If the bit error rate is detected to exceed the threshold, it is determined to be in a fault state, a third fault event is generated, and the system switches to the warning state. In the early warning state, continuously monitor the fault status. If the fault status persists, enter the resynchronization state and initiate link resynchronization. In the resynchronization state, if resynchronization is successful, it returns to the normal working state; if it fails to recover within a timeout period, it switches to the fault state.

6. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that: The data error correction includes the following steps: executing the BCH error correction encoder to perform real-time error correction on bit errors or frame tampering anomalies determined in the standardized integrity check; After the error correction is completed, the CRC32 verification circuit is triggered to perform a second verification on the repaired data. If the second verification passes, the system will operate normally. If the second verification fails, the fault level will be upgraded and fault channel / link isolation operation will be triggered. The clock switching steps include: when the main clock is detected to have no valid rising edge for a continuous period or the frequency offset exceeds the preset range, the clock switching process is immediately triggered; the local clock counter is frozen to maintain the continuity of time counting; then the backup clock is enabled, and the phase alignment between the backup clock and the global clock is completed through a digital delay phase-locked loop. After the clock sources of all time-related modules inside the FPGA are updated synchronously, the operation of the local clock counter is restored to ensure that the global time synchronization state is not interrupted.

7. The TTE network hardware-level fault-tolerant method according to claim 5, characterized in that: The steps for isolating the faulty channel / link include: Based on the fault event location, the corresponding fault channel or physical link is located, and isolation instructions are written to the switch's control register via the axi-lite bus. Cut off the power supply path of the physical layer chip corresponding to the faulty channel / link to physically isolate the faulty object; If the faulty object is a processing channel, the corresponding processing channel will be automatically blocked, and the output of valid data will be adjusted synchronously. If the faulty object is a physical link, the system will immediately switch to the backup redundant link and update the transmission path parameters of the corresponding data stream in the TTE network global scheduling table.

8. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that: The multi-level recovery steps include: A fast recovery finite state machine is constructed, which continuously receives fault events under normal conditions; When a fault event is detected, the system enters the fault detection state, and, based on the fault type and / or severity level, determines and classifies it into correctable and uncorrectable errors. If the judgment result is a correctable error, data error correction is performed; after the error correction is completed, the system enters the recovery verification state to complete the validity verification; after the validity verification is passed, the system runs normally. If the judgment result is an uncorrectable error, the fault channel / link isolation is triggered; after the isolation is completed, the system enters the system reconstruction state to perform system reconstruction operations. During the reconstruction process, clock switching or link switching adaptation is completed synchronously. After the reconstruction verification is successful, the system returns to normal operation.

9. The TTE network hardware-level fault-tolerant method according to claim 1, characterized in that: It also includes FPGA resource performance optimization management, including the following steps: through the collaborative design of pipelined parallel processing, on-chip hierarchical memory architecture, clock gating and dynamic power consumption adjustment, the FPGA resource utilization, data transmission latency and power consumption are optimized while ensuring microsecond-level fault detection and recovery performance.

10. The TTE network hardware-level fault-tolerant method according to claim 9, characterized in that: The pipelined parallel processing includes breaking down the TTE frame preprocessing, integrity verification, data voting, and fault recovery process into multi-level continuous processing stages. Through pipelined task allocation and delay balancing of critical processing paths, each processing stage is executed in parallel in sequence. The hierarchical storage access includes constructing a three-level hierarchical storage unit, which includes a first-level storage module, a second-level storage module, and a third-level storage module; the first-level storage module stores the metadata of the TTE frame currently being processed, the second-level storage module stores the TTE network global scheduling table and data stream status information, and the third-level storage module is used for large-capacity temporary buffering of TTE frames; Shorten the data access path by prioritizing on-chip memory access over external storage interaction; The dynamic clock control includes real-time monitoring of the working status and performing a clock shutdown operation on idle modules that are not processing tasks. The adaptive power consumption adjustment includes real-time monitoring of task load and operating temperature, and dynamic adjustment of operating voltage and frequency according to load changes; when a sudden high load task is detected, it switches to performance priority mode and shuts down the clock supply to non-core processing modules. When the operating temperature reaches the preset temperature threshold, the frequency is reduced and some redundant processing mechanisms are turned off. The heat dissipation adaptation strategy is enabled. After the temperature returns to the normal range, the original operating configuration is gradually restored.

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