Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure. The semiconductor structure comprises a first semiconductor tube core, a second semiconductor tube core, a sealing cover layer and an insulating packaging body, wherein the first semiconductor tube core and the second semiconductor tube core are stacked and jointed with each other; the sealing cover layer is used for sealing a joint interface of the first semiconductor tube core and the second semiconductor tube core, and the insulating packaging body is arranged above the second semiconductor tube core and covers the first semiconductor tube core and the sealing cover layer. The first semiconductor die includes a first portion and a second portion connected to the first portion, and the first portion is wider than the second portion. The capping layer contributes to reducing the risk of delamination and crack generation or propagation during the formation of the insulating encapsulant, thereby achieving a semiconductor structure with reduced defects, improved reliability, and improved yield.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure, and more particularly, to a semiconductor structure with a cap layer. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to, among other things, the "scaling" of various components such as transistors, diodes, resistors, capacitors, etc. Much of this scaling has come from continuous reductions in the minimum feature size, which has allowed more components to be integrated into a given area. Technological advances in integrated circuit (IC) design have produced several generations of ICs, each with more and smaller circuitry than the last. There is a continuing effort to develop new mechanisms for forming semiconductor structures with improved electrical performance. SUMMARY

[0003] Embodiments of the present application provide a semiconductor structure including a first semiconductor die and a second semiconductor die stacked and bonded to each other, a cap layer sealing a bonding interface of the first semiconductor die and the second semiconductor die, and an insulative encapsulation disposed over the second semiconductor die and covering the first semiconductor die and the cap layer, the first semiconductor die including a first portion and a second portion connected to the first portion, and the first portion being wider than the second portion.

[0004] Embodiments of the present application provide a semiconductor structure including a first semiconductor die, a second semiconductor die under the first semiconductor die and bonded to the first semiconductor die, a cap layer conformally lining the first semiconductor die and the second semiconductor die to seal a bonding interface of the first semiconductor die and the second semiconductor die, and an insulative encapsulation covering the first semiconductor die, the second semiconductor die, and the cap layer, the first semiconductor die including a first sidewall and a second sidewall laterally misaligned from the first sidewall, the cap layer separating the insulative encapsulation from the first semiconductor die and the second semiconductor die.

[0005] Based on the above, the semiconductor structure of embodiments of the present application includes a cap layer around a bonding interface of first and second semiconductor dies, and the cap layer can serve as a seal between the first and second semiconductor dies. The presence of the cap layer helps reduce the risk of delamination propagation during insulative encapsulation formation. Thus, a semiconductor structure with reduced defects, improved reliability, and improved yield can be realized.

[0006] So that the foregoing features and advantages of the embodiments of the present application can be understood in more detail, more embodiments will be described in detail with reference to the following drawings, where: BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1C schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0008] Figures 2A-2D schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0009] Figure 2E schematic top view of a semiconductor structure according to some embodiments.

[0010] Figure 3 schematic cross-sectional view of an integrated circuit package including a semiconductor structure according to some embodiments.

[0011] Figure 4A and Figure 4B schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0012] Figure 5A and Figure 5B schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0013] Figure 6A and Figure 6B schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0014] Figure 7A and Figure 7B schematic cross-sectional views showing intermediate steps during a process for forming a semiconductor structure according to some embodiments.

[0015] Figure 8 schematic cross-sectional view of a semiconductor structure according to some embodiments.

[0016] BRIEF DESCRIPTION OF DRAWINGS

[0017] 10, 10A, 10B, 10C, 10D: Semiconductor structure; 20: Packaging substrate; 30: IC package; 101, 101', 301, 401, 401': First layer; 102, 102': Second layer; 110, 210, 210', 210”: First semiconductor die; 110-1, 110-2: Die area; 110A: Functional area; 110F, 111a, 121a, 1200F: Front side; 110L: Drilling channel area; 110N, 210Y, 210Y', 1312, 2312, 3312: Second part; 110R: Ridge; 110S: Sealing ring area; 110T, 110T-1, 110T-2: Trench; 110W, 210X, 210X', 1311, 2311, 3311, 4311, 4311': First portion; 111, 111': First semiconductor substrate; 111G: Flange portion / first flange portion; 111L, 1131L: Lower surface; 111W, 111X, 111Y, 120W, 132W, 1131W, 1141W, 1311W, 2312W: Sidewall; 111b, 121b: Back side; 112: First device; 113: First interconnect structure; 114: First bonding structure; 115: Sealing ring; 120: Second semiconductor die; 121: Second semiconductor substrate; 123: Second interconnect structure; 124, 214: Second bonding structure; 12 5: Perforation / TSV; 125a: First end; 125b: Second end; 131, 231, 331, 431, 431': Capping layer; 131Y: Outer boundary; 131Z: Inner boundary; 131t, 132t, 1141t, 1142t, 1241t, 1242t: Top surface; 132: Insulating encapsulant; 141: Conductive pad; 142: Conductive terminal; 150: Redistribution structure; 151: Dielectric layer; 152: Conductive pattern; 202: Substrate; 204: Contact pad; 206: Underfill; 210-1, 210-2: Die area; 210GW, 210RW, L1: Lateral size; 210P, 210P': Peripheral area; 210R: Recess; 210R D: Depth; 210Y1, 3312a, 4311a, 4311a': First part; 210Y2, 3312b, 4311b: Second part; 210Z, 2313', 3313, 3313', 4313, 4313': Third part; 211G: Second flange portion; 1100, 1200, 2100: Semiconductor wafer; 1131, 1131': First dielectric layer; 1131U, 1131U', 1151U: Top surface; 1132: First metallization pattern; 1141: First bonding dielectric layer; 1142: First bonding connector; 1142D, 1242D: Additional bonding connectors; 1151: Additional sealing ring; 1231: Second dielectric layer;1232: Second metallization pattern; 1241: Second bonding dielectric layer; 1242: Second bonding connector; 3312c: Third part; 3312d: Vertical distance; D1: First direction; D2: Second direction; IF10, IF20: Bonding interface; NB1: Unbonded area; TH1: Thickness. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0019] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0020] The embodiments discussed herein aim to provide various semiconductor structures and methods of forming them. For example, a semiconductor structure is formed by the following steps: bonding a first semiconductor die to a second semiconductor die, forming a capping layer to seal the bonding interface between the first and second semiconductor dies, and forming an insulating encapsulation on the second semiconductor die to surround the first semiconductor die and the capping layer. Internal stress originates from the difference in thermal expansion between the first and second semiconductor dies and the insulating encapsulation. This difference in thermal expansion is due to the difference in the coefficient of thermal expansion (CTE) of the materials between the first and second semiconductor dies and the insulating encapsulation. Furthermore, a large CTE mismatch between the insulating encapsulation and the first and second semiconductor dies generates stress in the semiconductor structure, particularly at the bonding interface between the first and second semiconductor dies. During the formation of the insulating encapsulation, the bonding dielectric layer in the bonded structure may delamination or worsen. For example, delamination propagates from the non-functional (or peripheral) area of ​​the bonded structure toward the functional (or central) area of ​​the bonded structure, and this propagation can lead to device failure. By forming a capping layer to surround the bonding interface, the capping layer can serve as a seal between the first and second semiconductor dies. The presence of a capping layer helps reduce the risk of delamination propagation during the formation of the insulating encapsulation. Therefore, semiconductor structures with reduced defects can be achieved, improving reliability and yield.

[0021] Figures 1A-1C A schematic cross-sectional view is shown of intermediate steps during the process of forming a first semiconductor die according to some embodiments. It should be noted that... Figure 1A and 1B Provided for illustrative purposes only, and according to some embodiments, the first semiconductor die may utilize fewer or additional components.

[0022] refer to Figure 1A A semiconductor wafer 1100 comprising multiple die regions (e.g., 110-1, 110-2) is provided. The die regions (e.g., 110-1, 110-2) may be separated by dicing channels 110L, and subsequent monomerization processes are performed in the dicing channels 110L. For example, the die regions (e.g., 110-1, 110-2) are monomerized to form individual first semiconductor dies 110, wherein the respective first semiconductor dies 110 may be included in a first layer of the resulting semiconductor structure (see, for example, [reference needed]). Figure 2D and Figure 4BThe corresponding first semiconductor die 110 may be a logic device (e.g., a central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), a combination thereof (e.g., a system-on-a-chip (SoC) die), or the like.

[0023] In some embodiments, the corresponding first semiconductor die 110 includes a first semiconductor substrate 111, a first device 112 formed in / on the first semiconductor substrate 111, a first interconnect structure 113 formed over the first semiconductor substrate 111 and electrically coupled to the first device 112, and a first bonding structure 114 formed over the first interconnect structure 113 and electrically coupled to the first interconnect structure 113. The first semiconductor substrate 111 may be a doped or undoped silicon substrate or an active layer of a semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 111 may include other semiconductor materials (e.g., germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or combinations thereof. Other suitable substrates, such as multilayer substrates or gradient substrates, may be used.

[0024] The first semiconductor substrate 111 may include a front side 111a and a back side 111b opposite to the front side 111a. For example, a first device 112 is formed on the front side 111a of the first semiconductor substrate 111. The first device 112 may include active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, inductors, etc.), combinations thereof, or the like. Although a single first device 112 is schematically shown in the corresponding first semiconductor die 110, it should be noted that the number and type of the first devices 112 may be different from those shown.

[0025] Continue to refer to Figure 1A A first interconnect structure 113 may be formed over the front side 111a of the first semiconductor substrate 111 and electrically coupled to the first device 112 to form an integrated circuit. The first interconnect structure 113 may include one or more first dielectric layers 1131 and first metallization patterns 1132 embedded in the first dielectric layers 1131. The material of the first dielectric layer 1131 may include oxides (e.g., silicon oxide or aluminum oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), the like, or combinations thereof. The corresponding first metallization pattern 1132 may include conductive pads, wires, conductive vias, combinations thereof, and / or the like. The corresponding first metallization pattern 1132 may be formed from conductive materials such as copper, cobalt, aluminum, gold, combinations thereof, or the like. It should be noted that the first dielectric layer 1131 and the first metallization pattern 1132 may have different configurations than those shown.

[0026] In some embodiments, the first bonding structure 114 includes one or more first bonding dielectric layers 1141 and first bonding connectors 1142 embedded in the first bonding dielectric layers 1141. The first bonding dielectric layers 1141 may be formed of a material suitable for subsequent dielectric-to-dielectric bonding (e.g., silicon oxide, silicon oxynitride, and / or the like). The first bonding connectors 1142 may be formed of a conductive material such as copper, aluminum, or the like. The corresponding first bonding connectors 1142 may be conductive pads, conductive vias, combinations thereof, etc. In some embodiments, the first bonding connectors 1142 are electrically connected to a first metallization pattern 1132 of the first interconnect structure 113. It should be noted that the first bonding dielectric layers 1141 and the first bonding connectors 1142 may have different configurations than those shown. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), grinding, etching, or a combination thereof) is performed such that the top surfaces (1141t and 1142t) of the first bonding dielectric layer 1141 and the first bonding connector 1142 are substantially flush (or coplanar) within the range of process variations.

[0027] Continue to refer to Figure 1AThe corresponding first semiconductor die 110 includes a functional (or active) region 110A and a sealing ring region 110S surrounding the functional region 110A. For example, the sealing ring region 110S is located between the functional region 110A and the dicing region 110L, and the dicing region 110L is located between two adjacent die regions (e.g., 110-1, 110-2). In some embodiments, a first device 112, a first metallization pattern 1132, and a first bonding connector 1142 are located within the functional region 110A. In some embodiments, both the first bonding dielectric layer 1141 and the first dielectric layer 1131 extend across the functional region 110A, the sealing ring region 110S, and the dicing region 110L. The corresponding first semiconductor die 110 may (or may not) include conductive features within the dicing region 110L.

[0028] In some embodiments, one or more sealing rings 115 may be formed in the first dielectric layer 1131 and within the sealing ring region 110S. For example, the sealing ring 115 is disposed in the peripheral region of each first semiconductor die 110. In some embodiments, the corresponding sealing ring 115 is disposed in a circle surrounding the first metallization pattern 1132 of the functional region 110A. The sealing ring 115 may include conductive vias and conductive pads that are vertically stacked and connected together by conductive vias, wherein the conductive pads of the sealing ring 115 may be at the same level as the conductive pads of the first metallization pattern 1132, and the conductive vias of the sealing ring 115 may be at the same level as the conductive vias of the first metallization pattern 1132. The corresponding first semiconductor die 110 may (or may not) include any metallization pattern and / or conductive features outside the sealing ring 115. It should be noted that the sealing ring 115 may have a different configuration than that shown.

[0029] Still referencing Figure 1A The first bonding structure 114 may include an additional bonding connector 1142D embedded in the first bonding dielectric layer 1141 and formed above the sealing ring 115 within the sealing ring region 110S. The additional bonding connector 1142D may be formed at the same level as the first bonding connector 1142. In some embodiments, the additional bonding connector 1142D is electrically and spatially isolated from the sealing ring 115 at least through the first bonding dielectric layer 1141. In an alternative embodiment, the additional bonding connector 1142D is physically connected to the underlying sealing ring 115. In some embodiments, the additional bonding connector 1142D is a dummy connector and is electrically floating in the corresponding first semiconductor die 110. For example, the presence of the additional bonding connector 1142D helps increase pattern uniformity and metal density, thereby benefiting subsequent bonding processes. Alternatively, the additional bonding connector 1142D may be omitted, and no conductive feature may be formed directly above the sealing ring 115.

[0030] refer toFigure 1B And refer to Figure 1A Trench 110T may be selectively formed in semiconductor wafer 1100 and within dicing regions 110L between adjacent die regions (e.g., 110-1, 110-2). In some embodiments, trench 110T is formed by an etching process (e.g., dry etching, such as reactive ion etching or the like), plasma dicing, or the like. The corresponding trench 110T may extend through the first bonding dielectric layer 1141 and the first dielectric layer 1131. In some embodiments, the corresponding trench 110T further extends into the first semiconductor substrate 111. The corresponding trench 110T may not penetrate the first semiconductor substrate 111. For example, the corresponding trench 110T is defined by the sidewalls 1141W of the first bonding dielectric layer 1141, the sidewalls 1131W of the first dielectric layer 1131, the sidewalls 111W of the first semiconductor substrate 111, and the lower surface 111L of the first semiconductor substrate 111. For example, the lower surface 111L of the first semiconductor substrate 111 is between the front side 111a and the back side 111b.

[0031] In some embodiments, the corresponding trenches 110T are formed as a ring around the corresponding die regions (e.g., 110-1, 110-2). For example, die region 110-1 is surrounded by trench 110T-1, and die region 110-2 is surrounded by trench 110T-2. Trench 110T-1 and trench 110T-2 may not be interconnected. For example, trench 110T-1 and trench 110T-2 are spatially separated from each other by a ridge 110R within the dicing region 110L. The ridge 110R may include the remainder of the first bonding dielectric layer 1141, the first dielectric layer 1131, and the first semiconductor substrate 111, which remain in the dicing region 110L and between two adjacent trenches (110T-1 and 110T-2).

[0032] refer to Figure 1C And refer to Figure 1BA sawing process can be performed on the semiconductor wafer 1100 to separate die regions (e.g., 110-1, 110-2) from each other, thereby forming individual first semiconductor dies 110. The sawing process can be performed via trenches 110T in the kerf region 110L. In some embodiments, the sawing process is a mechanical process of sawing through the ridge 110R using saw blades placed in adjacent trenches (110T-1 and 110T-2). Other sawing processes may be used in other embodiments. In some embodiments, after the sawing process, a portion of the first semiconductor substrate 111 in the ridge 110R is retained, thus forming a first semiconductor substrate 111 with a ledge portion 111G. The lateral size (e.g., width) of the ledge portion 111G can vary and may depend on the width of the blade used to perform the sawing process. It should be noted that the width of the ledge portion 111G is not limited in this disclosure. The sidewalls 111X of the ledge portion 111G can be formed by the sawing process. Due to the differences in etching and sawing processes, the sidewalls / surfaces of different regions of the corresponding first semiconductor die 110 may have different roughnesses. For example, sidewalls (111W, 1131W, and 1141W) formed by etching (or plasma cutting) are smoother than sidewalls 111X formed by sawing. In some embodiments, the surface roughness of sidewalls (111W, 1131W, and 1141W) is less than the surface roughness of sidewall 111X.

[0033] like Figure 1C As shown, the corresponding first semiconductor die 110 may include a first portion 110W and a second portion 110N connected to the first portion 110W, wherein the first portion 110W is a part of the first semiconductor substrate 111, and the second portion 110N includes another part of the first semiconductor substrate 111 and structures above said other part of the first semiconductor substrate 111. The first portion 110W may laterally protrude from the second portion 110N. For example, the sidewalls (i.e., 111X) of the first portion 110W are laterally misaligned with the sidewalls (including 111W, 1131W, and 1141W) of the second portion 110N. The first portion 110W may be wider than the second portion 110N. For example, the difference in lateral size between the first portion 110W and the second portion 110N lies in the lateral size of the flange portion 111G. In some embodiments, the presence of the flange portion 111G facilitates the formation of the insulating encapsulation (see...). Figure 2C Avoid stress concentration on the periphery of the joint interface.

[0034] According to some embodiments, Figures 2A-2D A schematic cross-sectional view of an intermediate step during the process of forming a semiconductor structure is shown, and Figure 2E A schematic top view of the semiconductor structure is shown. Figure 1CThe first semiconductor die 110 described herein may be included in the first layer 101 of the semiconductor structure 10 (see [reference]). Figure 2D Furthermore, as will be discussed in more detail below, the first semiconductor die 110 can be electrically connected to another layer to form a semiconductor structure 10. Similar reference numerals indicate similar features having similar structures and compositions.

[0035] First refer to Figure 2A A semiconductor wafer 1200 may be provided. The semiconductor wafer 1200 may include a second semiconductor substrate 121, a second interconnect structure 123 formed over the second semiconductor substrate 121, a second bonding structure 124 formed over the second interconnect structure 123, and a through-hole 125 in the second semiconductor substrate 121 and extending into the second interconnect structure 123. The second semiconductor substrate 121 may be a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The material of the second semiconductor substrate 121 may be selected from materials used to form... Figure 1A The same set of candidate materials as the first semiconductor substrate 111 discussed herein. The second semiconductor substrate 121 may be doped or undoped. In some embodiments, the semiconductor wafer 1200 does not contain active / passive devices, and the second semiconductor substrate 121 does not include devices formed on the front side 121a of the second semiconductor substrate 121. In some embodiments, active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.) are formed on the front side 121a of the second semiconductor substrate 121.

[0036] The second interconnect structure 123 may be formed above the front side 121a of the second semiconductor substrate 121. The second interconnect structure 123 may include one or more second dielectric layers 1231 and a second metallization pattern 1232 embedded in the second dielectric layer 1231. The second dielectric layer 1231 and the second metallization pattern 1232 may be respectively similar to Figure 1A The first dielectric layer 1131 and the first metallization pattern 1132, as described above, will not be repeated here. The second bonding structure 124 may be formed over and electrically connected to the second interconnect structure 123. For example, the second bonding structure 124 includes one or more second bonding dielectric layers 1241 and second bonding connectors 1242 embedded in the second bonding dielectric layers 1241. The second bonding connectors 1242 may be electrically connected to the second metallization pattern 1232. The second bonding dielectric layer 1241 and the second bonding connectors 1242 may be similar to... Figure 1AThe first bonding dielectric layer 1141 and the first bonding connector 1142 are described herein and will not be repeated here. In some embodiments, a planarization process (e.g., CMP process, polishing process, etching process, a combination thereof, or the like) is performed such that the top surfaces (1241t and 1242t) of the second bonding dielectric layer 1241 and the second bonding connector 1242 are substantially flush (or coplanar) within the range of process variations.

[0037] Continue to refer to Figure 2A The second bonding structure 124 may include an additional bonding connector 1242D embedded in the second bonding dielectric layer 1241. The additional bonding connector 1242D may be formed at the same level as the second bonding connector 1242. In some embodiments, the additional bonding connector 1242D is a dummy connector and electrically isolated from the second bonding connector 1242. The additional bonding connector 1242D may be electrically floated in the semiconductor wafer 1200. In some embodiments, the additional bonding connector 1242D is subsequently bonded to an additional bonding connector 1142D of the first semiconductor die 110. The via 125 may be formed in the second semiconductor substrate 121 by depositing one or more diffusion barrier layers or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., tungsten, titanium, aluminum, copper, any combination thereof, and / or the like) into trenches within the second semiconductor substrate 121. For example, the corresponding through-hole 125 includes a first end 125a that is physically and electrically connected to one of the second metallization patterns 1232 and a second end 125b relative to the first end 125a, wherein the second end 125b may be buried in the second semiconductor substrate 121 at this stage.

[0038] Still referencing Figure 2A And refer to Figure 1CThe first semiconductor die 110 can be bonded to the semiconductor wafer 1200. It should be noted that although a single first semiconductor die 110 is shown, any number of first semiconductor dies 110 can be bonded to the semiconductor wafer 1200. In some embodiments, the first semiconductor die 110 and the semiconductor wafer 1200 are directly bonded face-to-face via dielectric-to-dielectric bonding and metal-to-metal bonding, such that the front side 110F of the first semiconductor die 110 is bonded to the front side 1200F of the semiconductor wafer 1200. For example, the first bonding dielectric layer 1141 is fused to the second bonding dielectric layer 1241 via dielectric-to-dielectric bonding, and a dielectric-to-dielectric (e.g., oxide-to-oxide) bond may be formed between them. The first bonding connector 1142 is bonded to the second bonding connector 1242 via metal-to-metal bonding, and a metal-to-metal (e.g., copper-to-copper) bond may be formed between them. The bonding interface IF10 may be solder-free. In some embodiments, a dielectric-to-metal (e.g., oxide-to-copper, not shown separately) bond may be formed at the bonding interface IF10 of the first semiconductor die 110 and the semiconductor wafer 1200. In some embodiments, the bonding interface IF10 is substantially flat and planar.

[0039] In some embodiments, the bonding of the first semiconductor die 110 and the semiconductor wafer 1200 includes a pre-bonding process and an annealing process. During the pre-bonding process, a force may be applied to press the first semiconductor die 110 toward the semiconductor wafer 1200. The bonding strength of the first and second bonding dielectric layers (1141 and 1241) may be improved in the annealing process, wherein the first and second bonding dielectric layers (1141 and 1241) are annealed at a high temperature. In some embodiments, after the bonding process, the first and second bonding connectors (1142 and 1242) are directly interconnected in a one-to-one correspondence. In some embodiments, additional bonding connectors (1142D and 1242D) may be directly interconnected in a one-to-one correspondence.

[0040] It should be understood that an issue affecting the electrical reliability of the bonded structure is the adhesion between the first semiconductor die 110 and the semiconductor wafer 1200. Poor adhesion can lead to delamination. In some cases, during the bonding process, the first and second bonding connections may expand at the annealing temperature and exert stress on the surrounding bonding dielectric layer, resulting in delamination. For example, an unbonded region NB1 exists in the peripheral region of the bonding interface IF10 (e.g., corresponding to the sealing ring region 110S). During subsequent processing steps (e.g.) Figure 2CThe formation of the insulating encapsulation described herein, and the large CTE mismatch between the insulating encapsulation and the first / second semiconductor die, can generate stress in the resulting structure, particularly at the interface between the insulating encapsulation and the first / second semiconductor die. Under the influence of thermal mismatch stress, the unbonded area NB1 may expand and cracks (if present) may extend toward the functional region 110A. This may cause the first semiconductor die and the semiconductor wafer to separate and result in the resulting structure malfunctioning or failing. Therefore, in the fabrication of semiconductor structures, it is important to prevent delamination of the bonding interface and to prevent any cracks from extending to the functional region 110A. As described in more detail below, to mitigate such delamination, cracking, and / or peeling, some embodiments described herein provide a capping layer that seals the periphery of the bonding interface IF10.

[0041] refer to Figure 2B And refer to Figure 2A Capping layer 131 may be formed on the first semiconductor die 110 and the semiconductor wafer 1200 to seal the bonding interface IF10. Capping layer 131 may be a single layer or may comprise multiple sublayers formed of different dielectric materials. For example, the material of capping layer 131 includes any suitable dielectric material, such as oxides (e.g., silicon oxide or the like), nitrides (e.g., silicon nitride or the like), combinations thereof, etc. In some embodiments, the Young's modulus of capping layer 131 is lower than that of the subsequently formed insulating encapsulation (in... Figure 2C (Illustrated as "132"). The capping layer 131 may be conformally formed on the first semiconductor die 110 and the semiconductor wafer 1200 by chemical vapor deposition (CVD). Other suitable deposition methods (e.g., atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or similar) may be used to form the capping layer 131. The capping layer 131 may have a thickness TH1 ranging from about 1 μm to about 30 μm. However, any suitable materials, processes, and thicknesses may be used.

[0042] In some embodiments, the capping layer 131 surrounds the bonding interface IF10 and partially covers the first semiconductor die 110 and the semiconductor wafer 1200. For example, the capping layer 131 includes a first portion 1311 and a second portion 1312 connected to the first portion 1311, wherein the first portion 1311 extends in a first direction D1 and the second portion 1312 extends in a second direction D2. The first direction D1 may be substantially perpendicular to the second direction D2. For example, the first direction D1 is the stacking direction of the first semiconductor die 110 and the semiconductor wafer 1200. The first portion 1311, which partially lining the sidewalls of the first semiconductor die 110, can be considered a vertical portion of the capping layer 131, while the second portion 1312, which partially covers the top surface 1241t of the second bonding dielectric layer 1241, can be considered a horizontal portion of the capping layer 131. In some embodiments, a first portion 1311 extends along and is physically connected to the sidewalls 1141W and 1131W of the first bonding dielectric layer 1141 and the first dielectric layer 1131. In some embodiments, the first portion 1311 does not extend upward to cover the sidewall 111W of the first semiconductor substrate 111. In alternative embodiments, the first portion 1311 extends upward to partially (or completely) cover the sidewall 111W of the first semiconductor substrate 111. In some embodiments, a second portion 1312 extends from the sidewall of the first semiconductor die 110 and has a lateral size L1 measured in a second direction D2. For example, the lateral size L1 is greater than (or substantially equal to) 10 μm. Other lateral sizes L1 may also be present.

[0043] The capping layer 131, which lining the sidewalls (1131W and 1141W) of the first semiconductor die 110 and covering the top surface 1241t of the semiconductor wafer 1200, can serve as a dielectric seal for the sealing interface IF10. During the formation of the insulating encapsulation (see...), Figure 2C The capping layer 131 prevents stress from being directly applied to the periphery of the joint interface IF10, thereby enhancing the reliability of the jointed structure. Even in unjoined areas (e.g.) Figure 2A If the NB1 marked in the middle and / or cracks exist in the joined structure, the capping layer 131 of the sealing joint interface IF10 can also help prevent delamination / cracks from occurring, prevent delamination / cracks from becoming more severe and / or prevent delamination / cracks from extending into the functional area 110A.

[0044] refer to Figure 2C And refer to Figure 2BAn insulating encapsulation 132 may be formed on the semiconductor wafer 1200 to cover the first semiconductor die 110 and the capping layer 131. In some embodiments, the insulating encapsulation 132 is formed from a molding material or compound and may be formed by compression molding, transfer molding, or the like. The molding material includes a polymeric material and optionally includes a filler (not shown separately), wherein the filler may be silica particles or the like, and the polymeric material may be an epoxy resin or the like. The filler mixed in the polymeric material may provide mechanical strength and heat dissipation for the insulating encapsulation 132. For example, an insulating material is formed over the top surface 1241t of the second bonding dielectric layer 1241 of the semiconductor wafer 1200, and the first semiconductor die 110 and the capping layer 131 may be buried or covered by the insulating material. The insulating material may then be cured to form the insulating encapsulation 132. Selectively, a planarization process (e.g., CMP, polishing, etching, a combination thereof, or the like) is performed on the insulating material to planarize the top surface 132t of the insulating material and the first semiconductor die 110. The planarization process may (or may not) remove the back side 111b of the first semiconductor substrate 111. In some embodiments, the back side 111b of the first semiconductor die 110 is exposed by planarization of the insulating encapsulation 132, such that the surfaces (e.g., 111b and 132t) of the first semiconductor die 110 and the insulating encapsulation 132 are substantially flush (or coplanar) within a range of process variations.

[0045] In some embodiments, the insulating encapsulation 132 extends along the outer surface of the first semiconductor die 110 not covered by the capping layer 131. For example, the sidewall 111X of the flange portion 111G, the lower surface 111L of the first semiconductor substrate 111, and the sidewall 111W of the first semiconductor substrate 111 are in physical and direct contact with the insulating encapsulation 132. The capping layer 131 can laterally separate the insulating encapsulation 132 from the first interconnect structure 113 and the first bonding structure 114. The top surface 1241t of the second bonding dielectric layer 1241 of the semiconductor wafer 1200 may include a first portion bonded to the first semiconductor die 110, a second portion surrounding the first portion and covered by a second portion 1312 of the capping layer 131, and a third portion surrounding the second portion and covered by the insulating encapsulation 132. The capping layer 131 can vertically separate the insulating encapsulation 132 from the top surface 1241t of the second portion. As previously described, the capping layer 131 can seal between the first semiconductor die 110 and the semiconductor wafer 1200. In this way, thermal mismatch stress does not directly affect the bonding interface IF10 during the formation of the insulating encapsulation 132. The presence of the capping layer 131 helps prevent delamination from occurring (or becoming more severe) and prevents cracks (if present) from extending into the functional region 110A, thereby improving the reliability of the resulting semiconductor structure.

[0046] Still referencingFigure 2C Thinning processes (e.g., polishing, CMP, etching, combinations thereof, or similar) can be performed on the back side of the semiconductor wafer 1200. For example, the back side 121b of the second semiconductor substrate 121 is thinned until at least a portion of the second end 125b of the via 125 is exposed in an accessible manner. In some embodiments, the thinning process is performed after the formation of the insulating encapsulation 132. Since the via 125 penetrates the second semiconductor substrate 121, the via 125 can be considered a through-substrate via (TSV) 125.

[0047] refer to Figure 2D And refer to Figure 2C Multiple conductive terminals 142 may be formed above the back side 121b of the second semiconductor substrate 121 and electrically connected to the TSV 125. The conductive terminals 142 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. The conductive terminals 142 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive terminals 142 are formed by forming solder and performing a reflow process on the solder to form the desired bump shape. In some embodiments, a corresponding conductive terminal 142 includes a pillar portion (e.g., a copper pillar) and a cap portion formed on the pillar portion, wherein the pillar portion has substantially vertical sidewalls and the cap portion has a bump profile.

[0048] In some embodiments, a conductive pad 141 is formed over the second end 125b of the TSV 125 and the back side 121b of the second semiconductor substrate 121 before the conductive terminal 142 is formed. The conductive terminal 142 may rest on the conductive pad 141 and be electrically connected to the TSV 125 through the conductive pad 141. In some embodiments, the conductive pad 141 is an under bump metallization (UBM) pad. In an alternative embodiment, a redistribution structure (e.g., Figure 4B The 150 marked in the diagram is formed above the back side 121b of the second semiconductor substrate 121, and then a conductive terminal 142 is formed on the redistribution structure such that the conductive terminal 142 is electrically connected to the TSV 125 through the redistribution structure.

[0049] Still referencingFigure 2D And refer to Figure 2C The monomerization process is selectively performed by cutting along scribe lines (not shown) to form individual semiconductor structures 10. For example, the semiconductor structure 10 includes a first layer 101 stacked on a second layer 102, wherein the first layer 101 includes a first semiconductor die 110, a capping layer 131, and an insulating encapsulation 132, and the second layer 102 includes a second semiconductor die 120 formed by monomerizing a semiconductor wafer 1200. After the monomerization process, the sidewalls 132W of the insulating encapsulation 132 may be substantially aligned (or flush) with the sidewalls 120W of the second semiconductor die 120.

[0050] refer to Figure 2E And refer to Figure 2D , Figure 2E The top view shows the boundary relationship between the insulating encapsulation 132, the capping layer 131, the first semiconductor die 110, and the second semiconductor die 120. Since the capping layer 131 is embedded within the insulating encapsulation 132, therefore... Figure 2E The capping layer 131 is shown as a dashed line. In some embodiments, the boundary of the second semiconductor die 120 is substantially aligned with the outer boundary of the insulating encapsulation 132, wherein the sidewall 132W of the insulating encapsulation 132 is substantially aligned with the sidewall 120W of the second semiconductor die 120. In some embodiments, the outer boundary 131Y of the capping layer 131 lies within the outer boundary of the insulating encapsulation 132 defined by the sidewall 132W. In a top view, the capping layer 131 may be a closed loop (or a continuous loop) surrounding the boundary of the first semiconductor die 110, wherein the boundary of the first semiconductor die 110 includes a first boundary defined by the sidewall 111X and a second boundary defined by the sidewall 111W (or 1131W, 1141W). In some embodiments, the inner boundary 131Z of the capping layer 131 is adjacent to the second boundary of the first semiconductor die 110 defined by the sidewalls (1131W and 1141W).

[0051] The capping layer 131 may have a lateral size L1. Depending on the relationship between the lateral size of the capping layer 131 and the lateral size of the flange portion 111G of the first semiconductor die 110, a first boundary of the first semiconductor die 110 defined by the sidewall 111X may be disposed between the inner boundary 131Z and the outer boundary 131Y of the capping layer 131, such as... Figure 2E As shown. In an alternative embodiment, the outer boundary 131Y of the capping layer 131 is substantially aligned with the first boundary of the first semiconductor die 110 defined by the sidewall 111X. In other embodiments, the outer boundary 131Y of the capping layer 131 lies between the first boundary of the first semiconductor die 110 defined by the sidewall 111X and the second boundary of the first semiconductor die 110 defined by the sidewalls (1131W and 1141W).

[0052] Figure 3 A schematic cross-sectional view of an integrated circuit (IC) package including a semiconductor structure 10 according to some embodiments is shown. Similar reference numerals indicate similar features having similar structures and compositions.

[0053] refer to Figure 3 And refer to Figure 2D Conductive terminals 142 can be used to mount the semiconductor structure 10 onto the packaging substrate 20 to form an IC package 30. The packaging substrate 20 may include a substrate 202, which may be made of semiconductor materials such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may be used. The substrate 202 may be an SOI substrate. Alternatively, the substrate 202 may include, for example, an insulating core of glass fiber reinforced resin (e.g., FR4), BT resin (not shown separately), or include printed circuit board (PCB) material or film. The substrate 202 may use build-up films (e.g., Ajinomoto build-up film) or other laminated materials not shown separately. The substrate 202 may include active and / or passive devices (not shown) to meet the functional requirements of the system design.

[0054] The packaging substrate 20 may include contact pads 204 formed on / in the substrate 202. Conductive terminals 142 can be reflowed to attach conductive pads 141 to the contact pads 204. After coupling the conductive terminals 142 to the contact pads 204, the semiconductor structure 10 may be electrically coupled to the packaging substrate 20. In some embodiments, the IC package 30 includes an underfill 206 formed between the semiconductor structure 10 and the packaging substrate 20, wherein the underfill 206 may surround the conductive terminals 142 and the conductive pads 141 for protection. The underfill 206 may be formed by a capillary process after attaching the semiconductor structure 10 or by a suitable deposition method before attaching the semiconductor structure 10. The underfill 206 may be a continuous material extending from the packaging substrate 20. In some embodiments, the underfill 206 extends upward to physically contact the sidewalls 120 of the second semiconductor die 120. According to some embodiments, the underfill 206 may further physically contact the sidewall 132W of the insulating encapsulation 132. Due to surface tension and capillary processes, the outer surface of the underfill 206 may be inclined or curved. Unlike the underfill 206, the outer surface of the capping layer 131 may be substantially vertical or substantially parallel to the sidewalls / surfaces of the first / second semiconductor die (110 / 120). The above examples are provided for illustrative purposes only, and in other embodiments, the IC package 30 may include fewer or additional components.

[0055] Figure 4A and Figure 4B Schematic cross-sectional views are shown of intermediate steps during a process for forming a semiconductor structure according to some embodiments. Unless otherwise stated, the materials and formation methods of the components in these embodiments are similar to those in the original document. Figures 2A-2D The similar components in the illustrated embodiments are substantially the same, and these components are indicated by similar reference numerals. Regarding Figures 4A-4B Details of the forming process and materials of the components shown can be found in the discussion of the previous embodiments.

[0056] refer to Figure 4A And refer to Figure 2B In addition to the capping layer 231, Figure 4A The structure shown is Figure 2BThe structure shown is similar. In the illustrated embodiment, a capping layer 231 is formed on the semiconductor wafer 1200 and the first semiconductor die 110. The capping layer 231 may be substantially conformally oriented to the shapes of the semiconductor wafer 1200 and the first semiconductor die 110. The term "substantially conformally oriented" as used herein means that the outer surface of the capping layer 231 is substantially parallel to the sidewalls / surfaces of the semiconductor wafer 1200 and the first semiconductor die 110. The capping layer 231 may be a single layer or may comprise multiple sublayers formed of different dielectric materials. The material and formation method of the capping layer 231 may be similar to... Figure 2B The material and formation method of the capping layer 131 described herein are similar. In some embodiments, the capping layer 231 includes a first portion 2311 lining a second portion 110N of the first semiconductor die 110, a second portion 2312 covering a second bonding dielectric layer 1241 on the semiconductor wafer 1200, and a third portion 2313' lining a first portion 110W of the first semiconductor die 110.

[0057] In some embodiments, a first portion 2311 of the capping layer 231 extends along a first direction D1 to physically contact the sidewalls (111W, 1131W, and 1141W) of the first semiconductor substrate 111, the first dielectric layer 1131, and the first bonding dielectric layer 1141. A second portion 2312 of the capping layer 231 may extend along a second direction D2 to completely (or partially) cover the portion of the top surface 1241t of the second bonding dielectric layer 1241 that is not bonded to the first semiconductor die 110. A third portion 2313' of the capping layer 231 may physically contact the lower surface 111L and the sidewall 111X of the first semiconductor substrate 111. The third portion 2313' may (or may not) cover the back side 111b of the first semiconductor substrate 111.

[0058] refer to Figure 4B And refer to Figure 4A and Figure 2C After the capping layer 231 is formed, an insulating encapsulation 132 can be formed on the semiconductor wafer 1200. The material and formation method of the insulating encapsulation 132 can be compared with those of the semiconductor wafer 1200. Figure 2CThe materials and formation methods of the described insulating encapsulant 132 are similar. In some embodiments, a planarization process (e.g., CMP, polishing, etching, combinations thereof, or the like) is performed. During the planarization process, a portion of the third portion 2313' overlying the first semiconductor die 110 may be removed to expose the back side 111b of the first semiconductor substrate 111. For example, after the planarization process, the surfaces (e.g., 111b and 132t) of the first semiconductor die 110 and the insulating encapsulant 132 are substantially flush (or coplanar) within a process variation range. In some embodiments, during the planarization process, the top surface 131t of the capping layer 131 is planarized, and the top surface 131t of the capping layer 131 is substantially flush (or coplanar) with the surfaces (e.g., 111b and 132t) of the first semiconductor die 110 and the insulating encapsulant 132 within a process variation range.

[0059] Continue to refer to Figure 4B , Figure 4A and Figures 2C-2D A thinning process can be performed on the back side 121b of the second semiconductor substrate 121 until at least a portion of the TSV 125 is exposed in a tangible manner. The thinning process can be similar to... Figure 2C The described process. In some embodiments, the redistribution structure 150 is formed on the back side 121b of the second semiconductor substrate 121. For example, the redistribution structure 150 includes one or more dielectric layers 151 and conductive patterns 152 formed in the dielectric layers 151 and electrically connected to the TSV 125. The dielectric layers 151 may be formed of any suitable dielectric material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), combinations thereof, or the like. The conductive patterns 152 may include conductive pads, conductive vias, wires, combinations thereof, or the like, and may be formed of any suitable conductive material (e.g., copper, cobalt, aluminum, gold, combinations thereof, or the like). In some embodiments, the conductive patterns 152 include UBM pads, and conductive terminals 142 may be formed on the UBM pads. In alternative embodiments, the redistribution structure 150 is replaced with Figure 2D The conductive pad 141 described herein.

[0060] Still referencing Figure 4B And refer to Figure 2D and Figure 3 The monomerization process is selectively performed by cutting along scribe lines (not shown) to form individual semiconductor structures 10A. Conductive terminals 142 are used to selectively mount the semiconductor structures 10A onto a packaging substrate 20 to form an IC package, such as... Figure 3As shown. For example, semiconductor structure 10A includes a first layer 101' stacked on a second layer 102', wherein the first layer 101' includes a first semiconductor die 110, a capping layer 231, and an insulating encapsulator 132, and the second layer 102' includes a second semiconductor die 120 formed by monomerizing semiconductor wafer 1200. The monomerization process can be compared with... Figure 2D The process described in the previous section is similar, so it will not be repeated here. After the monomerization process, the sidewall 2312W of the second portion 2312 of the capping layer 231 is substantially aligned (or coplanar) with the sidewall 132W of the insulating encapsulant 132 and the sidewall 120W of the second semiconductor die 120.

[0061] In the illustrated embodiment, the first layer 101' of the semiconductor structure 10A includes a capping layer 231 that spatially separates the insulating encapsulation 132 from the first semiconductor die 110 and vertically separates the insulating encapsulation 132 from the second semiconductor die 120. The capping layer 231 serves as a dielectric seal isolating the insulating encapsulation 132 from the first and second semiconductor dies (110 and 120). The presence of the capping layer 231 helps reduce the risk of delamination propagation during the formation of the insulating encapsulation 132. Therefore, a semiconductor structure 10A with reduced defects, improved reliability, and improved yield can be achieved.

[0062] Figure 5A and Figure 5B A schematic cross-sectional view is shown of intermediate steps during a process for forming a first semiconductor die, according to some embodiments. Unless otherwise stated, the materials and methods of forming the components in these embodiments are the same as those in other embodiments. Figures 1A-1C The similar components in the illustrated embodiments are substantially the same, and these components are indicated by similar reference numerals. Regarding Figures 5A-5B Details of the forming process and materials of the components shown can be found in the discussion of the previous embodiments.

[0063] refer to Figure 5A And refer to Figures 1A-1B A semiconductor wafer 2100 is provided. Except that the semiconductor wafer 2100 further includes a peripheral region 210P between the sealing ring region 110S and the dicing region 110L, the semiconductor wafer 2100 may be similar to the semiconductor wafer 1100. In some embodiments, an additional sealing ring 1151 is disposed in the peripheral region 210P and embedded in the first dielectric layer 1131. In some embodiments, an additional bonding connector 1142D embedded in the first bonding dielectric layer 1141 is distributed above the sealing ring 115 and the additional sealing ring 1151. The additional bonding connector 1142D may (or may not) be physically connected to the underlying sealing ring 115 and / or the additional sealing ring 1151.

[0064] In some embodiments, a recess 210R is formed in a semiconductor wafer 2100 by etching, plasma dicing, or any suitable removal process. For example, forming a recess 210R includes forming a patterned mask (not shown) on the semiconductor wafer 2100, and then etching the portion of the patterned mask of the semiconductor wafer 2100 exposed by the pattern (e.g., openings). For example, the recess 210R is formed in a dicing region 110L and may further extend into a peripheral region 210P adjacent to the dicing region 110L. For example, after forming the recess 210R, a portion of a first bonding structure 114 in the peripheral region 210P is removed. In some embodiments, depending on the depth 210RD of the corresponding recess 210R, a portion of the first dielectric layer 1131 beneath said portion of the first bonding structure 114 in the peripheral region 210P is also removed. The depth 210RD, measured in the first direction D1, may be approximately... Within the range of approximately 5 μm. The lateral size (e.g., width) 210RW of the corresponding recess 210R can vary according to process requirements and is not limited in this disclosure. The recess 210R may be referred to as a shallow recess.

[0065] Continue to refer to Figure 5A After forming the recess 210R, a grooving process (e.g., laser grooving, plasma dicing, or the like) can be performed on the semiconductor wafer 2100. For example, a groove 210G is formed by a grooving process within a dicing channel region 110L between adjacent die regions (210-1 and 210-2). A grooving process can be performed on the corresponding recess 210R such that the corresponding groove 210G is connected to the corresponding recess 210R. The corresponding groove 210G can extend from the corresponding recess 210R along a first direction D1 to the first dielectric layer 1131. For example, the corresponding groove 210G penetrates the first dielectric layer 1131. In some embodiments, the groove 210G extends vertically into the first semiconductor substrate 111. In some embodiments, the corresponding groove 210G has a lateral size (e.g., width) 210GW smaller than the lateral size 210RW of the corresponding recess 210R.

[0066] refer to Figure 5B And refer to Figure 5A and Figure 1CA sawing process can be performed on the semiconductor wafer 2100 to completely separate the die regions (210-1 and 210-2) from each other to form individual first semiconductor dies 210. The sawing process can be performed via corresponding recesses 210R and underlying grooves 210G in the dicing channel region 110L. In some embodiments, the sawing process is a mechanical process using saw blades placed in the corresponding recesses 210R and underlying grooves 210G to saw through the remaining first semiconductor substrate 111. Other sawing processes can be used in other embodiments.

[0067] Following the sawing process, each monomerized first semiconductor die 210 may include a first flange portion 111G formed by a first semiconductor substrate 111 and a second flange portion 211G formed by a first interconnect structure 113. In a cross-sectional view, the sidewalls of the first semiconductor die 210 may have a stepped profile. For example, the sidewall 111X of the first flange portion 111G is formed by a sawing process, and the lower surface 111L of the first flange portion 111G is formed by a grooving process. The sidewall 1131W of the second flange portion 211G may be formed by a grooving process, and the lower surface 1131L of the second flange portion 211G connected to the sidewall 1131W may be formed by an etching process. The sidewall 1141W of the first bonding layer 1141 may be formed by an etching process. Due to the differences in etching / grooving / sawing processes, the surfaces of different regions of the first semiconductor die 210 may have different roughnesses. For example, the surface formed by etching / grooving (e.g., 1141W, 1131L, 1131W and 111L) can be smoother than the sidewall 111X of the first semiconductor substrate 111 formed by sawing.

[0068] like Figure 5BAs shown, the corresponding first semiconductor die 210 may include a first portion 210X, a second portion 210Y connected to the first portion 210X, and a third portion 210Z connected to the second portion 210Y. The first portion 210X is a first semiconductor substrate 111, the second portion 210Y is a first interconnect structure 113 or includes a portion of the first interconnect structure 113, and the third portion 210Z is a first bonding structure 114 or includes a first bonding structure 114 and a portion of the first interconnect structure 113 below the first bonding structure 114. The first portion 210X may laterally protrude from the second portion 210Y, and the second portion 210Y may laterally protrude from the third portion 210Z. The first portion 210X may be wider than the second portion 210Y, and the second portion 210Y may be wider than the third portion 210Z. For example, the difference in lateral size between the first and second portions (210X and 210Y) is equal to the lateral size of the first flange portion 111G, and the difference in lateral size between the second and third portions (210Y and 210Z) is equal to the lateral size of the second flange portion 211G. In some embodiments, the presence of the first and second flange portions (111G and 211G) facilitates the formation of the insulating encapsulation (see [link to documentation]). Figures 6A-6B To avoid stress concentration occurring on the periphery of the joint interface.

[0069] Figure 6A and Figure 6B Schematic cross-sectional views are shown of intermediate steps during a process for forming a semiconductor structure according to some embodiments. Unless otherwise stated, the materials and formation methods of the components in these embodiments are similar to those in the original document. Figures 2A-2D and Figures 4A-4B The similar components in the illustrated embodiments are substantially the same, and these components are indicated by similar reference numerals. Regarding Figures 6A-6B Details of the forming process and materials of the components shown can be found in the discussion of the previous embodiments.

[0070] refer to Figure 6A And refer to Figure 5B and Figures 2A-2B or Figure 4A The first semiconductor die 210 can be bonded to the semiconductor wafer 1200. The bonding process between the first semiconductor die 210 and the semiconductor wafer 1200 can be similar to... Figure 2AThe described process. For example, a first bonding structure 114 of the first semiconductor die 210 may be bonded to a second bonding structure 214 of the semiconductor wafer 1200, and the bonding interface IF20 of the first semiconductor die 210 and the semiconductor wafer 1200 may be substantially planar and flat. In some embodiments, a capping layer 331 is conformally (or blanket-covered) formed on the semiconductor wafer 1200 and the first semiconductor die 210. The capping layer 331 may be a single layer or may comprise multiple sublayers formed of different dielectric materials. The materials and formation methods of the capping layer 331 may be similar to those of the first semiconductor die 210. Figure 2B The capping layer 131 or as described in the document Figure 4A The material and method of forming the capping layer 231 described herein.

[0071] In some embodiments, the capping layer 331 includes a first portion 3311 lining a second portion 210Y of the first semiconductor die 210, a second portion 3312 lining a third portion 210Z of the first semiconductor die 210 and covering the semiconductor wafer 1200, and a third portion 3313' lining the first portion 210X of the first semiconductor die 210. The first portion 3311 may extend along a first direction D1 to physically contact the sidewall 1131W of the first dielectric layer 1131. The second portion 3312 may include a first portion 3312a connected to the first portion 3311 and covering the lower surface 1131L of the first dielectric layer 1131, a second portion 3312b connected to the first portion 331 and lining the sidewall 1141W of the first bonding dielectric layer 1141, and a third portion 3312c connected to the second portion 3312b and covering the top surface 1241t of the second bonding dielectric layer 1241, wherein the first portion 3312a and the third portion 3312c extend along a second direction D2, and the second portion 3312b extends along a first direction D1. In some embodiments, there is a gap with a vertical distance 3312d between the first portion 3312a and the third portion 3312c, wherein the vertical distance 3312d is non-zero. For example, the vertical distance 3312d is approximately Within a range of approximately 4 μm. The third portion 3313' may be in physical contact with the lower surface 111L and sidewall 111X of the first semiconductor substrate 111. The third portion 3313' may (or may not) cover the back side 111b of the first semiconductor substrate 111. In an alternative embodiment, omitting the entire third portion 3313' and / or the third portion of the second portion 3312 may partially cover the top surface 1241t of the second bonding dielectric layer 1241, such as... Figure 2B As stated above.

[0072] refer to Figure 6B And refer to Figure 6A and Figures 2C-2D or Figure 4BAn insulating encapsulation 132 may be formed on the semiconductor wafer 1200 to cover the capping layer 331 and the first semiconductor die 210. The material and formation method of the insulating encapsulation 132 may be similar to... Figure 2C The materials and methods of forming the insulating encapsulation 132 are described. In some embodiments, the vertical distance 3312d is large enough that the insulating encapsulation 132 can extend to fill the gap. In some embodiments, a planarization process (e.g., CMP, polishing, etching, combinations thereof, or the like) is performed. During the planarization process, a portion of the third portion 3313' overlying the first semiconductor die 210 may be removed to expose the first semiconductor substrate 111. For example, after the planarization process, the surfaces (e.g., 111b, 132t, 3313t) of the first semiconductor die 210, the insulating encapsulation 132, and the third portion 3313 are substantially flush (or coplanar) within a range of process variations.

[0073] In some embodiments, a thinning process is performed on the back side 121b of the second semiconductor substrate 121 until at least a portion of the TSV 125 is exposed in a tangible manner. The thinning process may be similar to... Figure 2C The described process. In some embodiments, the redistribution structure 150 is formed on the back side 121b of the second semiconductor substrate 121. The redistribution structure 150 may be similar to... Figure 4B The redistribution structure 150 described herein. In some embodiments, conductive terminals 142 are formed on the pads of the redistribution structure 150 to electrically couple to the TSV 125 via the redistribution structure 150. In an alternative embodiment, the redistribution structure 150 is replaced with Figure 2D The conductive pad 141 described herein.

[0074] Still referencing Figure 6B And refer to Figure 2D , Figure 3 or Figure 4B The monomerization process is selectively performed by cutting along scribe lines (not shown) to form individual semiconductor structures 10B. Conductive terminals 142 are used to selectively mount the semiconductor structures 10B onto a packaging substrate 20 to form an IC package, such as... Figure 3 As shown. For example, semiconductor structure 10B includes a first layer 301 stacked on a second layer 102', wherein the first layer 301 includes a first semiconductor die 210, a capping layer 331, and an insulating encapsulator 132, and the second layer 102' includes a second semiconductor die 120 formed by monomerizing semiconductor wafer 1200. The monomerization process can be similar to... Figure 2DThe process described herein. For example, after the monomerization process, the insulating encapsulation 132, the second portion 3312 of the capping layer 331, and the sidewalls (e.g., 132W, 3312W, and 120W) of the second semiconductor die 120 are substantially flush (or coplanar) with each other within a range of process variations. In the illustrated embodiment, the first layer 301 includes a capping layer 331 that spatially separates the insulating encapsulation 132 from the first semiconductor die 210 and separates the insulating encapsulation 132 from the second semiconductor die 120. The capping layer 331 can serve as a dielectric seal that isolates the insulating encapsulation 132 from the first and second semiconductor dies (210 and 120). In an alternative embodiment, omitting the third portion 3313 and / or the second portion 3312 of the capping layer 331 may partially cover the second semiconductor die 120, as shown below. Figure 2B As described, the presence of the capping layer 331 helps reduce the risk of delamination propagation during the formation of the insulating encapsulation 132. Therefore, a semiconductor structure 10B with reduced defects can be achieved, improving reliability and yield.

[0075] Figure 7A and Figure 7B Schematic cross-sectional views are shown of intermediate steps during a process for forming a semiconductor structure according to some embodiments. Unless otherwise stated, the materials and formation methods of the components in these embodiments are similar to those in the original document. Figures 6A-6B The similar components in the illustrated embodiments are substantially the same, and these components are indicated by similar reference numerals. Regarding Figures 7A-7B Details of the forming process and materials of the components shown can be found in the discussion of the previous embodiments.

[0076] refer to Figure 7A And refer to Figure 5B and Figure 6A The first semiconductor die 210 can be bonded to the semiconductor wafer 1200. The bonding process between the first semiconductor die 210 and the semiconductor wafer 1200 can be similar to... Figure 2A or Figure 6A The process described. For example, a first bonding structure 114 of the first semiconductor die 210 may be bonded to a second bonding structure 214 of the semiconductor wafer 1200, and the bonding interface IF20 of the first semiconductor die 210 and the semiconductor wafer 1200 may be substantially planar and flat. After the bonding process, a portion of the first semiconductor substrate 111 may be removed by etching, dicing, sawing, a combination thereof, or any suitable removal process. In some embodiments, a portion of the first semiconductor substrate 111 in the peripheral region 210P is removed. In some embodiments, not only a portion of the first semiconductor substrate 111 in the peripheral region 210P may be removed, but also a portion of the first semiconductor substrate 111 in the sealing ring region 110S.

[0077] In some embodiments, after partially removing the first semiconductor substrate 111, the first semiconductor die 210' includes a first semiconductor substrate 111' having sidewalls 111Y. The sidewalls 111Y of the first semiconductor substrate 111', the sidewalls 1131W of the first dielectric layer 1131, and the sidewalls 1141W of the first bonding dielectric layer 1141 may be laterally offset from each other. The first semiconductor die 210' may include a first portion 210X' having a lateral size (e.g., width) smaller than the second portion 210Y and a third portion 210Z having a lateral size (e.g., width) larger than the first portion 210X' and smaller than the second portion 210Y. For example, the lateral size (e.g., width) of the first semiconductor substrate 111' measured in the second direction D2 is smaller than the lateral size of the first interconnect structure 113 and the first bonding structure 114. In some embodiments, after the first semiconductor substrate 111' is formed, the upper surface 1131U of the first dielectric layer 1131, which is connected to the sidewall 1131W and is opposite to the lower surface 1131L, is exposed in an accessible manner. An additional sealing ring 1151 within the peripheral region 210P' may be located below the upper surface 1131U of the first dielectric layer 1131.

[0078] refer to Figure 7B And refer to Figure 7A and Figures 6A-6B The capping layer 431 may be conformally (or blanket-covered) formed on the semiconductor wafer 1200 and the first semiconductor die 210'. Except for the first portion 4311 and the third portion 4313, the capping layer 431 may be similar to... Figures 6A-6B The capping layer 331 described herein. For example, the first portion 4311 of the capping layer 431 includes a first portion 4311a extending along the second direction D2 to cover the upper surface 1131U and a second portion 4311b extending along the first direction D1 to cover the sidewall 1311W. The sidewall 111Y of the first semiconductor substrate 111' may be lined with a third portion 4313 of the capping layer 431. In an alternative embodiment, omitting the third portion 4313 and / or the second portion 3312 may partially cover the second bonding structure 124, as shown. Figure 2B As stated above.

[0079] After the capping layer 431 is formed, an insulating encapsulation 132 may be formed on the semiconductor wafer 1200 to cover the capping layer 431 and the first semiconductor die 210. In some embodiments, a thinning process is performed on the semiconductor wafer 1200 to expose the TSV 125 in an accessible manner. A redistribution structure 150 is selectively formed on the back side 121b of the second semiconductor substrate 121 to be electrically connected to the TSV 125. Conductive terminals 142 may then be formed on the redistribution structure 150. An individualization process is selectively performed by dicing along a scribing track (not shown) to form individual semiconductor structures 10C. The conductive terminals 142 are used to selectively mount the semiconductor structures 10C onto the package substrate 20 (see See [link to packaging substrate 20]). Figure 3 This is used to form an IC package. The formation of the insulating encapsulation 132, the thinning process, the formation of the redistribution structure 150, the formation of the conductive terminals 142, and the monomerization process can be combined with... Figure 6B The formation / process described in the text is similar, so it will not be repeated here.

[0080] Continue to refer to Figure 7B and Figure 6B Except for the first portion 210X' of the first semiconductor die 210', the capping layer 431 associated with the first portion 210X', and the insulating encapsulation 132 corresponding to the first portion 210X', the semiconductor structure 10C, including the first layer 401 stacked on the second layer 102', can be similar to the semiconductor structure 10B. The capping layer 431 can serve as a dielectric seal to isolate the insulating encapsulation 132 from the first and second semiconductor dies (210' and 120). The presence of the capping layer 431 can help reduce the risk of delamination propagation during the formation of the insulating encapsulation 132. Therefore, a semiconductor structure 10C with reduced defects can be achieved, improving reliability and yield.

[0081] Figure 8 A schematic cross-sectional view of a semiconductor structure according to some embodiments is shown. Unless otherwise stated, the materials and methods of forming the components in these embodiments are the same as those in the original. Figures 7A-7B The similar components in the illustrated embodiments are substantially the same, and these components are indicated by similar reference numerals. Regarding Figure 8 Details of the forming process and materials of the components shown can be found in the discussion of the previous embodiments.

[0082] refer to Figure 8 And refer to Figures 7A-7B Apart from the second portion 210Y' of the first semiconductor die 210", the capping layer 431 associated with the second portion 210Y', and the insulating encapsulator 132 corresponding to the second portion 210Y', the semiconductor structure 10D including the first layer 401' stacked on the second layer 102' can be similar to Figure 7BThe semiconductor structure 10C. For example, in... Figure 7A During the process of removing a portion of the first semiconductor substrate 111 in the peripheral region 210P, a portion of the first dielectric layer 1131' beneath said portion of the first semiconductor substrate 111 is also removed. In some embodiments, said portion of the first dielectric layer 1131' is removed to expose an additional sealing ring 1151. For example, the additional sealing ring 1151 serves as a stop layer during the removal process. The second portion 210Y' of the first semiconductor die 210" may include a first portion 210Y1 connected to the first portion 210X and a second portion 210Y2 perpendicularly between the first portion 210Y1 and the third portion 210Z. The lateral size of the first portion 210Y1, measured in the second direction D2, may be smaller than the lateral size of the second portion 210Y2.

[0083] In some embodiments, the first dielectric layer 1131' of the first semiconductor die 210 includes a sidewall 1131V substantially aligned with the sidewall 111Y of the first semiconductor substrate 111', an upper surface 1131U' connected to the sidewall 1131V, a sidewall 1131W connected to the upper surface 1131U' and laterally offset from the sidewall 1131V, and a lower surface 1131L connected to the sidewall 1131W. The upper surface 1151U of the additional sealing ring 1151 may be provided by the first dielectric layer 1131'. The upper surface 1131U' of the additional sealing ring 1151 is exposed. For example, the upper surface 1151U of the additional sealing ring 1151 is substantially flush (or coplanar) with the upper surface 1131U' of the first dielectric layer 1131' within a range of process variations. In some embodiments, the upper surface 1151U of the additional sealing ring 1151 protrudes from the upper surface 1131U' of the first dielectric layer 1131'. In alternative embodiments, the additional sealing ring 1151 remains (partially or completely) covered by the first dielectric layer 1131'.

[0084] Continue to refer to Figure 8 The capping layer 431' may be conformally (or blanket-covered) formed on the second semiconductor die 120 and the first semiconductor die 210". Except that the first portion 4311a' of the first portion 4311' covers the upper surfaces (1131U and 1151U) and the third portion 4313' extends to cover the sidewalls 1131V of the first dielectric layer 1131, the capping layer 431' may be similar to... Figure 7B The capping layer 431 described herein. In some embodiments, the first portion 4311a' is in direct contact with the upper surface 1151U of the additional sealing ring 1151. In an alternative embodiment, the portion of the third portion 4313' lining the sidewall 111Y of the first semiconductor substrate 111' and / or the second portion 3312 may partially cover the second bonding structure 124, as described above. Figure 2BThe capping layer 431' serves as a dielectric seal that isolates the insulating encapsulation 132 from the first and second semiconductor dies (210” and 120). The presence of the capping layer 431' helps reduce the risk of delamination propagation during the formation of the insulating encapsulation 132. Therefore, a semiconductor structure 10D with reduced defects can be achieved, improving reliability and yield. The semiconductor structure 10D is selectively mounted onto the package substrate 20 using conductive terminals 142 (see [link to documentation]). Figure 3 To form an IC package.

[0085] Other features and processes may also be included. For example, test structures can be incorporated to facilitate verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on redistribution layers or substrates, which allow testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0086] According to some embodiments, a semiconductor structure includes a first semiconductor die and a second semiconductor die stacked and bonded to each other, a capping layer sealing the bonding interface between the first and second semiconductor dies, and an insulating encapsulation disposed above the second semiconductor die and covering the first semiconductor die and the capping layer. The first semiconductor die includes a first portion and a second portion connected to the first portion, wherein the first portion is wider than the second portion.

[0087] In some embodiments, the first semiconductor die includes an interconnect structure beneath a semiconductor substrate and a bonding structure beneath the interconnect structure and electrically coupled to the interconnect structure and the second semiconductor die, wherein the capping layer extends conformally along the interconnect structure and the bonding structure. In some embodiments, the sidewalls of the interconnect structure are laterally offset from the sidewalls of the bonding structure. In some embodiments, a first portion of the first semiconductor die is an upper portion of the semiconductor substrate, and a second portion of the first semiconductor die includes a lower portion of the semiconductor substrate, an interconnect structure beneath the semiconductor substrate, and a bonding structure beneath the interconnect structure, wherein the lower portion is connected to the upper portion, and the bonding structure is electrically coupled to the interconnect structure and the second semiconductor die. In some embodiments, the first portion of the first semiconductor die is a semiconductor substrate, the second portion of the first semiconductor die is an interconnect structure beneath the semiconductor substrate, and the first semiconductor die further includes a bonding structure below the second portion and narrower than the second portion, the bonding structure being electrically coupled to the interconnect structure and the second semiconductor die. In some embodiments, the first portion of the first semiconductor die is an interconnect structure, the second portion of the first semiconductor die is a semiconductor substrate overlying the interconnect structure, and the first semiconductor die further includes a bonding structure below the second portion and wider than the second portion, the bonding structure being electrically coupled to the interconnect structure and the second semiconductor die. In some embodiments, the first semiconductor die includes a sealing ring, and the capping layer is in physical contact with the sealing ring. In some embodiments, the topmost surface of the second semiconductor die includes a first portion bonded to the first semiconductor die, a second portion surrounding the first portion and physically connected to the capping layer, and a third portion surrounding the second portion and physically connected to the insulating encapsulation. In some embodiments, the bonding interface is free of solder material. In some embodiments, the back side of the first semiconductor die and the back side of the insulating encapsulation are substantially coplanar. In some embodiments, the top surface of the capping layer is substantially coplanar with the back side of the first semiconductor die and the back side of the insulating encapsulation. In some embodiments, the sidewalls of the second semiconductor die, the sidewalls of the capping layer, and the sidewalls of the insulating encapsulation are substantially coplanar.

[0088] According to some alternative embodiments, a semiconductor structure includes a first semiconductor die, a second semiconductor die, and an insulating encapsulation. The first semiconductor die includes a first sidewall and a second sidewall laterally offset from the first sidewall. The second semiconductor die is located below the first semiconductor die and bonded to the first semiconductor die. The insulating encapsulation covers the first semiconductor die, the second semiconductor die, and a capping layer. The capping layer separates the insulating encapsulation from the first and second semiconductor dies.

[0089] In some embodiments, the first sidewall of the first semiconductor die is smoother than the second sidewall of the first semiconductor die. In some embodiments, the first semiconductor die further includes a third sidewall laterally offset from the first and second sidewalls. In some embodiments, the bonding interface between the first and second semiconductor dies is substantially flat.

[0090] According to some alternative embodiments, a method of manufacturing a semiconductor structure includes: bonding a first semiconductor die to a second semiconductor die, wherein the first semiconductor die includes a first portion and a second portion connected to the first portion, and the first portion is wider than the second portion; forming a capping layer to seal the bonding interface between the first and second semiconductor dies; and forming an insulating encapsulation over the second semiconductor die to cover the first semiconductor die and the capping layer.

[0091] In some embodiments, bonding the first semiconductor die to the second semiconductor die includes forming dielectric-to-dielectric and metal-to-metal bonds at the bonding interface between the first and second semiconductor dies, wherein the bonding interface is solder-free. In some embodiments, forming the capping layer includes conformally depositing a capping material layer on the first and second semiconductor dies. In some embodiments, forming the insulating encapsulation includes: forming an insulating material layer on the second semiconductor die to cover the first semiconductor die and the capping layer; and performing a planarization process on the insulating material layer, wherein after the planarization process, the top surface of the insulating encapsulation, the top surface of the capping layer, and the top surface of the first semiconductor die are substantially flush with each other.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor structure, characterized by, Comprising: a first semiconductor die and a second semiconductor die stacked and bonded to each other, the first semiconductor die including a first portion and a second portion connected to the first portion, and the first portion being wider than the second portion; a cap layer sealing a bonding interface of the first semiconductor die and the second semiconductor die; and an insulative encapsulation disposed over the second semiconductor die and covering the first semiconductor die and the cap layer. wherein the first semiconductor die includes:

2. The semiconductor structure of claim 1, wherein, an interconnect structure under a semiconductor substrate; and a bonding structure under the interconnect structure and electrically coupled to the interconnect structure and the second semiconductor die, wherein the cap layer conformally extends along the interconnect structure and the bonding structure. wherein:

3. The semiconductor structure of claim 1, wherein, the first portion of the first semiconductor die is an upper portion of a semiconductor substrate, and the second portion of the first semiconductor die includes a lower portion of the semiconductor substrate, an interconnect structure under the semiconductor substrate, and a bonding structure under the interconnect structure, wherein the lower portion is connected to the upper portion, and the bonding structure is electrically coupled to the interconnect structure and the second semiconductor die. wherein:

4. The semiconductor structure of claim 1, wherein, the first portion of the first semiconductor die is a semiconductor substrate, the second portion of the first semiconductor die is an interconnect structure under the semiconductor substrate, and the first semiconductor die further includes a bonding structure under the second portion and narrower than the second portion, the bonding structure electrically coupled to the interconnect structure and the second semiconductor die. wherein:

5. The semiconductor structure of claim 1, wherein, the first portion of the first semiconductor die is an interconnect structure, the second portion of the first semiconductor die is a semiconductor substrate overlying the interconnect structure, and the first semiconductor die further includes a bonding structure under the second portion and wider than the second portion, the bonding structure electrically coupled to the interconnect structure and the second semiconductor die. wherein the first semiconductor die includes a seal ring, and the cap layer is in physical contact with the seal ring.

6. The semiconductor structure of claim 1, wherein, wherein a topmost surface of the second semiconductor die includes a first portion bonded to the first semiconductor die, a second portion surrounding the first portion and physically connected to the cap layer, and a third portion surrounding the second portion and physically connected to the insulative encapsulation.

7. The semiconductor structure of claim 1, wherein, Comprising:

8. A semiconductor structure, characterized by a first semiconductor die including a first sidewall and a second sidewall laterally offset from the first sidewall; a second semiconductor die under the first semiconductor die and bonded to the first semiconductor die; a cap layer conformally lining the first semiconductor die and the second semiconductor die to seal a bonding interface of the first semiconductor die and the second semiconductor die; and an insulative encapsulation covering the first semiconductor die, the second semiconductor die, and the cap layer, the cap layer separating the insulative encapsulation from the first semiconductor die and the second semiconductor die. ​ 9. The semiconductor structure of claim 8, wherein, wherein the first sidewall of the first semiconductor die is smoother than the second sidewall of the first semiconductor die.

10. The semiconductor structure of claim 8, wherein, wherein the first semiconductor die further comprises a third sidewall laterally misaligned from the first sidewall and the second sidewall.

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