Chip packaging structure and radio frequency module with same

Abstract

The utility model provides a chip packaging structure and a radio frequency module with the chip packaging structure, the chip packaging structure comprises a substrate, the upper surface of which is provided with a solder mask layer, a substrate bonding pad and a substrate enclosing wall bonding pad; the solder mask layer is configured to be provided with a first solder mask opening and a chip enclosing wall opening, and the first solder mask opening and the chip enclosing wall opening are configured to correspond to an area of a filter chip; the at least one filter chip is configured to comprise a filter salient point, an interdigital transducer and a filter wall bonding pad, is electrically connected with the substrate bonding pad through the filter salient point, and forms a wall corresponding to the substrate wall bonding pad through the filter wall bonding pad; a cavity structure is formed below the at least one filter chip; and the plastic packaging layer covers the solder mask layer and the at least one filter chip so as to cover the area of the whole substrate.

Description

Technical Field

[0001] This utility model generally relates to chip packaging structures, and more specifically to radio frequency filter chip packaging structures and radio frequency modules having the packaging structures. Background Technology

[0002] Radio frequency (RF) filters are used to attenuate high-frequency interference signals generated by high-frequency electronic devices. One type of RF filter is the surface acoustic wave (SAW) filter. SAW filters are widely used in wireless communication systems to filter out signals outside of specific frequencies. SAW filters are characterized by their small size and high performance.

[0003] The working principle of a SAW filter is to allow sound waves to propagate on the surface of the interdigital transducer (IDT) of the SAW filter. Therefore, a cavity structure must be ensured on the surface of the IDT; otherwise, the propagation of sound waves will be affected, thus affecting product performance. As a result, there are special requirements for the packaging of SAW filters.

[0004] The filter cavity structure required for filter chip modules is generally achieved through film bonding or WLP (wafer-level packaging).

[0005] Existing solutions that use a black film to form a cavity for encapsulation create a fully hollow structure at the bottom of both filter and non-filter chips by directly applying the film after chip surface mounting. However, existing black film-covered chip packaging solutions have the following drawbacks: 1) High cost; 2) Poor material heat resistance, making rework impossible during the mounting and use phase, resulting in poor workability; 3) Fewer metal bump supports in the fully hollow structure lead to poor stress resistance and potential reliability risks. Utility Model Content

[0006] This invention uses a wall welding design to create a stable cavity structure for the filter chip, and its wall area is large, which strengthens its stress resistance and effectively solves the problem of metal bump cracks after the current filter devices are packaged.

[0007] In the RF module packaging structure according to this utility model, a cavity is formed at the bottom of the filter chip, rather than the bottom of the filter chip being completely filled with molding compound.

[0008] One aspect of this utility model provides a chip packaging structure, characterized in that it comprises: a substrate having a solder resist layer, substrate pads, and substrate perimeter pads disposed on its upper surface; the solder resist layer being configured to have a first solder resist opening and a chip perimeter opening, the first solder resist opening and the chip perimeter opening being configured to correspond to the region of a filter chip; at least one filter chip being configured to include filter bumps, interdigital transducers, and filter perimeter pads, forming an electrical connection with the substrate pads through the filter bumps, and forming a perimeter corresponding to the substrate perimeter pads through the filter perimeter pads, thereby forming a cavity structure under the at least one filter chip; and a molding compound layer covering the solder resist layer and the at least one filter chip to cover the entire area of ​​the substrate.

[0009] One aspect of this utility model provides a chip packaging structure, characterized in that it further includes at least one non-filter chip configured to include non-filter bumps, the solder mask layer is configured to further include a second solder mask opening, the second solder mask opening being configured to correspond to a region of the at least one non-filter chip, the at least one non-filter chip forming an electrical connection with a substrate pad through the non-filter bumps, and forming a molding compound filling underneath it.

[0010] One aspect of this utility model provides a chip packaging structure, characterized in that the molding layer comprises an epoxy resin film.

[0011] One aspect of this utility model provides a chip packaging structure, characterized in that the solder resist layer is configured to include a solder resist ink, a DAF film, an insulating tape, an epoxy resin film, a phenolic resin film, a polyimide film, or a liquid crystal polymer film structure.

[0012] One aspect of this invention provides a chip packaging structure, characterized in that the height of the cavity is configured in the range of 1-100 μm.

[0013] One aspect of this invention provides a chip packaging structure, characterized in that the bumps are configured to include tin-coated copper pillars or pure tin balls.

[0014] One aspect of this utility model provides a chip packaging structure, characterized in that the enclosure is formed by printing solder paste.

[0015] One aspect of this utility model provides a chip packaging structure, characterized in that the first solder mask opening corresponds to the substrate pad and is configured such that its area is larger than that of the substrate pad.

[0016] One aspect of this invention provides a chip packaging structure, characterized in that the second solder mask opening is configured such that its area is larger than the area of ​​the at least one non-filter chip.

[0017] One aspect of this utility model provides a chip packaging structure, characterized in that the chip enclosure opening is configured as an annulus having a shape similar to or the same as the outline of the at least one filter chip, and the outer edge of the annulus is set to be smaller than the side length of the outline of the at least one filter chip.

[0018] One aspect of this utility model provides a radio frequency module, characterized in that the radio frequency module is configured to have the chip packaging structure described in any one of the above. Attached Figure Description

[0019] Figure 1 This is a top view showing the structure of the substrate and solder resist layer according to the present invention.

[0020] Figure 2 This is a bottom view showing the filter chip according to the present invention;

[0021] Figure 3 This is a cross-sectional view showing a chip packaging structure according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram illustrating a chip packaging process according to an embodiment of the present invention; and

[0023] Figure 5 This is a flowchart illustrating the chip packaging process according to an embodiment of the present invention. Detailed Implementation

[0024] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “coupled,” “connected,” and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are physically in contact with each other. The terms “transmit,” “receive,” and “communicate,” and their derivatives cover both direct and indirect communication. The terms “comprise,” “include,” and their derivatives refer to, but are not limited to, those including, those including, those including, those including. The term “or” is inclusive, meaning and / or. The phrase “associated with,” and its derivatives refer to, including, being contained within, interconnected, containing, being included in, being connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposed, proximate, bound or bound to, having, having attributes, having a relationship or being related to, etc. The term “controller” refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0025] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0026] In this patent document, the application combination of modules and the hierarchical division of sub-modules are for illustrative purposes only. Without departing from the scope of this disclosure, the application combination of modules and the hierarchical division of sub-modules can be in different ways.

[0027] Figure 1 This is a top view showing the structure of the substrate and solder resist layer according to the present invention.

[0028] refer to Figure 1A solder resist layer is formed on top of the substrate. The solder resist layer is configured to cover the substrate, and in the region corresponding to the filter chip, a first solder resist opening corresponding to a substrate pad is formed; in the region corresponding to a non-filter chip, a second solder resist opening corresponding to the outline of the non-filter chip is formed. The substrate pad corresponds to a bump on the filter chip or non-filter chip to form an electrical connection with the filter chip or non-filter chip through the bump. Preferably, the substrate pad and the bump on the filter chip or non-filter chip have a one-to-one correspondence. The first solder resist opening corresponds to the substrate pad and is configured to have an area larger than the substrate pad; the second solder resist opening is configured to have an area larger than the non-filter chip. According to an embodiment of the present invention, the bump can be formed using a metallic material, such as a tinned copper pillar or a pure tin ball.

[0029] Furthermore, in the region of the solder mask corresponding to the filter chip, an opening corresponding to the chip perimeter region is formed. This chip perimeter opening is configured as annular and is located outside the first solder mask opening and within the outline of the filter chip. Preferably, the chip perimeter opening is configured to have a shape similar to or the same as the filter chip outline, and its size is configured such that the outer side of the annulus is smaller than or slightly smaller than the side length of the filter chip outline (e.g., the side length of the opening is 90% of the side length of the filter chip). A substrate perimeter pad is formed within the chip perimeter opening.

[0030] According to embodiments of the present invention, the solder resist layer can be configured to include structures such as solder resist ink, DAF film, insulating tape, epoxy resin film, phenolic resin film, polyimide film, or liquid crystal polymer film.

[0031] Figure 2 This is a bottom view showing the filter chip according to the present invention.

[0032] refer to Figure 2 At the bottom of the filter chip, filter bumps, interdigital transducers, and filter wall pads are configured. The filter bumps correspond to the substrate pads to form an electrical connection with the substrate. The filter wall pads correspond to the chip wall openings to form a wall formed by solder paste within the chip wall openings.

[0033] Figure 3 This is a cross-sectional view showing a chip package structure according to an embodiment of the present invention. The following references... Figure 3 This describes the chip packaging structure conceived according to the present invention.

[0034] like Figure 3As shown, a solder resist layer is disposed on a substrate, the solder resist layer having a first solder resist opening, a second solder resist opening, and a chip perimeter opening. The first solder resist opening corresponds to a substrate pad and is configured such that its area is larger than the substrate pad to connect the substrate pad and the filter chip via bumps. The second solder resist opening corresponds to a non-filter chip and is configured such that its area is larger than the area of ​​the non-filter chip. The chip perimeter opening is configured as annular and is disposed outside the first solder resist opening and within the outline of the filter chip to form a perimeter below the filter chip. According to an embodiment of the present invention, the perimeter is configured to have a width of less than 100 micrometers (e.g., 30 micrometers).

[0035] like Figure 3 As shown, the filter chip and non-filter chip are flip-chip bonded to the substrate using SMT (Surface Mount Technology). Furthermore, a molding compound is used to seal and protect the filter chip and non-filter chip. Due to the presence of the chip enclosure, a cavity is formed below the filter chip. Preferably, the cavity is configured to have a height range of 1μm-100μm. There is no enclosure below the non-filter chip; therefore, due to the fluidity of the molding compound, there is no cavity below the non-filter chip, and the non-filter chip is connected to the substrate pads via bumps. According to an embodiment of the present invention, the molding compound is configured to be formed using a molding compound comprising an epoxy resin film. According to an embodiment of the present invention, by forming an annular enclosure at the bottom of the filter chip, a cavity structure is first formed at the bottom of the filter chip to prevent the molding compound from intruding into the cavity structure during pressurization; furthermore, the enclosure structure formed by SMT provides additional support outside the filter bumps, thereby effectively reducing the risk of metal bump cracking.

[0036] Figure 4 This is a schematic diagram illustrating a chip packaging process according to an embodiment of the present invention. Figure 5 This is a flowchart illustrating the chip packaging process according to an embodiment of the present invention.

[0037] refer to Figure 4 and Figure 5 First, in S501, a substrate carrier (i.e., a substrate) is provided, and at least one filter chip with bumps (e.g., a surface acoustic wave filter chip) and at least one non-filter chip with bumps are provided.

[0038] In step S502, a wall is formed on the substrate wall pads. Preferably, a solder paste wall is formed on the substrate wall pads by printing solder paste.

[0039] In step S503, the at least one filter chip and at least one non-filter chip are flip-chip bonded to the substrate using surface mount technology (SMT). Flip-chip bonding electrically connects the bumps of the filter chip and non-filter chip to the substrate pads, and solder paste walls are formed between the substrate wall pads and the chip wall pads, creating a cavity between the bottom of the filter chip and the upper surface of the substrate.

[0040] In step S504, a compression molding process is performed, during which the bottom of at least one non-filter chip is filled with molding compound, while the bottom of at least one filter chip remains empty due to the barrier structure blocking the molding compound. According to an embodiment of this invention, the epoxy resin layer is preferably formed by low-pressure molding, with pressure parameters controlled at 0.6-1.0 MPa and temperature configured at 150-175°C.

[0041] In step S505, laser marking and cutting processes are performed to complete the packaging of the module chip.

[0042] Based on the above references Figures 1 to 5 The description describes a design that uses a perimeter welding technique to create a stable cavity structure for the filter chip. This perimeter has a large area and strong stress resistance, effectively solving the problem of metal bump cracking that occurs after reliability issues arise in current filter devices. Furthermore, the cavity structure formed by the perimeter effectively prevents the intrusion of molding compound, thus replacing existing technologies such as resin black film encapsulation or thin-film barrier molding. The annular perimeter formed by welding also effectively prevents external intrusion such as moisture, improving packaging reliability. Simultaneously, forming the perimeter through solder paste printing eliminates the need for special processes to create the cavity structure, further reducing manufacturing costs.

[0043] According to an embodiment of the present invention, an RF module is also provided, which is configured to have a chip packaging structure as described above.

[0044] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0045] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined solely by the claims.

Claims

1. A chip package structure, characterized by, Comprising: a substrate, on a top surface of which a solder resist layer, substrate pads and substrate wall pads are configured; the solder resist layer is configured to have a first solder resist opening and a chip wall opening, the first solder resist opening and the chip wall opening are configured to correspond to an area of a filter chip; at least one filter chip is configured to include filter bumps, an interdigital transducer and filter wall pads, the filter bumps form electrical connection with the substrate pads, and the filter wall pads form walls corresponding to the substrate wall pads to form a cavity structure below the at least one filter chip; and a plastic encapsulation layer covers the solder resist layer and the at least one filter chip to cover an entire area of the substrate.

2. The chip package structure of claim 1, wherein, Further comprising at least one non-filter chip configured to include non-filter bumps, the solder resist layer is configured to further include a second solder resist opening, the second solder resist opening is configured to correspond to an area of the at least one non-filter chip, the at least one non-filter chip forms electrical connection with the substrate pads through the non-filter bumps, and is filled with plastic encapsulation below.

3. The chip package structure of claim 1, wherein, The plastic encapsulation layer includes an epoxy resin film.

4. The chip package structure of claim 1, wherein, The solder resist layer is configured to include a solder resist ink, a DAF film, an insulating tape, an epoxy resin film, a phenolic resin film, a polyimide film or a liquid crystal polymer film structure.

5. The chip package structure of claim 1, wherein, The height of the cavity is configured to be in a range of 1-100 μm.

6. The chip package structure of claim 1, wherein, The bumps are configured to include tin-coated copper pillars or pure tin balls.

7. The chip package structure of claim 1, wherein, The walls are formed by printing tin paste.

8. The chip package structure of claim 1, wherein, The first solder resist opening corresponds to the substrate pads, and is configured to have an area greater than that of the substrate pads.

9. The chip package structure of claim 2, wherein The second solder resist opening is configured to have an area greater than that of the at least one non-filter chip.

10. The chip package structure of claim 1, wherein The chip wall opening is configured to have a ring shape similar or identical to a contour of the at least one filter chip, and an outer edge of the ring shape is set to be smaller than a contour edge length of the at least one filter chip.

11. A radio frequency module, characterized by The radio frequency module is configured to have a chip packaging structure according to any one of claims 1-10.

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