Comprehensive entertainment content management and control device based on dpi

Abstract

The utility model provides a dpi-based comprehensive entertainment content management and control device, which comprises a main board card and an auxiliary board card, and is characterized in that a first processing chip, a second processing chip, a third processing chip, a first plug-in interface, a second plug-in interface, a third plug-in interface and a fourth plug-in interface are integrated on the main board card; a fourth processing chip, a fifth insertion port and a sixth insertion port are integrated on the auxiliary board card, the first processing chip is electrically connected with the first insertion port, the second processing chip is electrically connected with the second insertion port, and the third processing chip is electrically connected with the first processing chip, the second processing chip, the third insertion port and the fourth insertion port. The fourth processing chip is electrically connected with a fifth plug-in port and a sixth plug-in port, the first plug-in port is connected with a data output port of an upper computer, the second plug-in port is connected with a data input port of the upper computer, the third plug-in port is electrically connected with the fifth plug-in port, and the fourth plug-in port is electrically connected with the sixth plug-in port. The beneficial effects of the utility model are that the system can adapt to the management and control of diversified entertainment contents.

Description

Technical Field

[0001] This utility model relates to the technical field of internet behavior management devices, and more specifically, to a comprehensive entertainment content control device based on DPI. Background Technology

[0002] As is well known, Internet access management devices are typically used between two or more networks, such as between an intranet and an extranet. The APP application in the Internet access management device analyzes network data packets to determine whether there is a threat, and after processing, transmits the data packets according to certain routing rules. If the Internet access management device experiences a power outage or crash, the network segments connected to this device must also communicate with each other. At this time, each network must be interconnected.

[0003] Existing internet access management devices have many shortcomings, mainly in that application filtering is primarily achieved through URL (uniform resource locator) libraries. The problems with this approach are: 1. It cannot effectively and accurately manage new connection protocols and CDNs (Content Delivery Networks). For example, QUC (Quick UDP Internet Connections), gRPC, and other end-to-end transport protocols can spoof SNI (Server Name Indication), presenting the gateway with a legitimate URL, but its actual payload is encrypted and cannot be detected; 2. It cannot adapt to non-standard ports and masquerading transport protocols. For example, WS can disguise itself as a normal H2 packet, but encrypt its own content within its payload.

[0004] Furthermore, since modern entertainment media often employ a variety of entertainment methods such as peer-to-peer (P2P), VoIP, streaming media, Web TV, and audio / video chat, it is impractical to collect and import all of them into the URL database. This would easily cause processor crashes, affect the data packet processing process, reduce processing efficiency, and ultimately leave the control of entertainment content in a helpless state, unable to adapt to the control of diverse entertainment content. Utility Model Content

[0005] The technical problem to be solved by this utility model is to improve the efficiency of data packet processing and adapt to the management of diverse entertainment content. In order to overcome the defects of the above-mentioned prior art (or related technology), this utility model provides a comprehensive entertainment content management device based on DPI.

[0006] This utility model provides a DPI-based integrated entertainment content management device, including a motherboard and a sub-board. The motherboard integrates a first processing chip, a second processing chip, a third processing chip, a first connector, a second connector, a third connector, and a fourth connector. The sub-board integrates a fourth processing chip, a fifth connector, and a sixth connector. The first processing chip is electrically connected to the first connector, the second processing chip is electrically connected to the second connector, the third processing chip is electrically connected to the first processing chip, the second processing chip, the third connector, and the fourth connector, respectively, and the fourth processing chip is electrically connected to the fifth connector and the sub-board. The sixth connector is electrically connected to the host computer. The first connector is connected to the data output port of the host computer, and the second connector is connected to the data input port of the host computer. The third connector is electrically connected to the fifth connector via a first adapter cable to form a data channel. The fourth connector is electrically connected to the sixth connector via a second adapter cable to form an instruction channel. The first processing chip receives multiple entertainment content data packets from the data output port. The third processing chip transmits each entertainment content data packet to the fourth processing chip via the data channel to obtain processing signaling, and receives the processing signaling via the instruction channel and transmits it to the second processing chip to assist the user in managing entertainment content.

[0007] Compared with existing technologies, the DPI-based integrated entertainment content management device proposed in this application has the following advantages:

[0008] This application employs a partitioned processing design with a motherboard and a sub-board. The motherboard integrates three processing chips responsible for data transmission, while the sub-board integrates a single, independent processing chip responsible for data packet processing. The motherboard handles data transmission, while the sub-board handles data processing, and the two operate independently. A separate data and command channel is formed between the motherboard and sub-board via an adapter cable to handle data packet transmission and signaling. This reduces downtime caused by excessive data volume, and the partitioned processing significantly improves data packet processing efficiency, adapting to the management challenges of diverse entertainment content.

[0009] In one possible implementation, the fourth processing chip includes a first processor, a second processor, and a third processor. The second processor is electrically connected to the first processor and the third processor, respectively. The first processor associates user information of each of the externally input entertainment content data packets and grants internet access. The second processor sequentially extracts feature words, archives, and performs big data association on each of the entertainment content data packets to obtain the processing signaling. The third processor transmits the processing signaling to the third processing chip.

[0010] Compared with existing technologies, the above technical solution can reasonably divide the functions of Internet access control, data packet analysis, and signaling transmission processing, thereby improving the processing efficiency of each unit and reducing interference.

[0011] In one possible implementation, the fourth processing chip further includes a memory electrically connected to the second processor, which stores the entertainment content data packets and the processing signaling.

[0012] In one possible implementation, the user information received by the first processor includes the user account, MAC address, and IP address.

[0013] In one possible implementation, the processing signaling obtained by the second processor includes a 5-tuple, protocol, header, SNI, path, certificate, encryption features, and fingerprint information.

[0014] In one possible implementation, the processing signaling received by the second processor further includes port rate limiting instructions, IP rate limiting instructions, and packet dropping instructions.

[0015] In one possible implementation, the first processing chip, the second processing chip, the third processing chip, and the fourth processing chip are programmable microcontroller chips.

[0016] In one possible implementation, the first and second connectors are Ethernet interfaces.

[0017] In one possible implementation, the third, fourth, fifth, and sixth connectors are USB interfaces.

[0018] In one possible implementation, the sub-board also integrates a battery pack, which is connected to the fourth processing chip to supply power to the fourth processing chip. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structural principle of this utility model;

[0020] Explanation of reference numerals in the attached diagram: 1. Motherboard card; 11. First processing chip; 12. Second processing chip; 13. Third processing chip; 14. First connector; 15. Second connector; 16. Third connector; 17. Fourth connector; 2. Sub-board card; 21. Fourth processing chip; 22. Fifth connector; 23. Sixth connector; 3. Data output port; 4. Data input port; 5. First adapter cable; 6. Second adapter cable. Detailed Implementation

[0021] First, those skilled in the art should understand that these embodiments are merely used to explain the technical principles of the embodiments of this application and are not intended to limit the scope of protection of the embodiments of this application. Those skilled in the art can make adjustments as needed to adapt to specific application scenarios.

[0022] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0023] See Figure 1 This application discloses a DPI-based integrated entertainment content management device. To overcome the problem that existing internet behavior management devices cannot adapt to the management of diverse entertainment content, this application introduces DPI (deep packet inspection) technology to analyze the payload of entertainment content data packets, determine their respective applications and services, and then provide this information to network administrators for unified management of various entertainment content within the same application. The technical solution adopted in this application is as follows: A DPI-based integrated entertainment content management device is provided, including a motherboard 1 and a secondary board 2. The motherboard 1 integrates a first processing chip 11, a second processing chip 12, a third processing chip 13, a first connector 14, a second connector 15, a third connector 16, and a fourth connector 17. The secondary board 2 integrates a fourth processing chip 21, a fifth connector 22, and a sixth connector 23. The first processing chip 11 is electrically connected to the first connector 14, the second processing chip 12 is electrically connected to the second connector 15, and the third processing chip 13 is electrically connected to the first processing chip 11. The second processing chip 12, the third connector 16, and the fourth connector 17 are electrically connected. The fourth processing chip 21 is electrically connected to the fifth connector 22 and the sixth connector 23, respectively. The first connector 14 is connected to the data output port 3 of the host computer, and the second connector 15 is connected to the data input port 4 of the host computer. The third connector 16 is electrically connected to the fifth connector 22 through the first adapter cable 5 to form a data channel. The fourth connector 17 is electrically connected to the sixth connector 23 through the second adapter cable 6 to form an instruction channel. The first processing chip 11 receives multiple entertainment content data packets from the data output port. The third processing chip 13 transmits each entertainment content data packet to the fourth processing chip 21 through the data channel to obtain processing signals, and receives processing signals through the instruction channel and transmits them to the second processing chip 12. The second processing chip 12 outputs processing signals to the data input port 4 to assist the user in managing entertainment content.

[0024] The fourth processing chip 21 includes a first processor, a second processor, and a third processor. The second processor is electrically connected to the first processor and the third processor, respectively. The first processor associates user information of each entertainment content data packet input from the outside and grants access to the Internet. The second processor sequentially extracts feature words, archives, and associates big data to obtain processing signaling for each entertainment content data packet. The third processor transmits the processing signaling to the third processing chip 13.

[0025] The fourth processing chip also includes a memory, which is electrically connected to the second processor, and stores various entertainment content data packets and processing signals in the memory.

[0026] The first processor can work with existing identity authentication servers to complete internet access control functions, including RADIUS and 802.1x. In this process, the first processor associates user accounts, MAC addresses, IP addresses and other information, which can not only manage user internet behavior and permissions in a unified manner, but also provide a basis for subsequent judgment of control effectiveness.

[0027] The fourth processing chip 21 uses DPI technology to identify the characteristic words of entertainment content data packets, including the five-tuple, protocol, header, SNI, path, certificate, encryption features, fingerprint, etc. of the entertainment content data packets. These characteristic words are all within the scope of DPI technology. These characteristic words are extracted and archived, and big data analysis and correlation are performed. Even if the application contains multiple media protocols, advanced deception and encryption technologies can be used to analyze the unencrypted parts. Combined with the analysis of routing features and spoofed SNI, the threat level can be determined. After this series of processing, the system can associate multiple types of data packets with a certain application, thereby completing the control of multiple entertainment applications.

[0028] The third processing chip 13 is connected to the fourth processing chip 21 through a data channel and an instruction channel. The data channel is responsible for transmitting the traffic of the third processing chip 13 to the fourth processing chip 21, and the instruction channel is responsible for receiving the processing signaling sent by the fourth processing chip 21 and executing a series of operations, including port rate limiting instructions, IP rate limiting instructions, and instructions to drop specific data packets.

[0029] In the fourth processing chip 21, a fourth processor can be added, which is mainly responsible for generating and distributing system parameters and providing a user-friendly interface for network administrators to perform convenient operations for network management. The fourth processor is combined with the host computer to provide a human-computer interaction interface in the form of a web UI. This interface provides a collection of common known application features pre-stored in the system. After the system has been running for a period of time, the application features collected during the network operation are collected and displayed. All displayed feature collections can be used by the administrator to formulate policies, including blocking, dropping, allowing, and custom policies. Independent operations can be performed according to user groups. After the user saves the policy, the system will convert the policy into rules and distribute them to the fourth processing chip 21 to realize the implementation of user rules.

[0030] The first processing chip 11, the second processing chip 12, the third processing chip 13, and the fourth processing chip 21 are programmable microcontroller chips. The first interface 14 and the second interface 15 are Ethernet interfaces, and the third interface 16, the fourth interface 17, the fifth interface 22, and the sixth interface 23 are USB interfaces. The sub-board 2 also integrates a battery pack, which is connected to the fourth processing chip 21 to provide power to the fourth processing chip 21.

[0031] By fully recording and analyzing entertainment content data packets, valid data tags can be extracted. During the decoding process of entertainment content data packets, other interference packets may be encountered. Port filtering is performed through the interface, and protocol filtering is performed by the chip, so that valid information flow can be obtained.

[0032] During the data stream decoding process, the protocol view is displayed in column form, which enables rapid data analysis, viewing of traffic, network connections, and valid information, extracting summaries, and obtaining diagnostic results, thereby achieving the goal of comprehensive entertainment content management.

[0033] In this application, the Internet access behavior management gateway using DPI technology has a logical concept of command channel and data channel. In practice, a single data communication channel can be used in combination, without using two separate physical channels for data transmission.

[0034] This application associates various transmission protocols and content of applications in complex network environments, and then provides them to network administrators in a feature-based centralized manner for decision-making. This enables the positioning and control of modern multimedia applications, effectively manages user access to entertainment applications, and achieves efficient control over entertainment content.

[0035] In the description of this application, the references to terms such as "an embodiment," "some embodiments," "in this embodiment," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0036] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dpi-based integrated entertainment content management device, characterized by, The application relates to a mainboard card and a subboard card, wherein the mainboard card is integrated with a first processing chip, a second processing chip, a third processing chip, a first plug-in interface, a second plug-in interface, a third plug-in interface and a fourth plug-in interface; the subboard card is integrated with a fourth processing chip, a fifth plug-in interface and a sixth plug-in interface; the first processing chip is electrically connected with the first plug-in interface; the second processing chip is electrically connected with the second plug-in interface; the third processing chip is electrically connected with the first processing chip, the second processing chip, the third plug-in interface and the fourth plug-in interface respectively; the fourth processing chip is electrically connected with the fifth plug-in interface and the sixth plug-in interface respectively; the first plug-in interface is connected with a data output port of an upper computer; the second plug-in interface is connected with a data input port of the upper computer; the third plug-in interface is electrically connected with the fifth plug-in interface through a first conversion line to form a data channel; the fourth plug-in interface is electrically connected with the sixth plug-in interface through a second conversion line to form an instruction channel; the first processing chip receives a plurality of entertainment content data packets from the data output port; the third processing chip transmits the entertainment content data packets to the fourth processing chip to obtain processing signaling; the processing signaling is received by the third processing chip through the instruction channel and is transmitted to the second processing chip; the second processing chip outputs the processing signaling to the data input port to assist a user in controlling the entertainment content.

2. The integrated entertainment content management device according to claim 1, wherein The fourth processing chip comprises a first processor, a second processor and a third processor; the second processor is electrically connected with the first processor and the third processor; the first processor is used for associating user information of the external input entertainment content data packets and for online access; the second processor is used for extracting a characteristic word, archiving and obtaining big data association of the entertainment content data packets to obtain the processing signaling; and the third processor is used for transmitting the processing signaling to the third processing chip.

3. The integrated entertainment content management device of claim 2, wherein, The fourth processing chip further comprises a memory which is electrically connected with the second processor and is used for storing the entertainment content data packets and the processing signaling.

4. The integrated entertainment content management device of claim 2, wherein, The user information received by the first processor comprises a user account, a mac address and an ip address.

5. The integrated entertainment content management device of claim 2, wherein, The processing signaling obtained by the second processor comprises five-tuple information, protocol information, packet header information, sni information, path information, certificate information, encryption characteristic information and fingerprint information.

6. The integrated entertainment content management device of claim 5, wherein, The processing signaling obtained by the second processor further comprises port speed limiting instructions, ip speed limiting instructions and data packet discarding instructions.

7. The integrated entertainment content management device of claim 1, wherein, The first processing chip, the second processing chip, the third processing chip and the fourth processing chip are programmable single-chip microcomputer chips.

8. The integrated entertainment content management device of claim 1, wherein, The first plug-in interface and the second plug-in interface are Ethernet interfaces.

9. The integrated entertainment content management device of claim 1, wherein, The third plug-in interface, the fourth plug-in interface, the fifth plug-in interface and the sixth plug-in interface are USB interfaces.

10. The integrated entertainment content management device of claim 1, wherein, The subboard card is further integrated with a battery pack which is connected with the fourth processing chip and is used for supplying power to the fourth processing chip.

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