Semiconductor device

Abstract

A semiconductor device includes a substrate. An oxide semiconductor channel layer is over the substrate. A gate structure is over the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer over an oxide semiconductor channel layer, a gate dielectric layer over the oxide semiconductor barrier layer, and a gate metal over the gate dielectric layer. The source / drain electrode is in contact with both ends of the oxide semiconductor channel layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to several generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advancements have increased the complexity of handling and manufacturing ICs. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process usually provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to shrink, manufacturing processes become increasingly difficult to execute. Therefore, forming reliable semiconductor devices in ever-smaller sizes remains a challenge. Utility Model Content

[0003] In some embodiments of this disclosure, the semiconductor device includes a substrate. An oxide semiconductor channel layer is located above the substrate. A gate structure is located above the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer above the oxide semiconductor channel layer, a gate dielectric layer above the oxide semiconductor barrier layer, and a gate metal layer above the gate dielectric layer. Source / drain electrodes are in contact with both ends of the oxide semiconductor channel layer.

[0004] In some embodiments of this disclosure, the semiconductor device includes a substrate. A semiconductor channel layer is located above the substrate. A gate structure is located above the semiconductor channel layer. The gate structure includes a semiconductor barrier layer surrounding the semiconductor channel layer, a gate dielectric layer located above the semiconductor barrier layer, and a gate metal located above the gate dielectric layer. Source / drain electrodes are in contact with both ends of the semiconductor channel layer.

[0005] In some embodiments of this disclosure, the semiconductor device includes a substrate. An oxide semiconductor channel layer is located above the substrate. A gate structure is located above the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer above the oxide semiconductor channel layer, a gate dielectric layer above the oxide semiconductor barrier layer, and a gate metal layer above the gate dielectric layer. A plurality of spacers are located at both ends of the gate structure, wherein the oxide semiconductor barrier layer contacts the spacers. Source / drain electrodes are in contact with both ends of the oxide semiconductor channel layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1A to 15C This describes a method for forming a semiconductor device at various stages according to some embodiments of the present disclosure;

[0008] Figure 16 This describes simulation results of a semiconductor device according to some embodiments of this disclosure;

[0009] Figure 17 This invention describes a method for forming a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 18 A cross-sectional view illustrating some embodiments of an integrated circuit according to this disclosure.

[0011] [Symbol Explanation]

[0012] 100:Substrate

[0013] 102: Channel material layer

[0014] 102CH: Channel Area

[0015] 102SD: Source / Drain Region

[0016] 104: Sacrifice Layer

[0017] 110: Gate structure

[0018] 111: Barrier Layer

[0019] 112: Gate dielectric layer

[0020] 114: First gate metal

[0021] 116: Second gate metal

[0022] 120: Conductive layer

[0023] 122: Source / Drain Electrode

[0024] 124: Gate electrode

[0025] 200: Plasma Chamber

[0026] 210: Gas Source

[0027] 220: Plasma generation area

[0028] 230: RF power supply

[0029] 240: Ion filter

[0030] 250: Reaction Chamber

[0031] 300:Substrate

[0032] 305: Isolation Structure

[0033] 310: Semiconductor Fin

[0034] 320: Gate structure

[0035] 322: Gate dielectric layer

[0036] 324: Work function metal layer

[0037] 326: Filler metal

[0038] 330: Gate spacer

[0039] 340: Source / Drain Region

[0040] 350: Interlayer dielectric layer

[0041] 360: Source / Drain Contacts

[0042] 370: Intermetallic dielectric layer

[0043] 372: Conductive via

[0044] 374: Conductive circuit

[0045] 380: Conductive via

[0046] Ec: Conductor band

[0047] Ev: Price band

[0048] G1: Gas

[0049] IC: Integrated Circuit

[0050] IO: Ion Plasma

[0051] MA1, MA2, MA3, MA4: Patterned Mask

[0052] O1, O2, O3: Opening

[0053] RD: Free Radical Plasma

[0054] ST1: Stacking

[0055] T1, T2: Semiconductor devices Detailed Implementation

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0057] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature and another illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. As used herein, “left or right,” “about,” “approximately,” or “substantially” can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms “left or right,” “about,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0058] Gate all-around (GAA) transistor structures can be patterned using any suitable method. For example, one or more lithography processes can be used to pattern the structure, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography with self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those obtained using a single direct lithography process. For example, in some embodiments, a sacrificial layer formed over a substrate is patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0059] Figures 1A to 15C This description illustrates methods for forming a semiconductor device at various stages according to some embodiments of the present disclosure. More specifically, Figures 1A to 15A This is a top view of a semiconductor device. Figures 1B to 15B respectively along Figures 1A to 15A A sectional view of line BB. Figures 1C to 15C respectively along Figures 1A to 15A A sectional view of line CC. Although Figures 1C to 15C The description is a series of behaviors, but it should be understood that these behaviors are not limited, as the order of the behaviors may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some behaviors described and / or illustrated may be omitted in whole or in part. Although the embodiments of this disclosure are discussed with regard to gate all-around (GAA) transistors, the embodiments of this disclosure can also be applied to nanosheet transistors, nanowire transistors, dendritic FETs, forked transistors, etc.

[0060] See Figure 1A , Figure 1B and Figure 1C The figure shows substrate 100. Typically, substrate 100 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x Semiconductor materials may be assimilated or undoped, and may include oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.). Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0061] The substrate 100 may also include a front-end-of-line (FEOL) structure, a middle-end-of-line (MEOL) structure above the FEOL structure, and a back-end-of-line (BEOL) structure above the MEOL structure. FEOL typically includes processes associated with manufacturing an IC device (such as a transistor). For example, an FEOL process may include the steps of forming isolation features, gate structures, and source and drain features (typically referred to as source / drain features). MEOL typically includes processes associated with the fabrication of contacts for conductive features (or conductive regions) of the IC device, such as contacts for gate structures and / or source / drain features. BEOL typically includes processes associated with the fabrication of interconnect structures that interconnect IC features fabricated by the FEOL process (referred to herein as FEOL features or structures) and the MEOL process (referred to herein as MEOL features or structures) to enable the IC device to operate. For example, a BEOL process may include the steps of forming multilayer interconnect features to facilitate the operation of the IC device. In some embodiments, via Figures 1A to 15C The resulting structure (e.g.) Figures 15A to 15C The semiconductor device T1 can be formed in the BEOL structure.

[0062] A stack ST1 is formed on substrate 100. The stack ST1 includes alternating channel material layers 102 and sacrificial layers 104. The channel material layers 102 and sacrificial layers 104 can be formed using deposition processes such as atomic layer deposition (ALD), sputtering, plasma-enhanced chemical vapor deposition (PECVD), epitaxial growth, or other suitable deposition processes. In some embodiments, a portion of the sacrificial layer 104 can be removed during the gate formation process, and a portion of the sacrificial layer 104 can be removed during the source / drain contact formation process. In some embodiments, each channel material layer 102 may include a channel region 102CH and source / drain regions 102SD located on opposite sides of the channel region 102CH. Here, the channel region 102CH may be a portion of the channel material layer 102 that is adjacent to the gate structure (e.g., Figures 10A to 10C The overlapping portion of the gate structure 110 in the channel material layer 102. The source / drain region 102SD can be the portion of the channel material layer 102 located on opposite sides of the channel region 102CH that does not overlap with the gate structure.

[0063] In some embodiments, the channel material layer 102 may include a semiconductor material, such as an oxide semiconductor material. Examples of oxide semiconductor materials include indium gallium zinc oxide (IGZO) and indium oxide (InO).x Zinc oxide (ZnO), indium gallium oxide (IGO), and indium zinc oxide (IZO) are all acceptable materials. Channel material layer 102 may also include indium tin oxide (InSnO), tungsten-doped indium oxide (InWO), and gallium oxide (GaO). x In other embodiments, the channel material layer 102 may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), etc. In some embodiments, the thickness of each channel material layer 102 is in the range of about 1 nm to about 1000 nm. The channel material layer 102 may be formed using suitable deposition processes, such as atomic layer deposition (ALD), sputtering, plasma-enhanced chemical vapor deposition (PECVD), epitaxial deposition, or other suitable deposition processes. In some embodiments, the channel material layer 102 may include an amorphous structure.

[0064] The sacrificial layer 104 may comprise a different material from the channel material layer 102 to provide sufficient etch selectivity. In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the sacrificial layer 104 may comprise a dielectric material such as silicon nitride (SiN) or silicon oxide (SiO2). x In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the sacrificial layer 104 may also include a conductive material, such as titanium nitride (TiN), tungsten (W), titanium (Ti), etc. In some embodiments, the thickness of each sacrificial layer 104 is in the range of about 1 nm to about 1000 nm. The sacrificial layer 104 may be formed using a suitable deposition process, such as atomic layer deposition (ALD), sputtering, plasma-enhanced chemical vapor deposition (PECVD), epitaxial deposition, or other suitable deposition processes.

[0065] See Figure 2A , Figure 2B and Figure 2C A patterned mask MA1 is formed on substrate 100. The patterned mask MA1 may include openings that expose portions of the stack ST1, which will be removed in the next step (see [link to documentation]). Figures 3A to 3C In some embodiments, the patterned mask MA1 may include a photoresist or a rigid mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0066] See Figure 3A , Figure 3B and Figure 3CThe portion of the stack ST1 exposed via the opening of the patterned mask MA1 is removed. A removal process is performed to define the width of the channel region 102CH of the channel material layer 102 along a first direction (e.g., the Y direction). In some embodiments, a suitable etching process, such as wet etching, dry etching, or a combination thereof, may be used to remove the portion of the stack ST1. After the etching process is complete, the patterned mask MA1 may be removed.

[0067] See Figure 4A , Figure 4B and Figure 4C An etching process is performed to remove a portion of the sacrificial layer 104. Therefore, the channel region 102CH of the channel material layer 102 is suspended above the substrate 100. On the other hand, after the etching process is completed, a portion of the sacrificial layer 104 located between adjacent source / drain regions 102SD of the channel material layer 102 can be retained because these portions are protected by the source / drain regions 102SD of the channel material layer 102, which have a larger area. In some embodiments, the topmost sacrificial layer 104 is removed in the etching process. In some embodiments, the etching process may include wet etching, dry etching, or a combination thereof. This process may also be referred to as a "channel release process".

[0068] After the channel release process is completed, an oxygen removal process can be performed on the source / drain region 102SD of the channel material layer 102 to increase the dopant concentration in the source / drain region 102SD of the channel material layer 102. More specifically, the oxygen removal process is performed to reduce the oxygen atom concentration in the source / drain region 102SD of the channel material layer 102, thereby creating oxygen vacancies in the source / drain region 102SD of the channel material layer 102. In some embodiments, oxygen vacancies can also be considered as dopants in the source / drain region 102SD of the channel material layer 102. In some embodiments, the dopant concentration in the source / drain region 102SD of the channel material layer 102 is higher than the dopant concentration in the channel region 102CH of the channel material layer 102. That is, the oxygen vacancy concentration in the source / drain region 102SD of the channel material layer 102 is higher than the oxygen vacancy concentration in the channel region 102CH of the channel material layer 102. In other words, the oxygen concentration in the source / drain region 102SD of the channel material layer 102 is lower than the oxygen concentration in the channel region 102CH of the channel material layer 102. In some embodiments, the doped source / drain region 102SD of the channel material layer 102 may be referred to as an n-type doped region.

[0069] In some embodiments where the channel material layer 102 comprises an oxide semiconductor material, a deoxygenation process can be used to form source / drain doped regions in the source / drain regions 102SD of the channel material layer 102. The deoxygenation process can be performed using the remainder of the sacrificial layer 104 as a deoxygenation layer. For example, the sacrificial layer 104 may comprise a material having a stronger oxygen affinity than the channel material layer 102 (e.g., TiN, Ti-containing materials, etc.). The deoxygenation process can be performed by an annealing process at a temperature ranging from about 25°C to about 500°C. During the annealing process, oxygen atoms in the source / drain regions 102SD of the channel material layer 102 can be attracted by the remainder of the sacrificial layer 104, allowing oxygen atoms in the source / drain regions 102SD of the channel material layer 102 to diffuse into the sacrificial layer 104, thereby leaving oxygen vacancies in the source / drain regions 102SD of the channel material layer 102. On the other hand, since part of the sacrificial layer 104 is removed from the channel region 102CH of the channel material layer 102, oxygen vacancies may not form in the channel region 102CH of the channel material layer 102. That is, the channel region 102CH of the channel material layer 102 may be left undoped due to the annealing process. In some embodiments, this can be omitted. Figures 4A to 4C The deoxygenation process discussed in the article.

[0070] See Figure 5A , Figure 5B and Figure 5C A barrier layer 111 is deposited on the substrate 100 and surrounds each channel region 102CH of the channel material layer 102. For example... Figure 6B As shown in the cross-sectional view, the barrier layer 111 can contact at least four sides of each channel region 102CH of the channel material layer 102. Figure 6C As shown in the cross-sectional view, the barrier layer 111 may contact the sacrificial layer 104, and the barrier layer 111 may also include at least one portion having a rectangular annular cross-sectional profile. In some embodiments, a portion of the barrier layer 111 contacts the top surface of the substrate 100.

[0071] The barrier layer 111 may include a semiconductor material, such as an oxide semiconductor material. Examples of oxide semiconductor materials include indium gallium zinc oxide (IGZO) and indium oxide (InO). xThe materials used include zinc oxide (ZnO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), and indium gallium tin oxide (IGTO). As mentioned above, the channel material layer 102 can also be made of an oxide semiconductor material. The difference between the barrier layer 111 and the channel material layer 102 is that the oxide semiconductor material of the barrier layer 111 is selected to have a higher conduction band value (Ec) than the oxide semiconductor material of the channel material layer 102. This can be achieved by changing the combination of indium (In), zinc (Zn), tin (Sn), gallium (Ga), and oxide (O) in the barrier layer 111, such that at least one of indium (In), zinc (Zn), tin (Sn), gallium (Ga), and oxide (O) in the barrier layer 111 has a different concentration than that in the channel material layer 102. The difference in conduction band value will lead to carrier accumulation at the interface between the oxide semiconductor barrier layer 111 and the oxide semiconductor channel material layer 102 during operation, which will... Figure 16 This will be discussed in more detail below. The accumulated carriers will increase the carrier mobility of the oxide semiconductor channel material layer 102, and will further increase the carrier mobility of the semiconductor device (e.g., Figures 15A to 15C The conduction current (I) of the semiconductor device T1 in the middle ON However, if the barrier layer 111 is omitted, the gate dielectric layer 112 will be in direct contact with the oxide semiconductor channel material layer 102. Due to the poor interface between the gate dielectric layer and the oxide semiconductor channel material layer, the high trap density at the interface leads to Coulomb scattering and surface roughness scattering, which degrades device performance. In this disclosure, the better interface quality between the barrier layer 111 and the channel material layer 102 results in a reduction of Coulomb scattering and surface roughness scattering. It should be noted that the barrier layer separates the traps in the gate dielectric layer 112 from the conduction electrons in the channel material layer 102 to reduce Coulomb scattering. Therefore, device performance can be improved.

[0072] In some embodiments, the barrier layer 111 and the channel material layer 102 may comprise the same material (e.g., having the same elements) but differ in composition. For example, the barrier layer 111 and the channel material layer 102 may comprise indium gallium zinc oxide (IGZO). However, the oxygen (O) concentration of the barrier layer 111 is higher than that of the channel material layer 102. This is because a higher oxygen concentration increases the conduction band value of IGZO, making it a suitable material for the barrier layer 111.

[0073] In other embodiments, the barrier layer 111 and the channel material layer 102 may comprise different materials. For example, the barrier layer 111 may be made of indium gallium zinc oxide (IGZO), and the channel material layer 102 may comprise indium zinc oxide (IZO). In other words, the gallium (Ga) concentration of the barrier layer 111 is higher than that of the channel material layer 102. This is because a higher gallium concentration will increase the conduction band value of IGZO, making it a suitable material for the barrier layer 111. The channel material layer 102 may also comprise indium gallium zinc oxide (IGZO), but with a lower gallium concentration than that of the indium gallium zinc oxide (IGZO) of the barrier layer 111.

[0074] In other embodiments, the channel material layer 102 may be made of indium oxide (In2O3), while the barrier layer 111 may be made of indium gallium zinc oxide (IGZO). That is, the barrier layer 111 may include a higher gallium concentration and / or zinc concentration than the channel material layer 102. This is because the doping of zinc and gallium into In2O3 leads to an increase in the band gap (and conduction band value).

[0075] In some embodiments, the barrier layer 111 is deposited using a conformal deposition process, such as ALD, CVD, etc. In some embodiments, the thickness of the barrier layer 111 is in the range of about 1 nm to about 1000 nm. If the barrier layer 111 is too thin (e.g., much less than 1 nm), current leakage may occur as carriers tunnel from the channel material layer 102 to the barrier layer 111. If the barrier layer 111 is too thick (e.g., much greater than 1000 nm), there is no significant improvement to the device. In some embodiments, the barrier layer 111 is thinner than each channel material layer 102.

[0076] See Figure 6A , Figure 6B and Figure 6C A gate dielectric layer 112 is deposited on the substrate 100 and covers the barrier layer 111. In some embodiments, the gate dielectric layer 112 is deposited using a conformal deposition process, such as ALD, CVD, etc. In some embodiments, the thickness of the gate dielectric layer 112 is in the range of about 1 nm to about 1000 nm.

[0077] In some embodiments, the gate dielectric layer 112 may be made of a high-k dielectric material. Examples of high-k dielectric materials include alumina (Al₂O₃), hafnium oxide (HfO₂), titanium oxide (TiO₂), zirconium oxide (ZrO₂), other suitable high-k dielectric materials, and / or combinations thereof. In other embodiments, the gate dielectric layer 112 may be made of a ferroelectric (FE) material. Examples of ferroelectric material layers may be or include hafnium zirconium oxide (HfZrO), alumina hafnium oxide (HfAlO), zirconium oxide (ZrO), hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), gadolinium (Gd), aluminum (Al), etc., undoped hafnium oxide (HfO), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or combinations thereof.

[0078] See Figure 7A , Figure 7B and Figure 7C A first gate metal 114 is deposited on the substrate 100 and covers the gate dielectric layer 112. For example... Figure 7B As shown in the cross-sectional view, a first gate metal 114 may be deposited in the space between two adjacent channel material layers 102. Similarly, the first gate metal 114 may surround each channel region 102CH of the channel material layer 102. In some embodiments, the first gate metal 114 may include titanium nitride (TiN), aluminum (Al), titanium (Ti), etc. In some embodiments, the first gate metal 114 is deposited using a conformal deposition process, such as ALD, CVD, etc. In some embodiments, the thickness of the first gate metal 114 is in the range of about 1 nm to about 1000 nm.

[0079] See Figure 8A , Figure 8B and Figure 8CA second gate metal 116 is deposited on the substrate 100 and covers the first gate metal 114. The gate dielectric layer 112, the first gate metal 114, and the second gate metal 116 can be collectively referred to as the gate structure 110. In some embodiments, the second gate metal 116 may include titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), nickel (Ni), etc. In some embodiments, the first gate metal 114 and the second gate metal 116 may include different materials to achieve the desired work function value. In other embodiments, the first gate metal 114 and the second gate metal 116 may include the same material, but the first gate metal 114 and the second gate metal 116 may be deposited using different deposition processes. For example, the first gate metal 114 may be deposited using a conformal deposition process, such as ALD, CVD, etc. The second gate metal 116 may be deposited using ALD, CVD, or sputtering. In some embodiments, the deposition process of the first gate metal 114 is performed such that the first gate metal 114 surrounds the channel material layer 102. A deposition process for the second gate metal 116 is performed to achieve the desired gate metal thickness. In some embodiments, the thickness of the second gate metal 116 is in the range of about 1 nm to about 1000 nm.

[0080] See Figure 9A , Figure 9B and Figure 9C A patterned mask MA2 is formed on the substrate 100. More specifically, as... Figure 9C As shown, the patterned mask MA2 overlaps with the channel region 102CH of the channel material layer 102 in the vertical direction. The patterned mask MA3 may include openings that expose the stacked portion ST1. Specifically, in Figure 9C In this embodiment, the opening of the patterned mask MA3 may overlap with the source / drain region 102SD of the channel material layer 102 in the vertical direction. In some embodiments, the patterned mask MA2 may include a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0081] See Figure 10A , Figure 10B and Figure 10C The portion of gate structure 110 that overlaps with the source / drain region 102SD of channel material layer 102 is removed. More specifically, the portions of barrier layer 111, gate dielectric layer 112, first gate metal 114, and second gate metal 116 that overlap with the source / drain region 102SD of channel material layer 102 are removed. Thus, the remaining portion of gate structure 110 overlaps with and surrounds each channel region 102CH of channel material layer 102. In some embodiments, portions of gate structure 110 may be removed using a suitable etching process, such as wet etching, dry etching, or a combination thereof. After the etching process is complete, the topmost channel material layer 102 is exposed.

[0082] See Figure 11A , Figure 11B and Figure 11C A patterned mask MA3 is formed on the substrate 100. More specifically, as... Figure 11C As shown, the patterned mask MA3 may include an opening O1 in the exposed portion of the stacked ST1. Specifically, in Figure 11C In this embodiment, the opening O1 of the patterned mask MA3 may overlap with the source / drain region 102SD of the channel material layer 102 in the vertical direction. In some embodiments, the patterned mask MA3 may include a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0083] See Figure 12A , Figure 12B and Figure 12C An etching process is performed using a patterned mask MA3 as an etching mask to remove portions of the channel material layer 102 and sacrificial layer 104 exposed by the opening O1. Thus, a source / drain opening O2 is formed in the stack ST1. In some embodiments, the etching process may include wet etching, dry etching, or a combination thereof. Figure 12C As shown, after the etching process is completed, a portion of the sacrificial layer 104 remains on the opposite sidewalls of the gate structure 110. The remaining portion of the sacrificial layer 104 can serve as an internal spacer, and may also be referred to as internal spacer 104 in the following description.

[0084] See Figure 13A , Figure 13B and Figure 13C Remove the patterned mask MA3. Then, deposit a conductive layer 120 on the substrate 100, filling the source / drain openings O2 in the stack ST1. More specifically, a portion of the conductive layer 120 in the source / drain openings O2 contacts the internal spacer 104 and the source / drain region 102SD of the channel material layer 102. The conductive layer 120 also includes a portion of the pad sidewalls and top surface of the gate structure 110. In some embodiments, the conductive layer 120 may include titanium nitride (TiN), aluminum (Al), titanium (Ti), etc. In some embodiments, the conductive layer 120 may be formed using conformal deposition processes such as ALD, CVD, etc. In some embodiments, the thickness of the conductive layer 120 is in the range of about 1 nm to about 1000 nm.

[0085] As mentioned above, such as Figures 4A to 4C The deoxygenation process discussed can be omitted. Instead, the deoxygenation process can be performed after the conductive layer 120 is formed. A deoxygenation process is performed on the source / drain regions 102SD of the channel material layer 102 to increase the dopant concentration in the source / drain regions 102SD of the channel material layer 102. It should be noted that in Figure 13CIn this embodiment, the source / drain region 102SD of the channel material layer 102 can be the portion of the channel material layer 102 that vertically overlaps with the internal spacer 104. More specifically, a deoxygenation process is performed to reduce the oxygen atom concentration in the source / drain region 102SD of the channel material layer 102, thereby creating oxygen vacancies within the source / drain region 102SD of the channel material layer 102. In some embodiments, oxygen vacancies can also be considered as dopants in the source / drain region 102SD of the channel material layer 102.

[0086] In some embodiments where the channel material layer 102 comprises an oxide semiconductor material, a deoxygenation process can be used to form source / drain doped regions in the source / drain regions 102SD of the channel material layer 102. The deoxygenation process can be performed using the source / drain electrodes 122 as a deoxygenation layer. For example, the conductive layer 120 may comprise a material with a higher and stronger oxygen affinity than the channel material layer 102 (e.g., TiN, Ti-containing materials, etc.). During the annealing process, oxygen atoms in the source / drain regions 102SD of the channel material layer 102 can be attracted by the conductive layer 120, allowing oxygen atoms in the source / drain regions 102SD of the channel material layer 102 to diffuse into the conductive layer 120, thereby leaving oxygen vacancies in the source / drain regions 102SD of the channel material layer 102.

[0087] See Figure 14A , Figure 14B and Figure 14C A patterned mask MA4 is formed on the substrate 100. More specifically, as... Figure 14C As shown, the patterned mask MA4 may include openings O3 exposing portions of the conductive layer 120. Specifically, in Figure 14C In this embodiment, the opening O3 of the patterned mask MA4 may overlap with the internal spacer 104 in the vertical direction. In some embodiments, the patterned mask MA4 may include a photoresist or a rigid mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0088] See Figure 15A , Figure 15B and Figure 15C An etching process is performed to remove a portion of the conductive layer 120 exposed by the opening O3 of the patterned mask MA4. After the etching process is completed, the patterned mask MA4 is removed. Therefore, the portion of the conductive layer 120 that contacts the source / drain region 102SD of the channel material layer 102 is called the source / drain electrode 122, and the portion of the conductive layer 120 that contacts the gate structure 110 is called the gate electrode 124, wherein the source / drain electrode 122 and the gate electrode 124 are physically spaced apart from each other.

[0089] Then, a semiconductor device T1 is formed. The semiconductor device T1 may include a channel material layer 102, a gate structure 110 surrounding a channel region 102CH of each channel material layer 102, source / drain electrodes 122 contacting the source / drain regions 102SD of each channel material layer 102, and a gate electrode 124 contacting the gate structure 110. In some embodiments, the semiconductor device T1 may be a field-effect transistor (FET). In some embodiments where the gate dielectric layer 112 of the gate structure 110 is made of a ferroelectric material, the semiconductor device T1 may be a ferroelectric field-effect transistor (FeFET).

[0090] Figure 16 Simulation results of a semiconductor device according to some embodiments of this disclosure are presented. Figure 16 The bottom shows a strip diagram of the barrier layer 111 and the channel material layer 102, in which a suitable gate voltage (V) is applied. GS ) and drain voltage (V DS It should be noted that Ec represents the conduction band, and Ev represents the valence band. It can be seen that a conduction band discontinuity occurs at the interface between the barrier layer 111 and the channel material layer 102, and electrons can accumulate in a localized low-energy region near the interface. Figure 16 As can also be seen at the top, near the interface between the barrier layer 111 and the channel material layer 102, electrons can include a higher density. As described above, the accumulated electrons will increase the carrier mobility of the oxide semiconductor channel material layer 102, and will further increase the semiconductor device (e.g., Figures 15A to 15C The conduction current (I) of the semiconductor device T1 in the middle ON This is because the improved interface quality between the barrier layer 111 and the channel material layer 102 leads to a reduction in Coulomb scattering and surface roughness scattering. Therefore, the device performance can be improved.

[0091] Figure 17 This description illustrates methods for forming semiconductor devices according to some embodiments of the present disclosure. More specifically, Figure 17 This describes the use of highly selective isotropic dry etching (HiSIDE) in the source / drain regions 102SD of the channel material layer 102 via an opening O2 (see [link]). Figure 12C The formation of doped regions may be omitted in these embodiments. Figures 1A to 15C The deoxygenation process discussed in the article.

[0092] In the HiSIDE method, remove Figures 12A to 12CA patterned mask MA3 is formed, and a substrate 100, including structures formed thereon, is transferred into a plasma chamber 200. The plasma chamber 200 includes a gas source 210, a plasma generation region 220 in gas communication with the gas source 210, a radio frequency (RF) power supply 230 adjacent to the plasma generation region 220, an ion filter 240 located below the plasma generation region 220, and a reaction chamber 250 located below the ion filter 240. The substrate 100 is transferred to the reaction chamber 250 and supported by a substrate stage.

[0093] In the doping process, gas G1 is supplied to the plasma generation region 220. Simultaneously, an RF power supply 230 is turned on, thereby generating ion plasma IO and radical plasma RD. In some embodiments, gas G1 may be a fluorine-containing (F) gas, such as nitrogen fluoride (NF3). The RF power supply 230 is used to generate fluoride ion plasma (F... - ) and fluorine radical plasma (F * On the other hand, gas G1 can be a hydrogen-containing gas (H), such as hydrogen gas (H2). RF power supply 230 is used to generate hydrogen ion plasma (H2). + ) and hydrogen radical plasma (H * Here, the term "ion" can refer to an atom or molecule with a net charge. On the other hand, the term "free radical" can refer to an atom or molecule with a neutral charge.

[0094] In the doping process, an ion filter 240 is used to prevent certain types of ions from entering the reaction chamber 250 from the plasma generation region 220. The blocking is selective, depending on the ion type. The ion filter 240 can be operated via an electric or magnetic field. In some embodiments, the ion filter 240 includes a DC power supply with a variable voltage. For example, when the ion plasma IO and the radical plasma RD are respectively fluoride ion plasma (F... - ) and fluorine radical plasma (F * When the ion filter 240 is in operation, it can generate a positive electric field to attract fluoride ion plasma (F). - This prevents the attraction of fluoride ion plasma (F...). - ) enters the reaction chamber at 250. On the other hand, neutral fluorine radical plasma (F * It can enter reaction chamber 250. In some embodiments, when the ion plasma IO and the free radical plasma RD are hydrogen ion plasmas (H... + ) and hydrogen radical plasma (H * When the ion filter 240 is in operation, it can generate a negative electric field to attract hydrogen ion plasma (H). + This prevents the attraction of hydrogen ion plasma (H) + ) enters the reaction chamber at 250°C. On the other hand, neutral hydrogen radical plasma (H... *It can enter the reaction chamber 250.

[0095] As shown in the figure, the source / drain regions 102SD of the channel material layer 102 are exposed to the free radical plasma RD entering the reaction chamber 250. In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the free radical plasma RD may serve as a donor for the source / drain regions 102SD of the channel material layer 102. For example, when the free radical plasma RD includes fluorine free radical plasma (F... * When the source / drain region 102SD of the channel material layer 102 is doped with fluorine, the fluorine atom concentration in the source / drain region 102SD of the channel material layer 102 can be higher than the fluorine atom concentration in the channel region 102CH of the channel material layer 102. On the other hand, when the radical plasma RD includes hydrogen radical plasma (H... * When the source / drain region 102SD of the channel material layer 102 is doped with hydrogen, the hydrogen atom concentration of the source / drain region 102SD of the channel material layer 102 can be higher than the hydrogen atom concentration of the channel region 102CH of the channel material layer 102.

[0096] Figure 18 This illustration shows a cross-sectional view of an integrated circuit according to some embodiments of this disclosure. The figure shows an integrated circuit (IC). It should be noted that... Figure 18 Some components and Figures 1A to 15C The components described are similar, and for the sake of brevity, the relevant details will not be repeated.

[0097] The integrated circuit IC includes a substrate 300. Typically, substrate 300 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include silicon, a crystalline semiconductor material, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x Semiconductor materials may be assimilated or undoped, and may include oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.). Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0098] The integrated circuit IC also includes semiconductor fins 310 protruding from the top surface of the substrate 300. In some embodiments, the semiconductor fins 310 are made of the same material as the substrate 300, or may include a different material than the substrate 300.

[0099] An isolation structure 305, such as a shallow trench isolation structure (STI), is disposed on the substrate 300 and laterally surrounds the semiconductor fin 310. In some embodiments, the isolation structure 305 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof.

[0100] Gate structures 320 are formed on respective semiconductor fins 310. Each gate structure 320 may include a gate dielectric layer 322, a work function metal layer 324 on the gate dielectric layer 322, and a fill metal 326 on the work function metal layer 324.

[0101] In some embodiments, the gate dielectric layer 322 may include an interface layer and a high-k dielectric layer located on the interface layer. The interface layer may be made of oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), etc. The high-k dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof.

[0102] The work function metal layer 324 can be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. The filler metal 326 may include tungsten (W), aluminum (Al), copper (Cu), or other suitable conductive materials.

[0103] Gate spacers 330 are formed on opposite sidewalls of each gate structure 320. In some embodiments, gate spacers 330 may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or combinations thereof.

[0104] Source / drain regions 340 are formed above semiconductor fins 310 and on opposite sides of each gate structure 320. In some embodiments, source / drain regions 340 may include heavily doped regions and relatively lightly doped drain extensions, or LDD regions. For example, source / drain regions 340 can be formed by implanting dopants (e.g., As, P, B, In, etc.) using an ion implantation process.

[0105] The source / drain region 340 may include an epitaxial growth region. For example, a groove may first be formed therein in the semiconductor fin 310, and a crystalline semiconductor material may be deposited in the groove using a selective epitaxial growt (SEG) process. The crystalline semiconductor material may be an element (e.g., Si, or Ge, etc.) or an alloy (e.g., Si...). 1-x C x Si 1-x Ge x High doses of dopant can be introduced in situ into the source / drain region 340 during SEG, or via ion implantation after SEG, or a combination thereof.

[0106] An interlayer dielectric layer 350 is formed on substrate 300, covering source / drain regions 340 and laterally surrounding gate structure 320. In some embodiments, the interlayer dielectric layer 350 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicate glass (FSG), doped silicon carbon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide.

[0107] Source / drain contacts 360 may be formed in the interlayer dielectric layer 350 and electrically connected to the corresponding source / drain regions 340. Source / drain contacts 360 may include a conductive pad and a contact plug located on the conductive pad. In some embodiments, the conductive pad may include Ti, Ni, Pt, Co, TiN, TaN, Ta, or other suitable metals. The contact plug may include tungsten (W) or other suitable conductive materials, such as Al, Cu, Ru, Ni, Co, these alloys, or combinations thereof.

[0108] Semiconductor fin 310, gate structure 320 located above semiconductor fin 310, and source / drain region 340 can be used together as semiconductor device T2, such as transistor. Semiconductor device T2, interlayer dielectric layer 350, and source / drain contacts 360 can be collectively referred to as front-end-of-line (FEOL) structure.

[0109] The integrated circuit (IC) further includes an interconnect structure. The interconnect structure may include multiple metallization layers stacked on top of each other. In some embodiments, each metallization layer may include an inter-metal dielectric layer 370. Conductive vias 372 and conductive lines 374 are disposed in the inter-metal dielectric layer 370.

[0110] like Figures 1A to 15C The semiconductor device T1 under discussion may be formed on an inter-metal dielectric layer 370. Another inter-metal dielectric layer 370 may be formed to cover the semiconductor device T1. Conductive vias 380 are formed in the inter-metal dielectric layer 370 and electrically connected to the semiconductor device T1. The interconnect structure and the semiconductor device T1 may be referred to as a back-end-of-line (BEOL) structure. In some embodiments, the semiconductor device T1 at the BEOL structure may be electrically connected to the semiconductor device T2 at the FEOL structure via an interconnect structure.

[0111] As can be seen from the foregoing embodiments, the present disclosure has advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor are the specific advantages of all embodiments required. Embodiments of the present disclosure provide a semiconductor device by forming an oxide semiconductor barrier layer on an oxide semiconductor channel layer. During operation of the semiconductor device, carrier accumulation occurs at the interface between the oxide semiconductor barrier layer and the oxide semiconductor channel layer. The accumulated carriers increase the carrier mobility of the oxide semiconductor channel layer and further increase the on-current (I0) of the semiconductor device. ON A better interface quality between the oxide semiconductor barrier layer and the oxide semiconductor channel layer will reduce Coulomb scattering and surface roughness scattering. Therefore, device performance can be improved.

[0112] In some embodiments of this disclosure, the semiconductor device includes a substrate. An oxide semiconductor channel layer is located above the substrate. A gate structure is located above the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer above the oxide semiconductor channel layer, a gate dielectric layer above the oxide semiconductor barrier layer, and a gate metal layer above the gate dielectric layer. Source / drain electrodes are in contact with both ends of the oxide semiconductor channel layer.

[0113] In some embodiments, the oxide semiconductor channel layer and the oxide semiconductor barrier layer differ in composition.

[0114] In some embodiments, the material of the oxide semiconductor barrier layer has a higher conduction band value than the material of the oxide semiconductor channel layer.

[0115] In some embodiments, in a cross-sectional view, an oxide semiconductor barrier layer surrounds an oxide semiconductor channel layer.

[0116] In some embodiments, the semiconductor device further includes spacers located at both ends of the gate structure, wherein the oxide semiconductor barrier layer is in contact with the spacers.

[0117] In some embodiments, the oxide semiconductor channel layer and the oxide semiconductor barrier layer are made of indium gallium zinc oxide (IGZO), and the oxygen concentration of the oxide semiconductor barrier layer is higher than that of the oxide semiconductor channel layer.

[0118] In some embodiments, the oxide semiconductor barrier layer is made of indium gallium zinc oxide (IGZO), and the oxide semiconductor channel layer is made of indium zinc oxide (IZO).

[0119] In some embodiments of this disclosure, the semiconductor device includes a substrate. A semiconductor channel layer is located above the substrate. A gate structure is located above the semiconductor channel layer. The gate structure includes a semiconductor barrier layer surrounding the semiconductor channel layer, a gate dielectric layer located above the semiconductor barrier layer, and a gate metal located above the gate dielectric layer. The material of the semiconductor barrier layer has a higher conduction band value than the material of the semiconductor channel layer. Source / drain electrodes are in contact with both ends of the semiconductor channel layer.

[0120] In some embodiments, the semiconductor barrier layer is made of a first oxide semiconductor material.

[0121] In some embodiments, the semiconductor channel layer is made of a second oxide semiconductor material.

[0122] In some embodiments, the gate dielectric layer is made of a high-k dielectric material.

[0123] In some embodiments, the gate dielectric layer is made of a ferroelectric material.

[0124] In some embodiments, the semiconductor channel layer is thicker than the semiconductor barrier layer.

[0125] In some embodiments, the semiconductor barrier layer has a higher oxygen concentration than the semiconductor channel layer.

[0126] In some embodiments, the semiconductor barrier layer has a higher germanium concentration than the semiconductor channel layer.

[0127] In some embodiments of this disclosure, a method includes the following steps: forming an alternating stack of oxide semiconductor channel layers and sacrificial layers on a substrate; removing a portion of the sacrificial layer such that the channel regions of the oxide semiconductor channel layers are suspended on the substrate; forming an oxide semiconductor barrier layer surrounding the channel regions of the oxide semiconductor channel layers; forming a gate dielectric layer on the oxide semiconductor barrier layer; and forming a gate metal on the gate dielectric layer.

[0128] In some embodiments, the oxide semiconductor channel layer and the oxide semiconductor barrier layer differ in composition.

[0129] In some embodiments, the material of the oxide semiconductor barrier layer has a higher conduction band value than the material of the oxide semiconductor channel layer.

[0130] In some embodiments, the oxide semiconductor barrier layer extends to the top surface of the substrate.

[0131] In some embodiments, the method further includes the step of forming source / drain electrodes at both ends of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the remainder of the sacrificial layer.

[0132] In some embodiments of this disclosure, the semiconductor device includes a substrate. An oxide semiconductor channel layer is located above the substrate. A gate structure is located above the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer above the oxide semiconductor channel layer, a gate dielectric layer above the oxide semiconductor barrier layer, and a gate metal layer above the gate dielectric layer. A plurality of spacers are located at both ends of the gate structure, wherein the oxide semiconductor barrier layer contacts the spacers. Source / drain electrodes are in contact with both ends of the oxide semiconductor channel layer.

[0133] In some embodiments, the oxide semiconductor channel layer is thicker than the oxide semiconductor barrier layer.

[0134] In some embodiments, an oxide semiconductor barrier layer surrounds an oxide semiconductor channel layer.

[0135] In some embodiments, the oxide semiconductor barrier layer contacts the oxide semiconductor channel layer.

[0136] In some embodiments, the oxide semiconductor channel layer is in contact with the spacer.

[0137] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: A substrate; An oxide semiconductor channel layer over the substrate; A gate structure over the oxide semiconductor channel layer and comprising: An oxide semiconductor barrier layer over the oxide semiconductor channel layer; A gate dielectric layer over the oxide semiconductor barrier layer; and A gate metal over the gate dielectric layer; and Source / drain electrodes in contact with both ends of the oxide semiconductor channel layer. Wherein in a cross-sectional view, the oxide semiconductor barrier layer surrounds the oxide semiconductor channel layer. Further comprising spacers at both ends of the gate structure, wherein the oxide semiconductor barrier layer is in contact with the spacers. A substrate; 2. The semiconductor device according to claim 1, wherein A semiconductor channel layer over the substrate; 3. The semiconductor device according to claim 1, wherein A gate structure over the semiconductor channel layer and comprising:

4. A semiconductor device, characterized by comprising: A semiconductor barrier layer surrounding the semiconductor channel layer; A gate dielectric layer over the semiconductor barrier layer; and A gate metal over the gate dielectric layer; and Source / drain electrodes in contact with both ends of the semiconductor channel layer. Wherein the semiconductor channel layer is thicker than the semiconductor barrier layer. A substrate; An oxide semiconductor channel layer over the substrate; A gate structure over the oxide semiconductor channel layer and comprising:

5. The semiconductor device according to claim 4, wherein An oxide semiconductor barrier layer over the oxide semiconductor channel layer; 6. A semiconductor device, characterized by comprising: A gate dielectric layer over the oxide semiconductor barrier layer; and A gate metal over the gate dielectric layer; and Spacers at both ends of the gate structure, wherein the oxide semiconductor barrier layer is in contact with the spacers; And source / drain electrodes in contact with both ends of the oxide semiconductor channel layer. Wherein the oxide semiconductor channel layer is thicker than the oxide semiconductor barrier layer. Wherein the oxide semiconductor barrier layer surrounds the oxide semiconductor channel layer. Wherein the oxide semiconductor barrier layer is in contact with the oxide semiconductor channel layer. Wherein the oxide semiconductor channel layer is in contact with the spacers. ​ ​ ​ ​ 7. The semiconductor device according to claim 6, wherein ​ 8. The semiconductor device according to claim 6, wherein ​ 9. The semiconductor device according to claim 6, wherein ​ 10. The semiconductor device according to claim 6, wherein ​

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