Frequency divider, multimode frequency divider, phase-locked loop circuit, chip and electronic equipment

Abstract

The utility model provides a frequency divider, a multimode frequency divider, a phase-locked loop circuit, a chip and electronic equipment. The frequency divider comprises a first latch, a second latch, a third latch and a fourth latch which are in feedback cascade connection, the first AND logic circuit is respectively connected with the first latch, the second latch and the fourth latch; the second AND logic is connected between the second latch and the third latch; the third AND logic circuit is connected between the third latch and the fourth latch; and a delay circuit connected with the output end of the second latch, wherein the frequency divider generates an output frequency-divided clock signal through the delay circuit. According to the scheme of the invention, the structure of the frequency divider is optimized, so that the output delay time of the first-stage frequency division module in the multi-modulus frequency divider during signal output is improved, the situation that the signals are sampled by mistake in the subsequent sampling and frequency division process of the frequency division modules is avoided, and the problem that the frequency division ratio is wrong under continuous frequency division change is solved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a frequency divider, a multi-mode frequency divider, a phase-locked loop circuit, a chip, and electronic equipment. Background Technology

[0002] Frequency dividers are one of the core modules of wired and wireless transceivers, widely used in high-speed communications and circuits. Their main function is to generate an output signal from an input signal according to a specific frequency division ratio. A multi-modulus divider (MMD) is a programmable frequency divider that can be programmed to obtain various division ratios, thereby generating output signals of multiple frequencies. Frequency dividers, or multi-modulus dividers (MMDs), are an important component of fractional phase-locked loops (PLLs). They can convert high-frequency signals into low-frequency signals at a specific ratio, for example, by being used in the feedback branch of a PLL to complete channel switching.

[0003] Most multimode frequency dividers currently use cascaded 2 / 3 divider modules. As a result, the duty cycle of the output frequency divider clock signal is poor at different levels. When continuously changing the frequency division ratio, the frequency division ratio is prone to error. This will lead to an error in the frequency of the final phase-locked loop output clock signal and thus fail to lock. Utility Model Content

[0004] To address the aforementioned technical problems, this application provides a frequency divider, a multi-mode frequency divider, a phase-locked loop circuit, a chip, and an electronic device, aiming to solve the problem of errors in the frequency division result after continuous changes in the division ratio in a multi-mode frequency divider circuit.

[0005] According to a first aspect of this application, a frequency divider is provided, comprising:

[0006] The first latch has a clock input terminal that receives the input clock signal and a data input terminal that is connected to the output terminal of the first AND logic circuit.

[0007] The second latch has a clock input terminal that receives an input clock signal, a data input terminal that is connected to the non-inverting output terminal of the first latch, an inverting output terminal that is connected to the first input terminal of the first AND logic circuit, a non-inverting output terminal that is connected to the first input terminal of the second AND logic circuit, and a second input terminal of the second AND logic circuit that receives a mode input signal.

[0008] The third latch has a clock input terminal that receives an input clock signal, a data input terminal that is connected to the output terminal of the second AND logic circuit, a non-inverting output terminal that is connected to the first input terminal of the third AND logic circuit, and a second input terminal of the third AND logic circuit that receives a frequency division selection signal.

[0009] The fourth latch has a clock input terminal that receives an input clock signal, a data input terminal that is connected to the output terminal of the third AND logic circuit, and a non-inverting output terminal that is connected to the second input terminal of the first AND logic circuit.

[0010] The delay circuit has its input terminal connected to the output terminal of the second latch, and its output terminal generates an output frequency-divided clock signal.

[0011] Optionally, the delay circuit includes an inverter, the input of which is connected to the non-inverting output of the second latch, and the output of which generates the output frequency-divided clock signal.

[0012] Optionally, the frequency divider includes:

[0013] The frequency divider input terminal is connected to the clock input terminals of the first latch, the second latch, the third latch, and the fourth latch;

[0014] The frequency divider output terminal is connected to the output terminal of the delay circuit.

[0015] The mode input terminal is connected to the second input terminal of the second AND logic circuit.

[0016] The mode output terminal is connected to the non-inverting output terminal of the third latch;

[0017] The frequency divider selection terminal is connected to the second input terminal of the third AND logic circuit.

[0018] Optionally, the first latch and the third latch are clock rising edge sampling latches, and the second latch and the fourth latch are clock falling edge sampling latches.

[0019] According to a second aspect of this application, a multimode frequency divider is provided, comprising: n cascaded frequency divider modules, wherein the first-stage frequency divider module employs a frequency divider as disclosed in any embodiment of this application, and n is an integer greater than or equal to 4.

[0020] Optionally, each of the cascaded n frequency divider modules, excluding the first-stage frequency divider module, includes:

[0021] The fifth latch receives the input clock signal at its clock input terminal and its data input terminal is connected to the output terminal of the fourth AND logic circuit.

[0022] The sixth latch receives an input clock signal at its clock input terminal, and its data input terminal is connected to the non-inverting output terminal of the fifth latch. The inverting output terminal of the sixth latch is connected to the first input terminal of the fourth AND logic circuit, and simultaneously generates an output frequency-divided clock signal. The non-inverting output terminal of the sixth latch is connected to the first input terminal of the fifth AND logic circuit, and the second input terminal of the fifth AND logic circuit receives a mode input signal.

[0023] The seventh latch has a clock input terminal that receives an input clock signal, a data input terminal that is connected to the output terminal of the fifth AND logic circuit, a non-inverting output terminal that is connected to the first input terminal of the sixth AND logic circuit, and a second input terminal of the sixth AND logic circuit that receives a frequency division selection signal.

[0024] The eighth latch receives the input clock signal at its clock input terminal, and its data input terminal is connected to the output terminal of the sixth AND logic circuit. The non-inverting output terminal of the eighth latch is connected to the second input terminal of the fourth AND logic circuit.

[0025] Optionally, each of the cascaded n frequency divider modules, excluding the first-stage frequency divider module, includes:

[0026] The frequency divider input terminal is connected to the clock input terminals of the fifth latch, the sixth latch, the seventh latch, and the eighth latch;

[0027] The frequency divider output terminal is connected to the inverting output terminal of the sixth latch.

[0028] The mode input terminal is connected to the second input terminal of the fifth AND logic circuit;

[0029] The mode output terminal is connected to the non-inverting output terminal of the seventh latch;

[0030] The frequency divider selection terminal is connected to the second input terminal of the sixth AND logic circuit.

[0031] Optionally, the multi-mode divider further includes:

[0032] The output frequency divider signal selection module receives the mode output signal and selection signal from the third and fourth frequency divider modules in the cascaded n frequency divider modules respectively, and outputs the first clock signal;

[0033] The frequency division ratio adjustment logic module receives the first clock signal, the frequency division control signal, and the set signal, respectively, and outputs the frequency division selection signal to the frequency division selection terminal of each of the cascaded n frequency division modules. The frequency division control signal is a digital signal with n bits, corresponding to the n cascaded frequency division modules.

[0034] Optionally, the output frequency division signal selection module includes:

[0035] A 2-to-1 selector has its first input connected to the mode output of the third-level frequency divider in a cascade of n frequency divider modules, its second input connected to the mode output of the fourth-level frequency divider in a cascade of n frequency divider modules, its selection control terminal receiving a selection signal, and its output terminal generating the first clock signal.

[0036] The logic circuit has a first input terminal that receives the digital signal of the nth bit in the frequency division control signal, a second input terminal that receives the digital signal of the (n-1)th bit in the frequency division control signal, and an output terminal that outputs the selection signal.

[0037] Optionally, the frequency division ratio adjustment logic module includes:

[0038] The D flip-flop has its clock input connected to the output of the output frequency divider signal selection module, and its data input receives the frequency divider control signal.

[0039] The logic circuit has a first input terminal that receives the set signal, a second input terminal that is connected to the output terminal of the D flip-flop, and an output terminal that is connected to the frequency selection terminal of each of the n frequency divider modules.

[0040] According to a third aspect of this application, a phase-locked loop circuit is provided, comprising: a multi-mode divider as described in any embodiment of this application.

[0041] According to a fourth aspect of this application, a chip is provided, comprising one of the following:

[0042] Frequency divider as described in any embodiment of this application;

[0043] The multimode frequency divider as described in any embodiment of this application;

[0044] Phase-locked loop circuits as described in any embodiment of this application.

[0045] According to a fifth aspect of this application, an electronic device is provided, comprising one of the following:

[0046] Frequency divider as described in any embodiment of this application;

[0047] The multimode frequency divider as described in any embodiment of this application;

[0048] The phase-locked loop circuit as described in any embodiment of this application;

[0049] The chip as described in any embodiment of this application.

[0050] The beneficial effects of this application include at least the following:

[0051] This application embodiment utilizes a feedback-cascaded first latch, second latch, third latch, and fourth latch, as well as a first AND logic circuit, a second AND logic circuit, and a third AND logic circuit to design a frequency divider capable of 2 / 3 frequency division. A delay circuit connected to the output of the second latch is incorporated into this frequency divider to generate an output divided clock signal. Therefore, this frequency divider can improve its output delay time when outputting signals, ensuring that the rising edges of the output divided clock signal and the mode output signal are located within different high and low levels of the input clock.

[0052] Furthermore, by applying the frequency divider provided in this embodiment as the first-stage frequency divider module in a multi-mode frequency divider, the load capacity of the output frequency-divided clock signal of the first-stage frequency divider module in the multi-mode frequency divider can be increased, the delay time of the output frequency-divided clock signal can be reduced, and the latch in the subsequent frequency divider module can be sampled at the correct rising edge of the clock. Compared with the traditional multi-mode frequency divider, which is prone to frequency ratio errors when the frequency ratio changes continuously under different process angles and frequencies, the solution of this application can ensure that the frequency ratio of the multi-mode frequency divider will not be wrong when it changes continuously.

[0053] In a further preferred embodiment, the present application adds an output frequency division signal selection module to the output selection of the frequency division selection signal. This module can select the mode output signal of the third-level frequency division module or the mode output signal of the fourth-level frequency division module for different frequency division ratios, ensuring that the output signal of the multi-mode frequency divider has a good duty cycle, which is beneficial to improving the overall performance of the phase-locked loop.

[0054] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0055] Figure 1 This diagram shows a structural block diagram of a phase-locked loop circuit provided according to an embodiment of this application;

[0056] Figure 2 This diagram illustrates the structure of a multimode frequency divider in related technologies.

[0057] Figure 3 This diagram illustrates an embodiment of a multimode frequency divider provided according to an embodiment of this application.

[0058] Figure 4 Show Figure 3 A schematic diagram of an embodiment of each frequency divider module except for the first-stage frequency divider module;

[0059] Figure 5 Show Figure 3A schematic diagram of an embodiment of the first-stage frequency divider module;

[0060] Figure 6 The diagram shows a timing waveform of a portion of the signals of a frequency divider provided according to an embodiment of this application. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0062] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0063] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0064] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0065] Figure 1 A structural block diagram of the phase-locked loop circuit provided in an embodiment of this application is shown, as follows: Figure 1 As shown, the phase-locked loop circuit includes: a phase-frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LPF) 130, a voltage-controlled oscillator (VCO) 140, and a multi-mode divider (MMD) 150. The PFD 110 compares the phase difference between the reference frequency ref_clk and the output feedback frequency of the divider. The charge pump 120 and loop filter 130 convert the phase difference generated by the PFD 110 into a control voltage for the VCO 140. The VCO 140 outputs the required frequency based on the control voltage. The MMD 150 generates a feedback frequency based on the output frequency of the VCO 140 and compares it with the reference frequency ref_clk.

[0066] Figure 2 A schematic diagram of the structure of a multimode frequency divider in related technologies is shown, such as... Figure 2As shown, in the related technology, the multi-mode frequency divider is composed of multiple 2 / 3 frequency divider modules cascaded together. From left to right, they are the first-stage 2 / 3 frequency divider module (also referred to as the frequency divider module in this article) 211 to the nth-stage 2 / 3 frequency divider module 21n, where n is an integer greater than 1. Each 2 / 3 frequency divider module (also referred to as the frequency divider module in this article) includes a frequency divider input terminal fi, a frequency divider output terminal fo, a mode input terminal Mi, a mode output terminal Mo, and a frequency divider selection terminal P. The frequency divider input terminal fi of the first-stage frequency divider module 211 receives the initial signal f(in). The frequency divider input terminal fi of each subsequent frequency divider module is connected to the frequency divider output terminal fo of the previous frequency divider module, thereby generating the first down-frequency signal f(out) at the frequency divider output terminal fo of the nth-stage frequency divider module 21n. The frequency divider selection terminals P of the first-stage to the nth-stage frequency divider modules respectively receive frequency divider selection signals P[1] to P[n]. The mode input terminal Mi of the nth-stage frequency divider module 21n receives a high-level signal H to ensure the implementation of the 3-division function. The mode input terminal Mi of each frequency divider module before the nth-stage frequency divider module 21n is connected to the mode output terminal Mo of the next-stage frequency divider module, thereby generating the second down-frequency signal m(out) at the mode output terminal Mo of the first-stage frequency divider module 211.

[0067] Figure 2 In this multimode divider, the division ratio can be achieved as follows: Based on this structure, different logic combinations are used to control the input signals of the frequency selection terminal P of the subsequent frequency divider modules. This allows for different frequency division ratios, generating clock signals with different frequency division ratios. The frequency division ratio range that this multi-mode frequency divider can generate is as follows: k represents the number of bits in the multimode divider that are not involved in the division ratio programming.

[0068] Since most multi-mode frequency dividers currently use cascaded 2 / 3 divider modules, the duty cycle of the output frequency divider clock signals of different levels is poor. When continuously changing the frequency division ratio, the frequency division ratio is prone to error, which will lead to the final phase-locked loop output clock signal frequency error and thus fail to achieve locking.

[0069] Furthermore, in existing multi-mode frequency dividers, the output clock signal of the first-stage frequency divider module is sent to the next-stage frequency divider module and also serves as the feedback signal in the current-stage frequency divider module. This results in a large delay in the output clock signal of the first-stage frequency divider module, which can cause the latch in the next-stage frequency divider module to miss the correct flip edge when sampling the clock based on the output clock signal. Consequently, when two consecutive frequency divider modules are cascaded, the four-way frequency division function cannot be achieved, and the entire multi-mode frequency divider cannot achieve even-number frequency division. This leads to an error in the output clock frequency of the VCO in the phase-locked loop, and ultimately, the phase-locked loop cannot lock.

[0070] Based on this, the proposed solution further optimizes the structure of the frequency divider and the multi-mode frequency divider, thereby improving the output delay time of the first-stage frequency divider module in the multi-mode frequency divider when outputting the signal. This ensures that the signal will not be missampled during the sampling and frequency division process of subsequent frequency divider modules, solving the problem that the frequency division ratio is prone to error under continuously changing conditions. (Reference) Figure 3 , Figure 3 A schematic diagram of an embodiment of the multimode divider provided in this application is shown. It should be noted that the multimode divider disclosed in this application can be applied to, for example... Figure 1 The phase-locked loop circuit shown can also be applied to any other phase-locked loop architecture that includes a multi-mode divider.

[0071] like Figure 3 As shown in the embodiment of this application, the multi-mode frequency divider includes n cascaded frequency divider modules. From left to right, the n cascaded frequency divider modules are the first-stage frequency divider module 311 to the nth-stage frequency divider module 31n, where n is an integer greater than or equal to 4. Each frequency divider module is, for example, a 2 / 3 frequency divider module, and each frequency divider module includes a frequency divider input terminal fi, a frequency divider output terminal fo, a mode input terminal Mi, a mode output terminal Mo, and a frequency divider selection terminal P. In this document, the frequency divider module is also referred to as a frequency divider.

[0072] In this embodiment, each of the cascaded n frequency divider modules includes a frequency divider input terminal fi, a frequency divider output terminal fo, a mode input terminal Mi, a mode output terminal Mo, and a frequency divider selection terminal P. The frequency divider input terminal fi of the first-stage frequency divider module 311 receives the initial clock input signal f(in). The frequency divider input terminal fi of each subsequent frequency divider module 311 is connected to the frequency divider output terminal fo of its preceding module, thereby generating a first down-frequency signal f(out) at the frequency divider output terminal fo of the nth-stage frequency divider module 31n. The frequency divider selection terminals P of the first to nth-stage frequency divider modules respectively receive frequency divider selection signals P[1] to P[n]. The mode input terminal Mi of the nth-stage frequency divider module 31n receives a high-level signal H to ensure the implementation of the 3-stage frequency divider function. The mode input terminal Mi of each frequency divider module before the nth-stage frequency divider module 31n is connected to the mode output terminal Mo of the next stage frequency divider module, thereby generating the second down-frequency signal m(out) at the mode output terminal Mo of the first-stage frequency divider module 311.

[0073] Optionally, the frequency selection terminal P of each frequency division module in the multi-mode frequency divider provided in this application embodiment can be connected to the logic control circuit of the multi-mode frequency divider so that the logic circuit can configure the frequency selection terminal P of each distribution module; or, the frequency selection terminal P of each frequency division module can also be directly used as an external terminal and configured manually. Specifically, the multi-mode frequency divider can configure the frequency selection terminal P of each frequency division module according to the desired frequency division ratio to determine the number of frequency division modules participating in the frequency division and the frequency division ratio of each frequency division module, thereby realizing the desired frequency division of the clock input signal f(in).

[0074] When this multi-mode frequency divider is working, each stage of the frequency divider module can achieve a 2-way or 3-way frequency divider mode under the control of the signals received at the frequency divider selection terminal P and the mode input terminal Mi. For example, when the signal at the frequency divider selection terminal P is low, the frequency divider module acts as a 2-way frequency divider circuit. When the signal at the frequency divider selection terminal P is high, the frequency division ratio of the frequency divider module is determined by the signal at the mode input terminal Mi. When the signal at the mode input terminal Mi is low, the frequency divider module acts as a 2-way frequency divider circuit. When the signal at the mode input terminal Mi is high, the frequency divider module acts as a 3-way frequency divider circuit. Therefore, by setting the frequency divider selection signal P[n:1] of the multi-mode frequency divider, the input clock signal f(in) can be down-divided by different frequency division ratios, and the multi-mode frequency divider can achieve a continuously variable frequency division ratio under the control of the frequency divider selection signal P[n:1].

[0075] like Figure 5 As shown, in the cascaded n frequency divider modules, the first-stage frequency divider module 311 includes: feedback-cascaded latches 501, 502, 503, and 504, AND logic circuits 505, 506, and 507, and a delay circuit. In this embodiment, latches 501 and 503 are clock rising-edge sampling latches, and latches 502 and 504 are clock falling-edge sampling latches, wherein the clock rising-edge sampling latches and the clock falling-edge sampling latches are cross-cascaded.

[0076] Combination Figure 3 and Figure 5In this embodiment, the clock input terminals CLK of latches 501, 502, 503, and 504 are all connected to the frequency divider input terminal fi of the first-stage frequency divider module 311 to receive the input clock signal f(in). The data input terminal D of latch 501 is connected to the output terminal of logic circuit 505. The data input terminal D of latch 502 is connected to the non-inverting output terminal Q of latch 501. The inverting output terminal Qb of latch 502 is connected to the first input terminal of logic circuit 505. The non-inverting output terminal Q of latch 502 is connected to the first input terminal of logic circuit 506. The second input terminal of logic circuit 506 is connected to the mode input terminal Mi of the first-stage frequency divider module 311 to receive the mode input signal m(1). The data input terminal D of latch 503 is connected to the output terminal of logic circuit 506. The non-inverting output terminal Q of latch 503 is connected to the first input terminal of logic circuit 507. At the same time, the first input terminal of logic circuit 507 is also connected to the mode output terminal Mo of the first-stage frequency divider module 311 to generate the mode output signal (i.e. the second down-frequency signal mentioned above) m(out). The second input terminal of logic circuit 507 is connected to the frequency division selection terminal P of the first-stage frequency divider module 311 to receive the frequency division selection signal P[1]. The data input terminal D of latch 504 is connected to the output terminal of logic circuit 507. The non-inverting output terminal Q of latch 504 is connected to the second input terminal of logic circuit 505. The input terminal of delay circuit is connected to the output terminal of latch 502. The output terminal of delay circuit is connected to the frequency division output terminal fo of the first-stage frequency divider module 311 to generate the output frequency division clock signal f(1).

[0077] exist Figure 5 In the example shown, the delay circuit includes an inverter 508, whose input is connected to the non-inverting output Q of a latch 502, and whose output is connected to the frequency division output fo of the first-stage frequency divider module 311 to generate an output frequency-divided clock signal f(1). Optionally, in some other embodiments, multiple cascaded inverters can be used in the delay circuit to adjust the delay time of the output frequency-divided clock signal f(1). When multiple inverters are required, the number of inverters is odd, and the input of the first-stage inverter in the cascaded odd number of inverters is connected to the non-inverting input Q of the latch 502. By setting the delay circuit, the load capacity of the output frequency-divided clock signal f(1) can be adjusted, thereby adjusting its rise and fall times and delay time, which helps to ensure that the next-stage frequency divider module can perform correct sampling and frequency division.

[0078] like Figure 4As shown, in the cascaded n frequency divider modules, each frequency divider module except for the first-stage frequency divider module 311 includes: feedback cascaded latches 401, 402, 403, and 404, and AND logic circuits 405, 406, and 407. In this embodiment, latches 401 and 403 are clock rising edge sampling latches, and latches 402 and 404 are clock falling edge sampling latches, wherein the clock rising edge sampling latches and the clock falling edge sampling latches are cross-cascaded.

[0079] Combination Figure 3 and Figure 4 In this embodiment, the clock input terminals CLK of latches 401, 402, 403, and 404 are all connected to the frequency division input terminal fi of the corresponding frequency division module to receive the input clock signal, i.e., the output frequency division clock signal of the previous stage frequency division module. The data input terminal D of latch 401 is connected to the output terminal of logic circuit 405. The data input terminal D of latch 402 is connected to the non-inverting output terminal Q of latch 401. The inverting output terminal Qb of latch 402 is connected to the first input terminal of logic circuit 405. At the same time, the inverting output terminal Qb of latch 402 is also connected to the frequency division output terminal fo of the corresponding frequency division module to generate the corresponding output frequency division clock signal. The non-inverting output terminal Q of latch 402 is connected to the first input terminal of logic circuit 406. The second input terminal of logic circuit 406 is connected to the mode input terminal Mi of the corresponding frequency divider module to receive the corresponding mode input signal. The data input terminal D of latch 403 is connected to the output terminal of logic circuit 406. The non-inverting output terminal Q of latch 403 is connected to the first input terminal of logic circuit 407. At the same time, the first input terminal of logic circuit 407 is also connected to the mode output terminal Mo of the corresponding frequency divider module to generate the corresponding mode output signal. The second input terminal of logic circuit 407 is connected to the frequency division selection terminal P of the corresponding frequency divider module to receive the corresponding frequency division selection signal. The data input terminal D of latch 404 is connected to the output terminal of logic circuit 407. The non-inverting output terminal Q of latch 404 is connected to the second input terminal of logic circuit 405.

[0080] It is understood that in this embodiment, an inverter 508 is added to the non-inverting output terminal Q of the clock rising edge sampling latch 502 in the first-stage frequency divider module 311. The output signal of the inverter 508 is used as the input clock signal to the next-stage frequency divider module 312, while the inverting output terminal Qb of the latch 502 is only used as the internal feedback signal of the first-stage frequency divider module 311. In this way, the signal output waiting time of the frequency divider output terminal fo of the frequency divider module 311 can be reduced, thereby improving the output delay time when it outputs the signal, and realizing that the rising edges of the output frequency divider clock signal f(1) and the mode output signal m(out) are located within different high and low levels of the input clock signal f(in). Figure 6 As shown, the rising edge of the output frequency divider clock signal f(1) of the frequency divider module 311 disclosed in this embodiment is located during the high level period of the input clock signal f(in), while the rising edge of the mode output signal m(out) of the frequency divider module 311 is located during the low level period of the input clock signal f(in).

[0081] Furthermore, in this embodiment, by simply adding a delay circuit to the first-stage frequency divider module 311, the output load capacity of the first-stage frequency divider module 311 can be increased, thereby reducing the delay time of the output frequency divider clock signal of the frequency divider module 311. This ensures that the latch in the subsequent frequency divider module can be sampled at the correct rising edge of the clock, and thus ensures that the division ratio of the multi-mode frequency divider will not err when it changes continuously.

[0082] It should be noted that the size of the inverter 508 added in the first-stage frequency divider module 311 should not be too large, otherwise it will cause the signal output waiting time of the non-inverting output terminal Q of the latch 502 to be too long, thereby causing the frequency division ratio of the frequency divider module 311 to be incorrect.

[0083] In some preferred embodiments, the multimode divider further includes an output divider signal selection module and a divider ratio adjustment logic module.

[0084] The output frequency division signal selection module receives the mode output signals and selection signals SEL from the third-level frequency division module 313 and the fourth-level frequency division module 314 in the cascaded n frequency division modules. Based on the selection signal SEL, it selects one of the mode output signals from the third-level frequency division module 312 and the fourth-level frequency division module 313 to output, and outputs the first clock signal CLK_OUT. In this embodiment, the first clock signal CLK_OUT serves as the final output clock signal after frequency division, and as the clock signal for sampling the input frequency division ratio selection digital signal.

[0085] The frequency division ratio adjustment logic module receives the first clock signal CLK_OUT and the frequency division control signal DIV, respectively. <n:1>And a set signal RS, outputting a frequency division selection signal P[n:1] to the frequency division selection terminal of each of the n cascaded frequency division modules to control the frequency division ratio of each module. The frequency division control signal DIV... <n:1>The input signal consists of n bits, which are digital signals input from the external frequency division control register and correspond to the n cascaded frequency division modules 311~31n. The set signal RS is used to control whether the n cascaded frequency division modules work or not. The frequency division selection signal P[n:1] includes multiple frequency division selection signals P[1]~P[n].

[0086] In specific implementation, Figure 3 In the example shown, the output frequency division signal selection module includes a 2-to-1 selector 320 and an AND logic circuit 350. The first input of the 2-to-1 selector 320 is connected to the mode output of the third-stage frequency divider module 313 in a cascaded network of n frequency divider modules. The second input of the 2-to-1 selector 320 is connected to the mode output of the fourth-stage frequency divider module (not shown) in a cascaded network of n frequency divider modules. The selection control terminal of the 2-to-1 selector 320 receives the selection signal SEL, and the output of the 2-to-1 selector 320 generates a first clock signal CLK_OUT. The first input of the AND logic circuit 350 receives the digital signal (denoted as DIV) of the nth bit in the frequency division control signal. <n>The second input terminal of logic circuit 350 receives the digital signal of the (n-1)th bit in the frequency division control signal (denoted as DIV). <n-1>The output of logic circuit 350 is the selection signal SEL.

[0087] The frequency division ratio adjustment logic module includes a D flip-flop (DFF) 330 and a logic circuit 340. The clock input of the D flip-flop 330 is connected to the output of the output frequency division signal selection module, and the data input of the D flip-flop 330 receives the frequency division control signal DIV. <n:1>The first input terminal of logic circuit 340 receives the set signal RS, the second input terminal of logic circuit 340 is connected to the output terminal of D flip-flop 330, and the output terminal of logic circuit 340 is connected to the frequency division selection terminal P of each of the n frequency division modules, and outputs the frequency division selection signal P[n:1].

[0088] In these embodiments, the output frequency division signal selection module uses the frequency division control signal DIV. <n:1>The digital signal DIV of the nth bit <n>and the digital signal DIV of the (n-1)th bit <n-1>The selection signal SEL generated after the AND logic operation selects the output signals at its input terminals, producing the first clock signal CLK_OUT. The frequency division control signal DIV... <n:1>After being input to the multi-mode frequency divider, it needs to be clock-aligned with the first clock signal CLK_OUT, which is equivalent to synchronizing with the output frequency divider clock signal. This ensures that the output of the multi-mode frequency divider will not be erroneous after the system is reset. The two inputs of the output frequency divider signal selection module are the mode output signal m(2) of the third-stage frequency divider module 313 and the mode output signal m(3) of the fourth-stage frequency divider module 314. This ensures both a good duty cycle and that the output frequency division will not be erroneous. In other words, the solution of this application adds an output frequency divider signal selection module to the final frequency divider output selection. It can select the mode output signal of the third-stage frequency divider module or the mode output signal of the fourth-stage frequency divider module for different frequency division ratios, ensuring that the output signal of the multi-mode frequency divider has a good duty cycle, which is beneficial to improving the overall performance of the phase-locked loop.

[0089] Furthermore, embodiments of this application also provide a chip that integrates one of the frequency divider, multi-mode frequency divider, and phase-locked loop circuit disclosed in any of the foregoing embodiments. Exemplarily, this chip includes, but is not limited to, digital signal processor (DSP) chips, communication chips, microcontroller (MCU) chips, field-programmable gate array (FPGA) chips, complex programmable logic device (CPLD) chips, etc.

[0090] Furthermore, embodiments of this application also provide an electronic device, which includes one of the frequency dividers, multi-mode frequency dividers, phase-locked loop circuits, and chips disclosed in any of the foregoing embodiments. Exemplary examples include, but are not limited to, smartphones, laptops, tablets, desktop computers, digital cameras, game consoles (such as PlayStation, Xbox, Nintendo Switch), televisions, wireless routers, Bluetooth headsets, smartwatches, drones, smart home devices (such as smart speakers, smart light bulbs, smart sockets), e-book readers, Bluetooth keyboards and mice, electronic blood pressure monitors, weighing scales, and other health devices.

[0091] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application. < / n> < / n>

Claims

1. A frequency divider, characterized by, The frequency divider comprises: a first latch, a clock input end of which receives an input clock signal, and a data input end of which is connected with an output end of a first AND logic circuit; a second latch, a clock input end of which receives the input clock signal, and a data input end of which is connected with a non-inverted output end of the first latch, an inverted output end of the second latch being connected with a first input end of the first AND logic circuit, a non-inverted output end of the second latch being connected with a first input end of a second AND logic circuit, and a second input end of the second AND logic circuit receiving a mode input signal; a third latch, a clock input end of which receives the input clock signal, and a data input end of which is connected with an output end of the second AND logic circuit, a non-inverted output end of the third latch being connected with a first input end of a third AND logic circuit, and a second input end of the third AND logic circuit receiving a frequency division selection signal; a fourth latch, a clock input end of which receives the input clock signal, and a data input end of which is connected with an output end of the third AND logic circuit, a non-inverted output end of the fourth latch being connected with a second input end of the first AND logic circuit; a delay circuit, an input end of which is connected with an output end of the second latch, and an output end of the delay circuit generating an output frequency division clock signal.

2. The frequency divider of claim 1, wherein, The delay circuit comprises an inverter, an input end of the inverter being connected with the non-inverted output end of the second latch, and an output end of the inverter generating the output frequency division clock signal.

3. The frequency divider of claim 1, wherein, The frequency divider comprises: a frequency division input end, connected with clock input ends of the first latch, the second latch, the third latch and the fourth latch; a frequency division output end, connected with an output end of the delay circuit; a mode input end, connected with the second input end of the second AND logic circuit; a mode output end, connected with the non-inverted output end of the third latch; a frequency division selection end, connected with the second input end of the third AND logic circuit.

4. The frequency divider of claim 1, wherein, The first latch and the third latch are clock rising edge sampling latches, and the second latch and the fourth latch are clock falling edge sampling latches.

5. A multi-modulus frequency divider, comprising: The frequency divider comprises: n frequency division modules connected in cascade, a first frequency division module of the n frequency division modules being the frequency divider according to any one of claims 1-4, and n being an integer greater than or equal to 4.

6. The multi-modulus frequency divider of claim 5, wherein, Each frequency division module of the n frequency division modules connected in cascade, except the first frequency division module, comprises: a fifth latch, a clock input end of which receives the input clock signal, and a data input end of which is connected with an output end of a fourth AND logic circuit; a sixth latch, a clock input end of which receives the input clock signal, and a data input end of which is connected with a non-inverted output end of the fifth latch, an inverted output end of the sixth latch being connected with a first input end of the fourth AND logic circuit, and simultaneously generating the output frequency division clock signal, a non-inverted output end of the sixth latch being connected with a first input end of a fifth AND logic circuit, and a second input end of the fifth AND logic circuit receiving the mode input signal; a seventh latch, a clock input end of the seventh latch receiving an input clock signal, a data input end of the seventh latch being connected with an output end of the fifth AND logic circuit, a non-inverted output end of the seventh latch being connected with a first input end of a sixth AND logic circuit, a second input end of the sixth AND logic circuit receiving a frequency division selection signal; an eighth latch, a clock input end of the eighth latch receiving the input clock signal, a data input end of the eighth latch being connected with an output end of the sixth AND logic circuit, a non-inverted output end of the eighth latch being connected with a second input end of the fourth AND logic circuit.

7. The multi-modulus frequency divider of claim 6 wherein, Each of the n frequency division modules in the cascade, except the first frequency division module, comprises: a frequency division input end connected with clock input ends of the fifth, sixth, seventh and eighth latches; a frequency division output end connected with an inverted output end of the sixth latch; a mode input end connected with a second input end of the fifth AND logic circuit; a mode output end connected with a non-inverted output end of the seventh latch; a frequency division selection end connected with a second input end of the sixth AND logic circuit.

8. The multi-modulus frequency divider of claim 5, wherein, The multi-mode frequency divider further comprises: an output frequency division signal selection module receiving a mode output signal of a third frequency division module and a mode output signal of a fourth frequency division module in the n frequency division modules in the cascade and a selection signal, and outputting a first clock signal; a frequency division ratio adjustment logic module receiving the first clock signal, a frequency division control signal and a set signal, and outputting a frequency division selection signal to the frequency division selection end of each of the n frequency division modules in the cascade, wherein the frequency division control signal is a digital signal with n bits, and corresponds to the n frequency division modules in the cascade respectively.

9. The multi-modulus frequency divider of claim 8, wherein, The output frequency division signal selection module comprises: a two-way selector, a first input end of the two-way selector being connected with a mode output end of the third frequency division module in the n frequency division modules in the cascade, a second input end of the two-way selector being connected with a mode output end of the fourth frequency division module in the n frequency division modules in the cascade, a selection control end of the two-way selector receiving the selection signal, and an output end of the two-way selector generating the first clock signal; an AND logic circuit, a first input end of the AND logic circuit receiving a digital signal of an n-th bit in the frequency division control signal, a second input end of the AND logic circuit receiving a digital signal of an n-1-th bit in the frequency division control signal, and an output end of the AND logic circuit outputting the selection signal.

10. The multi-modulus frequency divider of claim 8, wherein, The frequency division ratio adjustment logic module comprises: a D flip-flop, a clock input end of the D flip-flop being connected with an output end of the output frequency division signal selection module, and a data input end of the D flip-flop receiving the frequency division control signal; a logic circuit, a first input end of the logic circuit receiving the set signal, a second input end of the logic circuit being connected with an output end of the D flip-flop, and an output end of the logic circuit being connected with the frequency division selection end of each of the n frequency division modules.

11. A phase-locked loop circuit, characterized by comprising: It comprises: the multi-mode frequency divider according to any one of claims 5-10.

12. A chip, characterized by It comprises one of: the frequency divider according to any one of claims 1-4; the multi-mode frequency divider according to any one of claims 5-10; the phase-locked loop circuit according to claim 11.

13. An electronic device, comprising: It comprises one of: the frequency divider according to any one of claims 1-4; The multi-modulus divider as claimed in any one of claims 5-10; The phase-locked loop circuit as claimed in claim 11; The chip as claimed in claim 12.

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