Analog-to-digital converter and chip

Abstract

The utility model provides an analog-to-digital converter and a chip. The analog-to-digital converter comprises a sampling hold circuit, a comparison circuit, a digital-to-analog conversion circuit and a control logic circuit, wherein the digital-to-analog conversion circuit comprises a low-level resistance network and a high-level resistance network which are connected in series, the low-level resistance network is controlled by a logic value of low K bits in an N-bit digital signal, and K is an integer greater than zero and less than M; the high-level resistance network is controlled by a logic value of a high N-K bit in the N-bit digital signal, and the high N-K bit in the N-bit digital signal comprises a redundant bit. According to the scheme, the structure of the analog-to-digital converter is optimized, so that the analog-to-digital converter has the advantages of high speed, good monotonicity and small circuit area, and has certain error correction capability based on redundant bit setting.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to an analog-to-digital converter and chip. Background Technology

[0002] An analog-to-digital converter (ADC) is a circuit module that converts analog signals into digital signals, serving as a link between the analog and digital signal worlds. Currently, there are various types of ADC architectures, such as scintillation ADCs, pipelined ADCs, two-step ADCs, folded ADCs, Δ-Σ ADCs, Successive Approximation Register (SAR) ADCs, and hybrid ADC architectures proposed in recent years.

[0003] A typical SAR ADC consists of three parts: a comparator, a digital-to-analog converter (DAC), and control logic. It estimates the value of the analog signal using the DAC, thus converting the analog input into a digital output word. SAR ADCs offer advantages such as simple structure, small area, low power consumption, good adaptability to process variations, and easy integration. During several successive approximation cycles, a series of digital estimates are provided to the DAC input. Within each successive approximation cycle, the DAC output is compared with the analog input signal, and each comparison result is used to provide a closer estimate for the next estimation or successive approximation cycle. In many successive approximation ADCs, a binary search algorithm is used to perform analog-to-digital conversion so that each bit of the ADC output word corresponds to a specific estimation or successive approximation cycle.

[0004] A problem with the binary search algorithm of SAR ADCs is that once a search interval is excluded, that interval will not be searched again. This requires that every bit of the SAR ADC's judgment be accurate during operation; otherwise, the error caused by the incorrect bit cannot be compensated by subsequent bits, leading to a deterioration in ADC performance. Therefore, redundancy design is needed for error correction. Utility Model Content

[0005] To address the aforementioned technical problems, this application provides an analog-to-digital converter and chip, aiming to provide an analog-to-digital converter that combines high speed, good monotonicity, small circuit area, and error correction capability.

[0006] According to a first aspect of this application, an analog-to-digital converter is provided, comprising:

[0007] Sample and hold circuit, comparator circuit, digital-to-analog converter circuit, and control logic circuit;

[0008] The sample-and-hold circuit receives the input voltage and outputs a sampled voltage of the input voltage;

[0009] The input terminal of the digital-to-analog converter circuit receives an N-bit digital signal, and the output terminal is coupled to the second input terminal of the comparator circuit. The first input terminal of the comparator circuit is coupled to the output terminal of the sample-and-hold circuit.

[0010] The input terminal of the control logic circuit is coupled to the output terminal of the comparison circuit. The output terminal of the control logic circuit outputs an M-bit digital signal as the output signal of the analog-to-digital converter, and outputs an N-bit digital signal. The N-bit digital signal is a quantized signal of the M-bit digital signal and the redundant bit digital signal. N and M are both positive integers, and N is greater than M.

[0011] The digital-to-analog conversion circuit includes: a low-order resistor network and a high-order resistor network connected in series;

[0012] The low-order resistor network is controlled by the logic values ​​of the lower K bits in the N-bit digital signal, where K is an integer greater than zero and less than M.

[0013] The high-order resistor network is controlled by the logic value of the high NK bits in the N-bit digital signal, and the high NK bits in the N-bit digital signal include redundant bits.

[0014] Optionally, the redundant bits include the low NM bits in the high NK bits.

[0015] Optionally, the low-bit resistor network is a binary-weighted resistor network that performs binary weighting on the logic values ​​of the lower K bits in the N-bit digital signal.

[0016] Optionally, the total weight value of the low-side resistor network is equal to 1 / 2 raised to the power of MK.

[0017] Optionally, the low-side resistor network is an R-2R resistor network.

[0018] Optionally, the high-order resistor network is a non-binary weighted resistor network.

[0019] Optionally, the high-level resistor network is a thermometer code resistor network.

[0020] Optionally, the thermometer code resistor network includes NK groups of resistor-switch units connected in parallel, each controlled by the logic value of the high NK bits in the N-bit digital signal;

[0021] Each resistor-switch unit includes at least one unit resistor, with the first end of each unit resistor coupled to the output of the low-side resistor network and the second end of each unit resistor coupled to a reference voltage via a selector switch.

[0022] Optionally, the number of unit resistors in each resistor-switch unit is positively correlated with the weight value corresponding to that resistor-switch unit.

[0023] Optionally, in the high-order resistor network, the redundant bits include at least one low bit obtained by splitting at least one original high bit, and the weight value corresponding to each original high bit is a positive integer power of 2.

[0024] Optionally, in the high-weight resistor network, the redundant bits include at least one low bit obtained by splitting at least one original high bit and recombining multiple low-weight bits after splitting, and the weight value corresponding to each original high bit is a positive integer power of 2.

[0025] Optionally, in the high-order resistor network, a portion of the redundant bits includes at least one low bit obtained by splitting at least one original high bit, and another portion of the redundant bits includes at least one low bit obtained by splitting at least one original high bit and recombining the split multiple low-weight bits, wherein the weight value corresponding to each original high bit is a positive integer power of 2.

[0026] According to a second aspect of this application, a chip is provided, including an analog-to-digital converter as described in any embodiment of this application.

[0027] The beneficial effects of this application include at least the following:

[0028] The analog-to-digital converter and chip disclosed in this application utilize two series-connected resistor networks to construct the digital-to-analog conversion circuit in the analog-to-digital converter, and set redundant bits in the high-order resistor network, thereby optimizing the structure of the analog-to-digital converter. Compared with the analog-to-digital converter constructed using a capacitor array, the solution of this application enables the analog-to-digital converter to have a certain error correction capability, while operating faster, having better monotonicity, and having a smaller circuit area.

[0029] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0030] Figure 1 This diagram illustrates the structure of an analog-to-digital converter provided according to an embodiment of this application.

[0031] Figure 2 This diagram shows a schematic representation of the digital-to-analog converter circuit provided according to the first embodiment of this application.

[0032] Figure 3This diagram illustrates the structure of the high-order resistor network in the digital-to-analog converter circuit provided according to the first embodiment of this application.

[0033] Figure 4 This diagram illustrates the structure of the low-order resistor network in the digital-to-analog converter circuit provided according to the second embodiment of this application.

[0034] Figure 5 This diagram illustrates the structure of the high-order resistor network in the digital-to-analog converter circuit provided according to the second embodiment of this application.

[0035] Figure 6 A schematic diagram of the transfer function of a digital-to-analog converter circuit according to a second embodiment of this application is shown. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0037] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] In the description of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. "And / or" in this document describes a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. "Coupling" describes a connection relationship between related objects. For example, A and B are coupled, which can indicate a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0039] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0040] Figure 1 This application provides a block diagram illustrating the structure of an analog-to-digital converter according to an embodiment. Figure 1 As shown in the embodiments of this application, the analog-to-digital converter 100 includes: a sample-and-hold circuit 110, a comparator circuit 130, a digital-to-analog converter circuit 120, and a control logic circuit 140. The sample-and-hold circuit 110 receives an input voltage Vin and outputs a sampled voltage of the input voltage Vin. The input terminal of the digital-to-analog converter circuit 120 receives an N-bit digital signal D.<n-1,0> and reference voltage V H V L The output terminal is coupled to the second input terminal of the comparator circuit 130, and the first input terminal of the comparator circuit 130 is coupled to the output terminal of the sample-and-hold circuit 110; the input terminal of the control logic circuit 140 is coupled to the output terminal of the comparator circuit 130, and the output terminal of the control logic circuit 140 outputs an M-bit digital signal D.<m-1,0> As the output signal of the analog-to-digital converter 100, and as the output N-bit digital signal D<n-1,0> To the input terminal of the digital-to-analog converter circuit 120.

[0041] In this embodiment, the analog-to-digital converter 100 is a successive approximation analog-to-digital converter. During operation, the sample-and-hold circuit 110 samples the input voltage Vin to form a sample voltage of the input voltage Vin. Then, in a series of successive approximation cycles, the comparator circuit 130, the control logic circuit 140, and the digital-to-analog converter circuit 120 work together to cause the output voltage of the digital-to-analog converter circuit 120 to successively approximate the input voltage Vin.

[0042] In various implementations, in the first successive approximation loop, the control logic circuit 140 outputs the N-bit digital signal D.<n-1,0> Set to a predetermined state. In some implementations, an N-bit digital signal D is set.<n-1,0> Including the N-bit digital signal D<n-1,0> All bits are set to logic 0 or logic 1. Alternatively, the N-bit digital signal D can be...<n-1,0> The most significant bit D <n-1>Set to the first state (e.g., logic 1), and can convert the N-bit digital signal D<n-1,0> The remaining bits are set to a second state different from the first state (e.g., logic 0). In other implementations, depending on the specific implementation and its specifications, the N-bit digital signal D...<n-1,0> The initial state may differ from these examples. The digital-to-analog converter 120 operates based on the received reference voltage V. H V L The current N-bit digital signal D<n-1,0> The voltage is converted into a corresponding analog voltage and transmitted to the comparator circuit 130. The comparator circuit 130 compares the output voltage of the sample-and-hold circuit 102 with the output voltage of the analog-to-digital converter 100, outputs a corresponding indication signal, and transmits it to the control logic circuit 140 to indicate whether the first estimate provided by the digital-to-analog converter circuit 120 is less than or greater than the sampled voltage generated by the sample-and-hold circuit 110. The control logic circuit 140 adjusts the output N-bit digital signal D according to the comparison result of the comparator circuit 130 each time.<n-1,0> The output voltage of the digital-to-analog converter 120 is adjusted by at least one logic value until the output of the digital-to-analog converter 120 more accurately estimates the sampled input voltage.

[0043] In existing solutions, the digital-to-analog converter (DAC) circuit in an analog-to-digital converter (ADC) often uses a capacitor array. Larger capacitors can improve the matching degree of the capacitor array in the DAC, thereby improving the accuracy of the ADC. However, this also leads to problems such as excessive power consumption and increased chip area. Based on this, this application provides a new digital-to-analog conversion circuit, such as... Figure 2 and Figure 3 As shown, Figure 2 A schematic diagram of the digital-to-analog converter circuit provided in the first embodiment of this application is shown. Figure 3 A schematic diagram of the high-order resistor network in the digital-to-analog converter circuit provided in the first embodiment of this application is shown.

[0044] exist Figure 2 In the illustrated embodiment, the digital-to-analog converter circuit 120 includes a low-order resistor network 121 and a high-order resistor network 122 connected in series, wherein the low-order resistor network 121 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the lower K bits (denoted as D)<k-1,0> The high-order resistor network 122 is controlled by an N-bit digital signal D.<n-1,0> The logical value of the middle and high NK bits, where K is an integer greater than zero and less than N.

[0045] The low-order resistor network 121 is a resistor network capable of implementing binary weighting, based on the received reference voltage V. H V L For the logic value D of the lower K bits in an N-bit digital signal<k-1,0> Perform binary weighting. Figure 2 In the illustrated embodiment, the low-side resistor network 121 is an R-2R resistor network. For example... Figure 2 As shown, in this R-2R resistor network, the resistance values ​​are fixed at R and 2R. Except for the leftmost 2R resistor, each of the remaining 2R resistor branches has a selector switch S connected in series, each controlled by an N-bit digital signal D.<n-1,0> Each bit in the low-to-mid K-bit range (also referred to as bit in this article, including D) <0> D <1> ... D <k-2> 、D <k-1>The selector switch S is used to connect the corresponding 2R resistor branch to the reference voltage V according to the corresponding bit in the digital signal. H and reference voltage V L One of them, for example, when the value of this bit is logic 0, the corresponding selector switch S connects the 2R resistor to the reference voltage V. L When the value of this bit is logic 1, the corresponding selector switch S connects the 2R resistor to the reference voltage V. H Where R and 2R represent the resistance values, and in this paper, the resistor with a resistance value of R is referred to as the unit resistor. Theoretically, for every additional stage added to this R-2R resistor network, the N-bit digital signal D...<n-1,0> For low to medium K bits, the number of bits or digits will increase accordingly. For each additional bit of precision, only one resistor each for R and 2R (i.e., one resistor ladder) and a selection switch S need to be added. The area of ​​the R-2R resistor network will not increase exponentially with the increase of precision, thus greatly saving the number of resistors.

[0046] The high-level resistor network 122 is a thermometer-coded resistor network. In Figure 2 In the illustrated embodiment, the high-order resistor network 122 includes three resistor-switch units. Each resistor-switch unit includes a resistor connected in series between the output terminal Vout1 of the R-2R resistor network and the reference voltage input terminal, and a selection switch S. The selection switch S in the three resistor-switch units is controlled by an N-bit digital signal D.<n-1,0> The three high-order logic values ​​D <n-3> 、D <n-2> 、D <n-1>Among them, those controlled by D <n-3>The total resistance of the resistor-switching unit is R, controlled by D. <n-2>The total resistance of the resistor-switching unit is R / 2, controlled by D. <n-1>The total resistance of the resistor-switch unit is R / 4, and it can be used as follows: Figure 2 The single resistor method shown can be used, or it can be set as shown in the example. Figure 3 The multiple unit resistors R shown are connected in parallel. Of course, in some other embodiments, Figure 3 Each resistor-switch unit can use only one selector switch.

[0047] It is understandable that the low-order resistor network 121 adopts a binary trapezoidal structure, such as an R-2R resistor network, so that its overall equivalent output resistance is always R, which is the same as the resistance value of each resistor-switch unit in the high-order resistor network 122. Therefore, Figure 2 The digital-to-analog converter circuit 120 shown can be based on the reference voltage V H V L For N-bit digital signal D<n-1,0> A weighted transformation is performed to obtain the corresponding analog voltage Vout. Because... Figure 2 The digital-to-analog converter circuit 120 shown is constructed using a resistor array, therefore, compared to a capacitor array type digital-to-analog converter circuit, Figure 2 The digital-to-analog converter circuit 120 shown has a smaller circuit area and lower resistor matching requirements.

[0048] However, Figure 2 The digital-to-analog converter circuit 120 shown has no redundant bits (i.e., the N-bit digital signal D output by the control logic circuit 140 at this time)<n-1,0> That is, an M-bit digital signal D<m-1,0> The control logic circuit 140 lacks error correction capabilities for output codeword errors that occur during the comparison process. Based on this, this application further optimizes the structure of the digital-to-analog converter (DAC) 120 in the DAC 100, including adding redundant bits to the high-order resistor network of the DAC. This allows the DAC to combine the advantages of a resistive DAC (high speed, good monotonicity, and small circuit area) while also possessing a certain degree of error correction capability.

[0049] refer to Figure 4 and Figure 5 , Figure 4 This paper shows a schematic diagram of the low-order resistor network in the digital-to-analog converter circuit provided in the second embodiment of this application. Figure 5 A schematic diagram of the high-order resistor network in the digital-to-analog converter circuit provided in the second embodiment of this application is shown. Figure 4 and Figure 5 As shown, the digital-to-analog converter circuit provided in the second embodiment of this application includes: a low-order resistor network 123 and a high-order resistor network 124 connected in series, wherein the low-order resistor network 123 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the lower K bits (denoted as D)<k-1,0> The high-order resistor network 124 is controlled by an N-bit digital signal D.<n-1,0> The logic values ​​of the high NK bits are defined, and the high NK bits of the N-bit digital signal include redundant bits, where K is an integer greater than zero and less than M. That is, in the second embodiment of this application, the N-bit digital signal D output by the control logic circuit 140...<n-1,0> M-bit digital signal D<m-1,0> The quantized signal of the redundant bit digital signal, where N and M are both positive integers, and N is greater than M.

[0050] In this embodiment, the low-side resistor network 123 adopts the same method as described above. Figure 2 The low-side resistor network 121 shown is basically the same design scheme as the one described above, which outputs a predetermined voltage Vout1. For details, please refer to the aforementioned design. Figure 2 The relevant descriptions of the content will be understood and will not be repeated here.

[0051] In this embodiment, the number of redundant bits in the N-bit digital signal is denoted as X, then X = NM, and the redundant bits include the lower NM bits of the higher NK bits in the N-bit digital signal. At this time, the total weight value of the low-bit resistor network 123 is equal to 1 / 2^MK.

[0052] In the second embodiment of this application, the high-order resistor network 124 is a non-binary weighted resistor network. For example, the high-order resistor network 124 is a thermometer code resistor network with redundant bits. (See reference...) Figure 5 The thermometer code resistor network includes NK groups of resistor-switch units connected in parallel. Each NK group of resistor-switch units is controlled by the logic value of the high NK bits of the N-bit digital signal. Each resistor-switch unit includes at least one unit resistor R. The first terminal of each unit resistor R is coupled to the output terminal of the low-order resistor network 123, and the second terminal of each unit resistor R is coupled to the reference voltage V via a selection switch S. H V L .

[0053] The number of unit resistors R in each resistor-switch unit is positively correlated with the weight value corresponding to that resistor-switch unit.

[0054] Optionally, in some embodiments, the redundant bits in the high-order resistor network 124 include at least one low-order bit obtained by splitting at least one original high-order bit. In other embodiments, the redundant bits in the high-order resistor network 124 include at least one low-order bit obtained by splitting at least one original high-order bit and recombinating the split multiple low-weight bits. In some other embodiments, a portion of the redundant bits in the high-order resistor network 124 include at least one low-order bit obtained by splitting at least one original high-order bit, and another portion of the redundant bits include at least one low-order bit obtained by splitting at least one original high-order bit and recombinating the split multiple low-weight bits. The weight value corresponding to each original high-order bit is a positive power of 2.

[0055] The embodiments of this application essentially achieve non-binary redundant encoding by directly splitting at least one original high-weight bit in the high-weight resistor network 124 into more low-weight bits, or by splitting at least one original high-weight bit in the high-weight resistor network 124 and then recombinating at least a portion of the low-weight bits to obtain more low-weight bits. For example, in some embodiments, the highest-weight bit of the high-weight resistor network 124 can be split into two or more lower-weight bits; in other embodiments, the highest-weight bit and the second-highest-weight bit of the high-weight resistor network 124 can be split into four or more lower-weight bits; in some other embodiments, only the second-highest-weight bit of the high-weight resistor network 124 can be split, or other splitting schemes can be used. The total weight of the high-weight resistor network 124 remains unchanged before and after the split, but the weight of each split high-weight bit is less than the original weight value.

[0056] Figure 5 An example of a high-order resistor network 124 including four sets of resistor-switch units is shown. These four sets of resistor-switch units include: resistor-switch unit 125, resistor-switch unit 126, resistor-switch unit 127, and resistor-switch unit 128. Resistor-switch unit 125 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the (K+1)th (or (n-4)th) bit in the N-bit digital signal D is...<n-1,0> The logic of the least significant bit in the high 4 bits (denoted as D) <n-4>The resistor-switch unit 126 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the (K+2)th (or (n-3)th) bit in the N-bit digital signal D is...<n-1,0> The logic of the second least significant bit among the high 4 bits (denoted as D) <n-3>The resistor-switch unit 127 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the (K+3)th (or (n-2)th) bit in the N-bit digital signal D is...<n-1,0> The logic of the second highest bit among the four highest bits (denoted as D) <n-2>The resistor-switch unit 128 is controlled by an N-bit digital signal D.<n-1,0> The logic value of the (K+4)th (or (n-1)th) bit in the N-bit digital signal D is...<n-1,0> The logic of the highest of the four high bits (denoted as D) <n-1>).

[0057] exist Figure 5 In the example shown, the resistor-switch unit 125 has a weight of 1 / 8 and includes a unit resistor R and a selection switch S, which is controlled by the N-bit digital signal D. <n-4>The resistor-switch unit 126 has a weight value of 1 / 8 and includes a unit resistor R and a selection switch S, which is controlled by the N-bit digital signal D. <n-3>The resistor-switch unit 127 has a weight value of 2 / 8 and contains two unit resistors R and two selector switches S, both of which are controlled by the N-bit digital signal D. <n-2>The resistor-switch unit 128 has a weight value of 3 / 8 and includes three unit resistors R and three selector switches S. Each of the three selector switches S is controlled by the N-bit digital signal D. <n-1>. Figure 5 The illustrated embodiment is equivalent to... Figure 2 The highest bit of the high-order resistor network 124 in the middle is split into D. <n-4>and D <n-1>Two logical bits, meaning the weight of the highest bit is split into two parts (the weight of the highest bit was originally 4 / 8, or 1 / 2, in...). Figure 5 The middle is split into D <n-4>The corresponding 1 / 8 and D <n-1>The corresponding 3 / 8), thus achieving non-binary redundant encoding where the weight values ​​of each high bit in the N-bit digital signal are 1 / 8, 1 / 8, 2 / 8, and 3 / 8 respectively. It can be understood that the scheme of the second embodiment of this application makes the quantization codewords in the analog-to-digital converter 100 exceed the binary algorithm codewords, thereby allowing overlapping windows between adjacent search intervals and realizing a redundant algorithm. Of course, in some other embodiments, Figure 5 Each resistor-switch unit can use only one selector switch.

[0058] Taking a 10-bit + 1-bit redundant RDAC as an example, the output signal (M-bit digital signal) of the analog-to-digital converter 100 has 10 bits, the redundant bits have 1 bit, and the N-bit digital signal output from the control logic circuit 140 to the digital-to-analog converter 120 has 11 bits. The lower 7-bit logic values ​​are weighted using a low-level resistor network (e.g., an R-2R resistor network) 123, while the higher 4-bit logic values ​​are weighted using a high-level resistor network (e.g., a thermometer code resistor network with redundant bits) 124. Furthermore, the highest bit of the higher 4-bit logic values ​​is split into two bits with weights of 3 / 8 and 1 / 8 respectively. (Refer to...) Figure 5 .at this time, Figure 4 and Figure 5 The transfer function (i.e., the scan output result) of the digital-to-analog converter circuit shown is as follows: Figure 6 As shown, the horizontal axis represents the 11-bit digital signal with redundant bits input to the digital-to-analog converter circuit, and the vertical axis represents the output value of the digital-to-analog converter circuit. Figure 6 As can be seen from this, most of the output values ​​of the digital-to-analog converter circuit disclosed in the second embodiment of this application can be obtained from at least two sets of 11-bit digital signals with redundant bits. This is equivalent to obtaining overlapping windows, i.e. error tolerance windows, in different search intervals. This allows the digital-to-analog converter circuit 100 to achieve error correction function even if the control logic circuit 140 outputs an incorrect codeword, resulting in an output error of the digital-to-analog converter circuit. This error correction function can be compensated by subsequent output codewords in subsequent successive approximation cycles. Through this redundancy, the digital-to-analog converter circuit 100 can achieve error correction function.

[0059] In summary, the digital-to-analog converter (DAC) circuit in the analog-to-digital converter (ADC) is constructed using two series-connected resistor networks. By splitting at least one original high-order bit in the high-order resistor network into more low-order bits, a DAC circuit with redundant bits is achieved, thereby optimizing the ADC structure. Compared with ADCs constructed using capacitor arrays, the proposed solution enables the ADC to have a certain error correction capability while operating faster, exhibiting better monotonicity, and having a smaller circuit area.

[0060] Furthermore, embodiments of this application also provide a chip including an analog-to-digital converter 100 as disclosed in any embodiment of this application. In some examples, the analog-to-digital converter 100 disclosed in any embodiment of this application can be applied to a chip with timing control functions, in which the analog-to-digital converter 100 can, for example, be used to measure the internal voltage of the chip at a certain operating voltage (e.g., 2.5V~3.3V). Of course, this example is only illustrative and does not mean that the analog-to-digital converter 100 disclosed in any embodiment of this application can only be applied to chips with timing control functions. In fact, the analog-to-digital converter 100 disclosed in any embodiment of this application can be applied as needed to any other type of chip that requires an analog-to-digital converter to realize the analog signal to digital signal conversion requirement.

[0061] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application. < / n-2> < / n-3> < / k-2>

Claims

1. An analog-to-digital converter, characterized by The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter.

2. The analog-to-digital converter of claim 1, wherein, The application relates to an analog-to-digital converter.

3. The analog-to-digital converter of claim 1, wherein, The application relates to an analog-to-digital converter.

4. The analog-to-digital converter of claim 3, wherein, The application relates to an analog-to-digital converter.

5. The analog-to-digital converter of claim 3, wherein, The application relates to an analog-to-digital converter.

6. The analog-to-digital converter of claim 1, wherein, The application relates to an analog-to-digital converter.

7. The analog-to-digital converter of claim 6, wherein, The application relates to an analog-to-digital converter.

8. The analog-to-digital converter of claim 7, wherein, The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter.

9. The analog-to-digital converter of claim 8, wherein, The application relates to an analog-to-digital converter.

10. The analog-to-digital converter of any of claims 1-9, wherein, The application relates to an analog-to-digital converter.

11. The analog-to-digital converter of any of claims 1-9, wherein, The application relates to an analog-to-digital converter.

12. The analog-to-digital converter of any one of claims 1-9, wherein, The application relates to an analog-to-digital converter.

13. A chip, characterized by The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. 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The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. 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The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application relates to an analog-to-digital converter. The application

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