Semiconductor die and interposer

Abstract

The utility model provides a semiconductor die and an interposer. An embodiment semiconductor die may include a silicon substrate and a first through silicon via (TSV) formed in the silicon substrate such that the first TSV includes a first protruding portion protruding from a surface of the silicon substrate. The embodiment semiconductor die may also include a dielectric isolation layer between the surface of the silicon substrate and a plane parallel to the first contact surface of the first TSV such that the dielectric isolation layer laterally surrounds the first protruding portion of the first TSV without covering the first contact surface of the first TSV. The semiconductor die may include a redistribution layer including a first redistribution via forming an electrical connection between a first contact surface of the first TSV and the at least one redistribution interconnect line. The dielectric isolation layer may prevent formation of a conductive path between the first redistribution via and the silicon substrate.

Description

Technical Field

[0001] This utility model relates to a semiconductor die and an interposer. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and assemblies. Tens, hundreds, or thousands of integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer can be individualized by sawing between the integrated circuits along dicing lines. For example, individual dies are often individually packaged in multi-chip modules or other types of packages.

[0003] In addition to smaller electronic components, improvements have been developed in the packaging of these components to strive for smaller packages that occupy less area than previous packages. Exemplary approaches include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), 3D integrated circuits (3DIC), wafer-level packaging (WLP), package-on-package (PoP), system-on-chip (SoC), or system-on-integrated circuit (SoIC) devices. Some of these 3D devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing chips on a single chip at the semiconductor wafer level. These 3D devices offer higher integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced interconnect lengths between stacked chips. However, there are many challenges associated with 3D devices. Utility Model Content

[0004] This invention provides a semiconductor die, comprising: a silicon substrate; a first through-silicon via (TSV) formed in the silicon substrate, wherein the first TSV includes a first protruding portion protruding from the surface of the silicon substrate; and a dielectric isolation layer located between the surface of the silicon substrate and a plane parallel to a first contact surface of the first TSV, such that the dielectric isolation layer laterally surrounds the first protruding portion of the first TSV but does not cover the first contact surface of the first TSV.

[0005] In some embodiments, the present invention provides an interposer layer comprising: a semiconductor die; and a molding material laterally surrounding the semiconductor die, wherein the semiconductor die comprises: a semiconductor substrate; a first electrical contact including a first protrusion extending from the surface of the semiconductor substrate; and a dielectric isolation layer located between the surface of the semiconductor substrate and a plane parallel to the first contact surface of the first electrical contact, such that the dielectric isolation layer laterally surrounds the first protrusion of the first electrical contact but does not cover the first contact surface of the first electrical contact.

[0006] In some embodiments, the present invention provides a method for forming an interposer, comprising: forming a molding material around a semiconductor die such that the molding material laterally surrounds the semiconductor die, wherein the molding material is formed such that one side of the semiconductor die is exposed, wherein the semiconductor die includes a first electrical contact formed in a semiconductor substrate; performing a recess etching process on the semiconductor substrate to remove a portion of the semiconductor substrate such that a first protrusion of the first electrical contact protrudes from the surface of the semiconductor substrate; depositing a dielectric material on the surface of the semiconductor substrate and the first electrical contact; and performing a planarization process to remove a portion of the dielectric material to expose a first contact surface of the first electrical contact, thereby forming a dielectric isolation layer located between the surface of the semiconductor substrate and a plane parallel to the first contact surface of the first electrical contact, such that the dielectric isolation layer laterally surrounds the first protrusion of the first electrical contact but does not cover the first contact surface of the first electrical contact.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] The various aspects of the embodiments of this utility model can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0009] Figure 1 This is an exploded vertical cross-sectional view of the components of a semiconductor package during the package assembly and surface mount processes.

[0010] Figure 2 It is a vertical cross-sectional view showing the related assembly of the semiconductor package mounted on a support substrate.

[0011] Figure 3A This is a vertical cross-sectional view of another semiconductor package according to various embodiments.

[0012] Figure 3B According to various embodiments Figure 3A An enlarged vertical cross-sectional view of a portion of a semiconductor package.

[0013] Figure 4A This is a vertical cross-sectional view of a portion of the interposer layer of a semiconductor die having a dielectric isolation layer, according to various embodiments.

[0014] Figure 4B It is a vertical cross-sectional view of a portion of the comparative interposer layer that includes the semiconductor die with the dielectric isolation layer omitted.

[0015] Figure 5A This is a vertical cross-sectional view of an intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0016] Figure 5B This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0017] Figure 5C This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0018] Figure 5D This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0019] Figure 5E This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0020] Figure 5F This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0021] Figure 5G This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0022] Figure 5H This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0023] Figure 5I This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0024] Figure 5J This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0025] Figure 6A This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0026] Figure 6B This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0027] Figure 6C This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0028] Figure 7A This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0029] Figure 7B This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0030] Figure 7C This is a vertical cross-sectional view of another intermediate structure that can be used to form an intermediary layer according to various embodiments.

[0031] Figure 8A This is a vertical cross-sectional view of a portion of an interposer layer according to various embodiments, the interposer layer including semiconductor dies having a dielectric isolation layer with a first configuration.

[0032] Figure 8B According to various embodiments Figure 8A A top view of the intermediate layer.

[0033] Figure 9A This is a vertical cross-sectional view of a portion of an interposer layer according to various embodiments, the interposer layer including semiconductor dies having a dielectric isolation layer of another configuration.

[0034] Figure 9B According to various embodiments Figure 9A A top view of the intermediate layer.

[0035] Figure 9C According to various embodiments Figure 9B A top view of the alternative configuration of the intermediate layer.

[0036] Figure 10 This is a flowchart of the operation of a method for forming an intermediary layer according to various embodiments. Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of the embodiments of the present invention. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0038] Furthermore, for ease of description, this document uses spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations shown in the figures, spatially related terms are also intended to cover different orientations of the device or operation in use. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly. Unless otherwise explicitly stated, each component with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0039] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) dies (i.e., "chips") can be mounted on a common substrate, also referred to as the "package substrate." In some embodiments, electrical connections to the semiconductor package can be achieved by mounting the package substrate onto a support substrate (e.g., a printed circuit board (PCB)) containing electrical interconnects. The semiconductor package may also include an interposer to which one or more semiconductor dies are attached and electrically coupled. The interposer may in turn be attached and electrically coupled to the package substrate, which may be further attached to the PCB. In this way, individual structures (e.g., semiconductor dies, interposer, package substrate, and PCB) can be fabricated and then assembled.

[0040] The disclosed embodiments can be advantageous by providing an interposer layer comprising a semiconductor die having a dielectric isolation layer formed between a surface of a semiconductor substrate and a plane parallel to the contact surface of an electrical contact of the semiconductor die. When a redistribution layer is formed on the semiconductor die, some redistribution vias intended to be electrically connected to the electrical contacts of the semiconductor die may become misaligned due to process variations. This misalignment may cause some redistribution vias to contact portions of the corresponding electrical contacts as well as portions of the dielectric isolation layer. The presence of the dielectric isolation layer prevents undesirable leakage between the redistribution interconnects / vias and the semiconductor substrate, leakage that would otherwise occur in comparative embodiments without a dielectric isolation layer.

[0041] An embodiment of the semiconductor die may include a silicon substrate and a first through-silicon-via (TSV) formed in the silicon substrate, such that the first TSV includes a first protrusion extending from the surface of the silicon substrate. The semiconductor die may further include a dielectric isolation layer located between the surface of the silicon substrate and a plane parallel to the first contact surface of the first TSV, such that the dielectric isolation layer laterally surrounds the first protrusion of the first TSV without covering the first contact surface of the first TSV. The semiconductor die may include a redistribution layer including a first redistribution via forming an electrical connection between the first contact surface of the first TSV and at least one redistribution interconnect. The dielectric isolation layer prevents the formation of a conductive path between the first redistribution via and the silicon substrate.

[0042] In this embodiment, the interlayer may include a semiconductor die and a molding compound laterally surrounding the semiconductor die. The semiconductor die may include a semiconductor substrate, a first electrical contact including a first protrusion extending from the surface of the semiconductor substrate, and a dielectric isolation layer located between the surface of the semiconductor substrate and a plane parallel to the first contact surface of the first electrical contact. The dielectric isolation layer may laterally surround the first protrusion of the first electrical contact without covering the first contact surface of the first electrical contact. In this embodiment, the interlayer may further include a polymer layer formed over the semiconductor die and the molding compound, such that the polymer layer at least partially covers the dielectric isolation layer, at least one redistribution interconnect formed in the polymer layer, and a first redistribution via electrically connecting the first contact surface of the first electrical contact and the at least one redistribution interconnect. The dielectric isolation layer may prevent the formation of a conductive path between the first redistribution via and the silicon substrate.

[0043] An embodiment of forming an interposer may include forming a molding compound around a semiconductor die such that the molding compound laterally surrounds the semiconductor die. The molding compound may be formed such that one side of the semiconductor die, including a first electrical contact formed in a semiconductor substrate, is exposed. The method may further include performing a recess etching process on the semiconductor substrate to remove a portion of the semiconductor substrate such that a first protrusion of the first electrical contact protrudes from the surface of the semiconductor substrate, and depositing a dielectric material over the semiconductor substrate and the surface of the first electrical contact. The method may further include performing a planarization process to remove portions of the dielectric material to expose a first contact surface of the first electrical contact, thereby forming a dielectric isolation layer located between the surface of the semiconductor substrate and a plane parallel to the first contact surface of the first electrical contact. In this way, the dielectric isolation layer may laterally surround the first protrusion of the first electrical contact without covering the first contact surface of the first electrical contact.

[0044] Figure 1 This is an exploded vertical cross-sectional view of the relevant semiconductor package 100 during the packaging assembly and surface mount processes. Figure 2 This is a vertical cross-sectional view showing a semiconductor package 100 assembled onto the surface of a support substrate 102, such as a printed circuit board (PCB). The semiconductor package 100 in this example is a chip-on-wafer-on-substrate (CoWoS) semiconductor package; however, it will be understood that similar assembly and mounting processes can be used for other types of semiconductor packages, such as integrated fan-out (InFO) semiconductor packages, flip-chip semiconductor packages, etc.

[0045] refer to Figure 1 and Figure 2 The associated semiconductor package 100 may include integrated circuit (IC) semiconductor devices, such as a first semiconductor device 104 and a second semiconductor device 106. During the package assembly process, the first semiconductor device 104 and the second semiconductor device 106 may be mounted on an interposer 108, and the interposer 108 containing the first semiconductor device 104 and the second semiconductor device 106 may be mounted on a package substrate 110 to form the semiconductor package 100. The semiconductor package 100 may then be mounted to a support substrate 102, such as a printed circuit board (PCB), by mounting the package substrate 110 to a support substrate 102 using an array of first solder balls 112 on the lower surface 114 of the package substrate 110.

[0046] A parameter that ensures proper interconnection between the package substrate 110 and the support substrate 102 is the coplanarity between the surfaces of the first solder ball 112, which can be connected to the mounting surface (i.e., Figure 1The upper surface 116 of the support substrate 102 is in contact with the first solder ball 112. The low coplanarity between the first solder balls 112 may cause solder cold joint (i.e., insufficient melting of solder material, resulting in poor bonding and easy breakage and separation) and / or solder bridging problems during the reflow process (i.e., the solder material of one solder ball 112 comes into contact with the material of the adjacent solder ball 112, resulting in unintentional connection (i.e. electrical short circuit)).

[0047] During the mounting of the package substrate 110 surface onto the support substrate 102, deformation of the package substrate 110 (e.g., stress-induced warping of the package substrate 110) can be a cause of low coplanarity of the first solder balls 112. Deformation of the package substrate 110 is not uncommon, especially in high-performance computing applications using semiconductor packages 100. These high-performance semiconductor packages 100 tend to be relatively large and may include multiple semiconductor devices (e.g., 104, 106) mounted to the package substrate 110, which can increase the likelihood of warping or other deformation of the package substrate 110. Such deformation can pose challenges to the effective soldering of these types of semiconductor package substrates 110 onto the support substrate 102.

[0048] In various embodiments, the first semiconductor device 104 may be a three-dimensional device, such as a three-dimensional integrated circuit (3DIC), a system-on-a-chip (SoC), or a system-on-integrated-chip (SoIC) device. The three-dimensional semiconductor device 104 can be formed by placing chips on top of each other at the semiconductor wafer level. Due to the reduced interconnect length between stacked chips, these three-dimensional devices can provide improved integration density and other advantages, such as faster speeds and higher bandwidth. In some embodiments, the first three-dimensional semiconductor device 104 may also be referred to as a “first die stack.”

[0049] The second semiconductor device 106 may differ from the first semiconductor device 104 in its structure, design, and / or function. One or more second semiconductor devices 106 may be three-dimensional semiconductor devices, also referred to as a "second die stack." In some embodiments, one or more second semiconductor devices 106 may include memory devices, such as high bandwidth memory (HBM) devices. Figure 1 and Figure 2 In the example shown, semiconductor package 100 may include SoC die stack 104 and HBM die stack 106, but it should be understood that semiconductor package 100 may include more or fewer semiconductor devices.

[0050] Refer again Figure 2The first semiconductor device 104 and the second semiconductor device 106 may be mounted on the interposer 108. In some cases, the interposer 108 may be an organic interposer comprising a polymer dielectric material (e.g., a polyimide material) having a plurality of metal interconnect structures extending therethrough. In other cases, the interposer 108 may be a semiconductor interposer, such as a silicon interposer, having a plurality of interconnect structures (e.g., through-silicon vias) extending therethrough. Other suitable configurations for the interposer 108 are within the scope of this embodiment of the invention. The interposer 108 may include a plurality of conductive bonding pads on the upper and lower surfaces of the interposer and a plurality of conductive interconnects extending through the interposer 108 between the upper and lower bonding pads. The conductive interconnects may distribute and route electrical signals between the first semiconductor device 104, the second semiconductor device 106, and the underlying packaging substrate 110.

[0051] Multiple first metal bumps 120, such as microbumps, can electrically connect conductive bonding pads on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106 to conductive bonding pads on the upper surface of the interposer 108. In a non-limiting embodiment, the first metal bumps 120 in the form of microbumps may include multiple first metal stacks (e.g., multiple Cu-Ni-Cu stacks) on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106, and multiple second metal stacks (e.g., Cu-Ni-Cu stacks) on the upper surface of the interposer 108. Solder material (such as tin (Sn)) may be located between the respective first and second metal stacks to electrically connect the first semiconductor device 104 and the second semiconductor device 106 to the interposer 108. Other suitable materials for the first metal bumps 120 and solder material are within the scope of this embodiment of the invention.

[0052] After the first semiconductor device 104 and the second semiconductor device 106 are mounted to the interposer 108, a first underfill material portion 122 can be selectively disposed around the first metal bump 120 and in the space between the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106 and the upper surface of the interposer 108, such as... Figure 2 As shown. The first underfill material portion 122 may also be disposed in the space that laterally separates adjacent first semiconductor devices 104 and second semiconductor devices 106 of the semiconductor package 100. In various embodiments, the first underfill material portion 122 may include an epoxy-based material, which may include a composite of resin and filler material.

[0053] Refer again Figure 2Intermediate layer 108 may be mounted on package substrate 110, which may provide mechanical support for intermediate layer 108 and first semiconductor device 104 and second semiconductor device 106 mounted on intermediate layer 108. Package substrate 110 may include suitable materials, such as organic materials (e.g., polymers and / or thermoplastics), semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, glass materials, combinations thereof, etc. Other suitable substrate materials are also within the scope of this invention. In various embodiments, package substrate 110 may include a plurality of conductive bonding pads (not shown) in the upper surface 126 of package substrate 110. A plurality of second metal bumps 124, such as C4 solder bumps, may electrically connect the conductive bonding pads (not shown) on the bottom surface of intermediate layer 108 to the conductive bonding pads on the upper surface 126 of package substrate 110. In various embodiments, the second metal bumps 124 may include suitable solder materials, such as tin (Sn), but other suitable solder materials are also within the scope of this invention.

[0054] The second bottom filler portion 128 can be disposed around the second metal bump 124 and in the space between the bottom surface of the interposer 108 and the upper surface 126 of the encapsulation substrate 110, for example, such as Figure 2 As shown. In various embodiments, the second bottom filler portion 128 may include an epoxy-based material, which may include a composite of a resin and a filler material. In some embodiments, the lid or cover ( Figure 1 and Figure 2 (Not shown) can be mounted to the packaging substrate 110 and can provide a housing around the upper and side surfaces of the first semiconductor device 104 and the second semiconductor device 106.

[0055] As described above, the encapsulation substrate 110 can be mounted to the support substrate 102, such as a printed circuit board (PCB). Other suitable support substrates 102 are within the scope of this embodiment. The encapsulation substrate 110 may include a plurality of conductive bonding pads 130 in the lower surface 114 of the encapsulation substrate 110. A plurality of conductive interconnects (not shown) may extend through the encapsulation substrate 110 between the conductive bonding pads on the upper surface 126 and the lower surface 114 of the encapsulation substrate 110. A plurality of first solder balls 112 (or bump structures) may electrically connect the conductive bonding pads 130 on the lower surface 114 of the encapsulation substrate 110 to a plurality of conductive bonding pads 132 on the upper surface 116 of the support substrate 102.

[0056] The bonding pads 130 of the package substrate 110 and the bonding pads 132 of the support substrate 102 can be formed of a suitable conductive material, such as copper. Other suitable conductive materials are within the scope of this embodiment. A plurality of first solder balls 112 on the lower surface 114 of the package substrate 110 can be formed into an array of first solder balls 112, such as a ball grid array (BGA), which may include an array pattern corresponding to the array pattern of the conductive bonding pads 132 on the upper surface 116 of the support substrate 102. In a non-limiting example, the array of first solder balls 112 may include a grid pattern and may have a spacing (i.e., the distance between the center of each solder ball 112 and the center of each adjacent solder ball 112). In an exemplary embodiment, the spacing may be between approximately 0.8 mm and 1.0 mm, but larger and smaller spacings may be used.

[0057] The first solder ball 112 may include any suitable solder material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, alloys thereof, combinations thereof, or the like. Other suitable materials for the first solder ball 112 are within the scope of this embodiment of the invention. In some embodiments, the lower surface 114 of the package substrate 110 may include a coating of solder resist (SR) material (not shown), which may also be referred to as a "solder mask". The SR material coating may provide a protective coating for the package substrate 110 and any underlying circuit patterns formed on or within the package substrate 110. The SR material coating may also inhibit solder material from adhering to the lower surface 114 of the package substrate 110 during the reflow process. In embodiments where the lower surface 114 of the package substrate 110 includes an SR coating, the SR material coating may include a plurality of openings through which the bonding pad 130 may be exposed.

[0058] In various embodiments, each conductive bonding pad 130 in different regions of the encapsulation substrate 110 may have the same size and shape. Figure 1 and Figure 2 In the illustrated embodiments, the surface of the bonding pad 130 may be substantially coplanar with the lower surface 114 of the encapsulation substrate 110, wherein in some embodiments, the encapsulation substrate 110 may include a solder resist (SR) coating. Alternatively, the surface of the bonding pad 130 may be recessed relative to the lower surface 114 of the encapsulation substrate 110. In some embodiments, the surface of the bonding pad 130 may be raised relative to the lower surface 114 of the encapsulation substrate 110.

[0059] Refer again Figure 1 and Figure 2The first solder ball 112 may be disposed on the corresponding conductive bonding pad 130. In a non-limiting example, the conductive bonding pad 130 may have a width dimension between about 500 μm and about 550 μm (e.g., ~530 μm), and the first solder ball 112 may have an outer diameter between about 600 μm and about 650 μm (e.g., ~630 μm), although larger and smaller dimensions of the first solder ball 112 and / or bonding pad 130 are within the contemplation range of this embodiment of the invention.

[0060] The first solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250°C) to melt the first solder balls 112 and cause the first solder balls 112 to adhere to the conductive bonding pads 130. After the first reflow process, the package substrate 110 may be cooled, causing the first solder balls 112 to re-solder. After the first solder reflow process, the first solder balls 112 may adhere to the conductive bonding pads 130. Each solder ball 112 may extend vertically from the lower surface 114 of the package substrate 110, and this vertical height may be less than the outer diameter of the solder ball 112 before the first reflow process. For example, the outer diameter of the solder ball 112 is between about 600 μm and about 650 μm (e.g., ~630 μm), and the vertical height of the solder ball 112 after the first reflow process may be between about 500 μm and about 550 μm (e.g., ~520 μm).

[0061] In various embodiments, such as Figure 2 The process of mounting the package substrate 110 onto the support substrate 102 may include aligning the package substrate 110 over the support substrate 102 such that first solder balls 112 contacting the conductive bonding pads 130 of the package substrate 110 can be positioned over corresponding bonding pads (e.g., bonding pads 132) on the support substrate 102. A second solder reflow process may then be performed. The second solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250°C) to melt the first solder balls 112 and cause the first solder balls 112 to adhere to the corresponding bonding pads 132 on the support substrate 102. As the solder material cools and solidifies, surface tension may cause the semi-liquid solder to keep the package substrate 110 aligned with the support substrate 102. When the first solder ball 112 is cured, the encapsulation substrate 110 may be located above the upper surface 116 of the support substrate 102 by a stand-off height, which may be between about 0.4 mm and about 0.5 mm, but may be larger or smaller than that expected in this embodiment of the invention.

[0062] After mounting the encapsulation substrate 110 onto the support substrate 102, a third bottom filler portion 134 can be provided around the first solder ball 112 and in the space between the lower surface 114 of the encapsulation substrate 110 and the upper surface 116 of the support substrate 102, such as... Figure 2 As shown. In various embodiments, the third bottom filler portion 134 may include an epoxy-based material, which may include a composite of a resin and a filler material.

[0063] Figure 3A This is a vertical cross-sectional view of another semiconductor package 300 according to various embodiments. Figure 3B yes Figure 3A This is an enlarged vertical cross-sectional view of a portion of the semiconductor package 300. The semiconductor package 300 may include a plurality of semiconductor devices (104, 106a, 106b) attached to an interposer 108. Therefore, the interposer 108 may be connected to the package substrate 110. The semiconductor package 300 may be configured as a CoWoS-L package. In this regard, the interposer 108 may be a molding-based interposer that may include one or more through-interposer vias (TIVs) 302. The TIVs 302 may be formed within a molding material 304, as described below. Figures 5A to 5J More detailed description. The molding material 304 may also surround one or more active or passive semiconductor dies (107a, 107b, 109). For example, the interposer 108 may include a first local-silicon-interconnect (LSI) 107a and a second LSI 107b. The interposer 108 may also include one or more integrated passive devices (IPDs) 109.

[0064] Semiconductor devices (104, 106a, 106b) can provide various functions. For example, as described above, the first semiconductor device 104 can be configured as a SoC die stack. Also as described above, the semiconductor package 300 may include a first HBM die 106a and a second HBM die 106b. A first LSI 107a can provide a fine-pitch electrical connection between the first semiconductor device 104 and the first HBM die 106a, and a second LSI 107b can provide a fine-pitch electrical connection between the first semiconductor device 104 and the second HBM die 106b. An IPD 109 can be electrically connected to the SoC die stack 104 and may include one or more passive electrical components, such as inductors, capacitors, resistors, diodes, etc. In this way, the IPD 109 can provide additional circuitry functionality to the SoC die stack 104. For example, in various embodiments, the IPD 109 may include one or more deep trench capacitors (DTCs).

[0065] like Figure 3A and Figure 3B As shown, the intermediate layer 108 may also include various redistribution layer (RDL) 306. For example... Figure 3A As shown, RDL306 can have a relatively wide inline spacing compared to the inline spacing provided by the LSIs (107a, 107b). Semiconductor devices (104, 106a, 106b) can be electrically connected to RDL306 on the top side of the interposer 108, and the interposer 108 can be electrically connected to the package substrate 110 via RDL306 formed on the bottom side of the interposer 108. Figure 3A and Figure 3B As shown, RDL306 can be formed on the surface of the molding material 304 and on the surface of one or more active or passive semiconductor dies (107a, 107b, 109), as referenced. Figure 4A To describe in more detail.

[0066] Figure 4A This is a vertical cross-sectional view of a portion of an interposer 108a including an active or passive semiconductor die (107, 109) having a dielectric isolation layer 402, according to various embodiments. Figure 4B This is a vertical cross-sectional view of a portion of the comparative interposer 108b including semiconductor dies (107, 109) with the dielectric isolation layer 402 omitted. As shown, the semiconductor dies (107, 109) may include a semiconductor substrate 404 and one or more electrical contacts (406a, 406b) formed in the semiconductor substrate 404. According to some embodiments, the semiconductor substrate 404 may be a silicon substrate, and the one or more electrical contacts 406 may be through-silicon vias (TSVs). Interposer 108b may also include RDL 306.

[0067] RDL306 may include a polymer layer 408 formed on the semiconductor dies (107, 109) and the molding material 304, such that the polymer layer 408 at least partially covers the dielectric isolation layer 402. RDL306 may also include at least one redistribution interconnect (410a, 410b) formed in the polymer layer 408. RDL306 may also include one or more redistribution vias (412a, 412b) that electrically connect one or more electrical contacts 406 to the respective redistribution interconnects 410a, 410b (collectively referred to as 410).

[0068] The presence of dielectric isolation layer 402 can be advantageous because it prevents the formation of conductive paths between one or more redistribution vias (412a, 412b) and the semiconductor substrate 404. In this regard, due to process variations and differences in the coefficient of thermal expansion (CTE), there may be misalignment of one or both of the redistribution vias (412a, 412b) relative to their corresponding electrical contacts (406a, 406b). For example, as... Figure 4A As shown, the first redistribution via 412a may be slightly misaligned relative to the first electrical contact 406a. In this way, the first redistribution via 412a may partially contact the first electrical contact 406a and partially contact the dielectric isolation layer 402. Thus, the dielectric isolation layer 402 can prevent current from flowing between the first redistribution via 412a and the semiconductor substrate 404, such as... Figure 4A As shown by the dashed arrow. Conversely, as... Figure 4B As shown, without the dielectric isolation layer 402, current can flow from the first redistribution via 412a into the semiconductor substrate 404, such as... Figure 4B As shown by the dashed arrow.

[0069] Figure 5A , Figure 5B and Figure 5C This is a vertical cross-sectional view of corresponding intermediate structures 500a, 500b, and 500c that can be used to form the intermediate layers 108 (108a, 108b) according to various embodiments. Intermediate structure 500a may include a carrier substrate 502 on which a seed layer 504 is formed. The seed layer 504 can be formed by sputtering. Figure 5B The intermediate structure 500b may include a patterned photoresist 506 formed above the seed layer 504. The patterned photoresist may include openings 508 formed in the patterned photoresist 506. Figure 5C In the intermediate structure 500c, TIV302 can be made by electroplating a metal filler material (such as copper, nickel, or a stack of copper and nickel) onto the substrate. Figure 5B The intermediate structure 500b is formed in the patterned photoresist 506 opening 508.

[0070] The metal seed layer 504 may include, for example, a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may be in the range of 50 nm to 400 nm, and the thickness of the copper seed layer may be in the range of 100 nm to 500 nm. The metal filler material may include copper, nickel, or copper and nickel. Other suitable metal filler materials are also within the scope of this embodiment. After the formation of TIV302, the patterned photoresist 506 can then be removed by ashing or dissolving in a solvent. Then, portions of the seed layer 504 may be etched in the regions between the electroplated metal filler material portions to produce TIV302 as a separated structure formed on the carrier substrate 502, for example, such as Figure 5D As shown in the image.

[0071] Figure 5D This is a vertical cross-sectional view of another intermediate structure 500d that can be used to form the interposer layer 108 according to various embodiments. As shown, the intermediate structure 500d may include a TIV 302 attached to a carrier substrate 502, which may be referenced above. Figures 5A to 5C The process described is used to form the intermediate structure 500d. The intermediate structure 500d may also contain one or more semiconductor dies (107, 109). One or more semiconductor dies (107, 109) may be attached to the carrier substrate 502 using an adhesive layer (not shown).

[0072] Figure 5E This is a vertical cross-sectional view of another intermediate structure 500e that can be used to form the interposer 108 according to various embodiments. The intermediate structure 500e can be formed from the intermediate structure 500d by forming a molding compound 304 around one or more semiconductor dies (107, 109) and TIV302. The molding compound 304 can be an epoxy molding compound (EMC) that can be applied to the gap between the continuous components of one or more semiconductor dies (107, 109) and TIV302. The molding compound 304 can be configured to provide mechanical support for one or more semiconductor dies (107, 109) and TIV302. The EMC can include an epoxy resin-containing compound that can be cured (i.e., cured) to provide a dielectric material portion with sufficient stiffness and mechanical strength. In this regard, the Young's modulus of pure epoxy resin is about 3.35 GPa, and by adding additives, the Young's modulus of the molding compound 304 can be higher than that of pure epoxy resin. The Young's modulus of the molding material 304 can be greater than 3.5 GPa.

[0073] EMC may include epoxy resin, hardener, silica (as filler), and other additives. Depending on viscosity and flowability, EMC can be provided in liquid or solid form. Liquid EMC offers better handling, good flowability, less voids, better filling, and fewer flow marks. Solid EMC offers less curing shrinkage, better stand-off, and less grain drift. High filler content in EMC (e.g., 85% by weight) can shorten molding time, reduce molded part shrinkage, and reduce molded part warpage. Uniform filler size distribution in EMC can reduce flow marks and enhance flowability. The curing temperature of EMC can range from 125°C to 150°C. A portion of the molding material 304 covering the horizontal plane (including the top surface of one or more semiconductor grains (107, 109)) can be removed by a planarization process (e.g., using chemical mechanical planarization (CMP)).

[0074] Figure 5F This is a vertical cross-sectional view of another intermediate structure 500f that can be used to form the interposer layer 108 according to various embodiments. It can be achieved by forming a patterned photoresist 506 on the intermediate structure 500f. Figure 5E Intermediate structure 500e forms intermediate structure 500f. In this regard, a blanket layer of photoresist (not shown) can be formed on intermediate structure 500e. The blanket layer of photoresist can then be patterned using photolithography to create openings 508 in the patterned photoresist 506. The patterned photoresist 506 can then be used as an etching mask to etch intermediate structure 500f. As shown, the patterned photoresist 506 can be used to mask portions of the molding compound 304, TIV 302, and portions of the silicon substrate 404 of one or more semiconductor dies (107, 109). An etchant material 510 can then be introduced to etch portions of the silicon substrate 404. For example, dry etching can be performed by introducing a plasma etchant gas 510. In other embodiments, a wet etching process can be performed.

[0075] Figure 5G This is a vertical cross-sectional view of another intermediate structure 500g that can be used to form the intermediate layer 108 according to various embodiments. After performing the above-described etching process, the patterned photoresist 506 can be removed from the intermediate structure 500f to obtain... Figure 5F The intermediate structure 500f forms the intermediate structure 500g. In this regard, the patterned photoresist 506 can be removed by ashing or by dissolving it in a solvent. For example... Figure 5GAs shown, the etching process can remove a portion of the semiconductor substrate 404, thereby creating the recessed region 512. In this regard, the first protrusion 514a of the first electrical contact 406a and the second protrusion 514b of the second electrical contact 406b can be exposed and thus can each protrude from the surface 516 of the semiconductor substrate 404.

[0076] Figure 5H This is a vertical cross-sectional view of another intermediate structure 500h that can be used to form the intermediate layer 108 according to various embodiments. It can be seen through... Figure 5G The intermediate structure is deposited with 402L dielectric material on top of 500g. Figure 5G The intermediate structure 500g forms the intermediate structure 500h. In this regard, dielectric material 402L can be deposited over the surface 516 of the semiconductor substrate 404 and over the first electrical contact 406a and the second electrical contact 406b. As shown, dielectric material 402L can also be deposited over a portion of the molding material 304. According to one embodiment, dielectric material 402L can be a polymer material. For example, the polymer can be polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO). Various other polymer materials can be used in other embodiments. Polymer material 402L can be deposited using spin coating technology, or it can be deposited using various other deposition techniques, such as vapor-deposition polymerization, chemical vapor deposition (CVD), etc.

[0077] Figure 5I This is a vertical cross-sectional view of another intermediate structure 500i that can be used to form the intermediate layer 108 according to various embodiments. A portion of the dielectric material 402L can be removed from the top surface of the intermediate structure 500h by performing a planarization process (e.g., using chemical mechanical planarization (CMP)). Figure 5H The intermediate structure 500h forms the intermediate structure 500i. As shown in the figure, a planarization process can be performed to remove a sufficient amount of dielectric material 402L, thereby exposing the first contact surface 520a of the first electrical contact 406a and the second contact surface 520b of the second electrical contact 406b.

[0078] In this regard, the above reference Figure 4A The described dielectric isolation layer 402 can be formed from the remaining portion of the dielectric material 402L after a planarization process. For example... Figure 5IAs shown, the dielectric isolation layer 402 can be located between the surface 516 of the semiconductor substrate 404 and the plane parallel to the first contact surface 520a of the first electrical contact 406a and the second contact surface 520b of the second electrical contact 406b. Furthermore, as... Figure 5I As shown, the dielectric isolation layer 402 can laterally surround the first protrusion 514a of the first electrical contact 406a and the second protrusion 514b of the second electrical contact 406b, while exposing the corresponding first contact surface 520a and second contact surface 520b.

[0079] Figure 5J This is a vertical cross-sectional view of another intermediate structure 500j that can be used to form the intermediate layer 108 according to various embodiments. It can be seen through... Figure 5I The intermediate structure 500i has a redistribution layer 306 formed above the top surface. Figure 5I Intermediate structure 500i forms intermediate structure 500j. In this regard, a redistribution layer 306 can be formed by depositing a polymer layer 408 over one or more semiconductor dies (107, 109) and molding material 304, such that the polymer layer 408 at least partially covers the dielectric isolation layer 402. Redistribution vias (412a, 412b, 412c) and redistribution interconnects (410a, 410b, 410c) can then be formed in the polymer layer 408, such that electrical connections can be formed between the redistribution interconnects (410a, 410b, 410c) and the corresponding electrical contacts (406a, 406b) and the contact surfaces (520a, 520b, 520c) of TIV302, respectively.

[0080] In this regard, a photolithography process can be used to pattern the polymer layer 408 to create vias (not shown). A seed layer (e.g., Ti / Cu or other conductive material) can then be deposited over the exposed contact surfaces (520a, 520b, 520c) and over the remaining surface of the polymer layer 408. A patterned photoresist (not shown) can then be formed over the polymer layer 408, such that the areas not masked by the patterned photoresist include the vias and areas of the polymer layer 408 on which redistributed interconnects (410a, 410b, 410c) can subsequently be formed. The redistributed vias (412a, 412b, 412c) and redistributed interconnects (410a, 410b, 410c) can then be formed by depositing a conductive material. For example, according to one embodiment, copper can be deposited by performing an electroplating process to form redistributed vias (412a, 412b, 412c) and redistributed interconnects (410a, 410b, 410c). Various other conductive materials may be used in other embodiments.

[0081] like Figure 5I and Figure 5J As further shown, the dielectric isolation layer 402 can be configured to extend laterally beyond the first contact surface 520a and the second contact surface 520b. Therefore, any misalignment between the redistribution vias (412a, 412b) and the contact surfaces (520a, 520b) may only result in one or both of the redistribution vias (412a, 412b) partially contacting the contact surfaces (520a, 520b) and the dielectric isolation layer 402. This prevents the redistribution vias (412a, 412b) from contacting the semiconductor substrate 404, for example, as... Figure 4A As shown and described in more detail above. In this way, the dielectric isolation layer 402 can prevent the formation of conductive paths between one or both of the redistribution vias (412a, 412b) and the semiconductor substrate 404. Therefore, it is possible to avoid... Figure 4B The dashed arrow in the image indicates an unwanted conductive path.

[0082] Figures 6A to 7C This is a vertical cross-sectional view of corresponding additional intermediate structures (600a to 700c) that can be used to form the intermediate layer 108 according to various embodiments. In this regard, Figure 6A and Figure 7A Corresponding to Figure 5H The intermediate structure 500h corresponds to the alternative intermediate structure; Figure 6B and Figure 7B Corresponding to Figure 5I The intermediate structure corresponding to the 500i intermediate structure; Figure 6C and Figure 7C Corresponding to Figure 5J The intermediate structure 500j corresponds to the alternative intermediate structure. In this regard, in one embodiment, reference can be made to... Figure 6A , Figure 6B and Figure 6C The intermediate structures (600a, 600b, 600c), in another embodiment, may be referred to Figure 7A , Figure 7B and Figure 7C The intermediate structures (700a, 700b, 700c) are used to perform the functions described in the reference above. Figure 5H , Figure 5I and Figure 5J The intermediate structures (500h, 500i, 500j) describe similar processing operations.

[0083] In Figure 6A , Figure 6B and Figure 6CIn embodiments related to the intermediate structures (600a, 600b, 600c), the molding compound (304, 402L) can be used as dielectric material 402L. The molding compound (304, 402L) can be similar to the molding compound 304 used to surround one or more of the aforementioned semiconductor grains (107, 109). For example, the molding compound can be an epoxy-based molding compound, which may or may not include various reinforcing materials. In some embodiments, the molding compound (304, 402L) can be the same material used to form the interposer 108. In other embodiments, different materials can be used for the molding compound 304 of the interposer 108 and the dielectric material 402L for forming the dielectric isolation layer 402.

[0084] In Figure 7A , Figure 7B and Figure 7C In embodiments related to the intermediate structures (700a, 700b, 700c), the dielectric material 402L can be a thin insulating material layer that can be deposited using a conformal deposition process. For example, the dielectric material 402L can include SiN, SiC, etc., that can be deposited using a CVD deposition process. As in other embodiments, a planarization process can be performed to remove excess portions of the dielectric material 402L, thereby exposing the electrical contacts (406a, 406b) and the contact surfaces of TIV302 (520a, 520b, 520c). Additional grinding and / or chemical treatment operations can be performed as needed to remove any residual material (e.g., CuO). x (Residue).

[0085] Figure 8A This is a vertical cross-sectional view of a portion 800 of an interposer 108 according to various embodiments, the interposer 108 including semiconductor dies (107, 109) having a first-configured dielectric isolation layer 402, and Figure 8B yes Figure 8A A top view of the intermediate layer. (e.g.) Figure 8A and Figure 8B As shown, the dielectric isolation layer 402 may include a single portion that laterally surrounds the protruding portions (514a, 514b, 514c, 514d) of each of the corresponding plurality of electrical contacts (406a, 406b, 406c, 406d). As described above, each of the plurality of electrical contacts (406a, 406b, 406c, 406d) may be formed as a TSV or other type of electrical contact.

[0086] Figure 9A This is a vertical cross-sectional view of a portion 900 of an interposer 108 according to various embodiments, the interposer 108 comprising semiconductor dies (107, 109) having a further configured dielectric isolation layer 402. According to various embodiments, Figure 9B yes Figure 9A A top view of the intermediate layer. Figure 9C yes Figure 9B A top view of the intermediate layer portion of the alternative configuration. (e.g.) Figure 9B and Figure 9C As shown, the dielectric isolation layer 402 may include multiple disconnected portions. For example, as Figure 9B As shown, the dielectric isolation layer 402 may include a portion surrounding each electrical contact 406.

[0087] Alternatively, one or more portions of the dielectric isolation layer 402 may have separate portions surrounding two or more electrical contacts. For example, such as Figure 9C As shown, the dielectric isolation layer 402 may include a first portion 402a laterally surrounding the first electrical contact 406a and a second portion 402b laterally surrounding the second electrical contact 406b, such that the first portion 402a and the second portion 402b are separated from each other. In a further embodiment, the semiconductor die (107, 109) may also include a third electrical contact 406c and a fourth electrical contact 406d, such as Figure 9C As shown. A first portion 402a of dielectric isolation layer 402 may laterally surround a first protrusion 514a of first electrical contact 406a and a third protrusion 514c of third electrical contact 406c. Similarly, a second portion 402b of dielectric isolation layer 402 may laterally surround a second protrusion 514b of second electrical contact 406b and a fourth protrusion 514d of fourth electrical contact 406d. The dielectric isolation layer may be configured in various other ways in other embodiments.

[0088] Figure 10 This is a flowchart of the operation of a method 1000 for forming an interposer 108 according to various embodiments. In operation 902, method 1000 may include forming a molding compound 304 around semiconductor dies (107, 109) such that the molding compound 304 laterally surrounds the semiconductor dies (107, 109). The molding compound 304 may be formed such that one side of the semiconductor dies (107, 109) is exposed, the semiconductor dies (107, 109) including a first electrical contact 406a formed in a semiconductor substrate 404. In operation 904, method 1000 may include performing a recess etching process on the semiconductor substrate 404 to remove a portion of the semiconductor substrate 404 such that a first protrusion 514a of the first electrical contact 406a protrudes from a surface 516 of the semiconductor substrate 404. In operation 906, method 1000 may include depositing a dielectric material 402L over the surface 516 of the semiconductor substrate 404 and the first electrical contact 406a.

[0089] In operation 908, method 1000 may include performing a planarization process to remove a portion of dielectric material 402L to expose the first contact surface 520a of the first electrical contact 406a, thereby forming a dielectric isolation layer 402 located between a surface 516 of the semiconductor substrate 404 and a plane parallel to the first contact surface 520a of the first electrical contact 406a. In this regard, the dielectric isolation layer 402 may laterally surround the first protrusion 514a of the first electrical contact 406a without covering the first contact surface 520a of the first electrical contact 406a.

[0090] Method 1000 may further include forming a redistribution layer 306 by performing operations including: forming a polymer layer 408 over semiconductor dies (107, 109) and molding material 304 such that the polymer layer 408 at least partially covers the dielectric isolation layer 402; forming at least one redistribution interconnect (410a, 410b) in the polymer layer 408; and forming a first redistribution via 412a in the polymer layer 408 such that the first redistribution via 412a forms an electrical connection between a first contact surface 520a of a first electrical contact 406a and at least one redistribution interconnect (410a, 410b).

[0091] Method 1000 may further include forming a dielectric isolation layer 402 extending laterally beyond the first contact surface 520a, such that any misalignment between the first redistribution via 412a and the first contact surface 520a only causes the first redistribution via 412a to partially contact the first contact surface 520a of the first electrical contact 406a and partially contact the dielectric isolation layer 402, but not to contact the semiconductor substrate 404. In this respect, the dielectric isolation layer 402 can prevent the formation of a conductive path between the first redistribution via 412a and the semiconductor substrate 404.

[0092] According to various embodiments, the semiconductor die (107, 109) may further include a second electrical contact 406b, which includes a second protrusion 514b projecting from the surface 516 of the semiconductor substrate 404. Method 1000 may further include forming a dielectric isolation layer 402 between the surface 516 of the semiconductor substrate 404 and a plane parallel to the second contact surface 520b of the second electrical contact 406b, such that the dielectric isolation layer 402 laterally surrounds the second protrusion 514b of the second electrical contact 406b without covering the second contact surface 520b of the second electrical contact 406b.

[0093] Referring to all the accompanying drawings and various embodiments of the present invention, semiconductor dies (107, 109) are provided. The semiconductor dies (107, 109) may include a silicon substrate 404, a first through-silicon via (TSV) 406a formed in the silicon substrate 404, wherein the first TSV 406a may include a first protrusion 514a projecting from a surface 516 of the silicon substrate 404, and a dielectric isolation layer 402 located between the surface 516 of the silicon substrate 404 and a plane parallel to a first contact surface 520a of the first TSV 406a. In this respect, the dielectric isolation layer 402 may laterally surround the first protrusion 514a of the first TSV 406a without covering the first contact surface 520a of the first TSV 406a. In various embodiments, the dielectric isolation layer 402 may include an epoxy molding compound. Alternatively, the dielectric isolation layer 402 may include silicon nitride.

[0094] According to a further embodiment, a redistribution layer 306 may be formed on semiconductor dies (107, 109). The redistribution layer 306 may include a polymer layer 408 formed on the semiconductor dies (107, 109) such that the polymer layer 408 at least partially covers the dielectric isolation layer 402. The redistribution layer 306 may include at least one redistribution interconnect (410a, 410b) and a first redistribution via 412a formed in the polymer layer 408, the first redistribution via 412a forming an electrical connection between the first contact surface 520a of the first TSV 406a and the at least one redistribution interconnect (410a, 410b). Due to process variations, in some embodiments, the first redistribution via 412a may partially contact the first contact surface 520a of the first TSV 406a and may also partially contact the dielectric isolation layer 402. In this configuration, the dielectric isolation layer 402 can prevent the formation of a conductive path between the first redistribution via 412a and the silicon substrate 404.

[0095] According to various embodiments, the semiconductor die (107, 109) may further include a second TSV406b having a second protrusion 514b projecting from the surface 516 of the silicon substrate 404. In such embodiments, a dielectric isolation layer 402 may be further formed between the surface 516 of the silicon substrate 404 and a plane parallel to the second contact surface 520b of the second TSV406b, such that the dielectric isolation layer 402 laterally surrounds the second protrusion 514b of the second TSV406b without covering the second contact surface 520b of the second TSV406b. In various embodiments, the dielectric isolation layer 402 may include a single portion laterally surrounding both the first protrusion 514a of the first TSV406a and the second protrusion 514b of the second TSV406b. In other embodiments, the dielectric isolation layer 402 may include a first portion 402a laterally surrounding a first protrusion 514a of a first TSV 406a and a second portion 402b laterally surrounding a second protrusion 514b of a second TSV 406b, such that the first portion 402a and the second portion 402b are disconnected from each other.

[0096] In some other embodiments, the semiconductor dies (107, 109) may further include a third TSV 406c and a fourth TSV 406d, the third TSV 406c including a third protrusion 514c protruding from the surface 516 of the silicon substrate 404, and the fourth TSV 406d including a fourth protrusion 514d protruding from the surface 516 of the silicon substrate 404. A first portion 402a of the dielectric isolation layer 402 may laterally surround the first protrusion 514a of the first TSV 406a and the third protrusion 514c of the third TSV 406c. Similarly, a second portion 402b of the dielectric isolation layer 402 may laterally surround the second protrusion 514b of the second TSV 406b and the fourth protrusion 514d of the fourth TSV 406d.

[0097] Further, referring to all the accompanying drawings, according to various embodiments of the present invention, an interposer 108 is provided. The interposer 108 may include semiconductor dies (107, 109) and a molding compound 304 laterally surrounding the semiconductor dies (107, 109). The semiconductor dies (107, 109) may include a semiconductor substrate 404, a first electrical contact 406a including a first protrusion 514a projecting from a surface 516 of the semiconductor substrate 404, and a dielectric isolation layer 402 located between the surface 516 of the semiconductor substrate 404 and a plane parallel to the first contact surface 520a of the first electrical contact 406a. The dielectric isolation layer 402 may laterally surround the first protrusion 514a of the first electrical contact 406a without covering the first contact surface 520a of the first electrical contact 406a.

[0098] Intermediate layer 108 may further include a redistribution layer 306, which includes a polymer layer 408 formed on the semiconductor dies (107, 109) and molding material 304, such that the polymer layer 408 at least partially covers the dielectric isolation layer 402. The redistribution layer 306 may further include at least one redistribution interconnect (410a, 410b) formed in the polymer layer 408, and a first redistribution via 412a electrically connecting the first contact surface 520a of the first electrical contact 406a and the at least one redistribution interconnect (410a, 410b). Due to process variations, in some embodiments, the first redistribution via 412a may partially contact the first contact surface 520a of the first electrical contact 406a and may partially contact the dielectric isolation layer 402. In such embodiments, the dielectric isolation layer 402 may prevent the formation of a conductive path between the first redistribution via 412a and the semiconductor substrate 404. In some embodiments, the semiconductor substrate 404 may include silicon and the first electrical contact 406a may be formed as a TSV. In some embodiments, the dielectric isolation layer 402 may include silicon nitride. In yet another embodiment, each of the dielectric isolation layer 402 and the molding compound 304 includes an epoxy molding compound 304.

[0099] In some embodiments, the interposer 108 may further include a second electrical contact 406b, which includes a second protrusion 514b projecting from the surface 516 of the semiconductor substrate 404. In such embodiments, a dielectric isolation layer 402 may be further formed between the surface 516 of the semiconductor substrate 404 and a plane parallel to the second contact surface 520b of the second electrical contact 406b, such that the dielectric isolation layer 402 laterally surrounds the second protrusion 514b of the second electrical contact 406b but does not cover the second contact surface 520b of the second electrical contact 406b.

[0100] The above embodiments can provide advantages over existing semiconductor package structures. In this regard, the disclosed embodiments can provide an interposer 108 including semiconductor dies (107, 109) having a dielectric isolation layer 402 formed between a surface 516 of a semiconductor substrate 404 and a plane parallel to the contact surfaces (520a, 520b) of electrical contacts (406a, 406b). When a redistribution layer 306 is formed on the semiconductor dies (107, 109), some redistribution vias (412a, 412b) intended to be electrically connected to the electrical contacts (406a, 406b) of the semiconductor dies (107, 109) may become misaligned due to process variations. This misalignment may cause some redistribution vias (412a, 412b) to partially contact the corresponding electrical contacts (406a, 406b) and partially contact the dielectric isolation layer 402. The presence of dielectric isolation layer 402 prevents undesirable leakage between the redistributed interconnects (410a, 410b) / vias (412a, 412b) and the semiconductor substrate 404, which would otherwise occur in a comparative embodiment without dielectric isolation layer 402.

[0101] The foregoing overview of features and embodiments enables those skilled in the art to better understand various aspects of the embodiments of this utility model. Those skilled in the art should understand that they can readily use the embodiments of this utility model as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this utility model, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of this utility model.

Claims

1. A semiconductor die, comprising: comprises: a silicon substrate; a first through-silicon via formed in the silicon substrate, wherein the first through-silicon via comprises a first protruding portion protruding from a surface of the silicon substrate; and a dielectric isolation layer between the surface of the silicon substrate and a plane parallel to a first contact surface of the first through-silicon via, such that the dielectric isolation layer laterally surrounds the first protruding portion of the first through-silicon via, but does not cover the first contact surface of the first through-silicon via. Further comprising a redistribution layer formed over the semiconductor die, the redistribution layer comprising:

2. The semiconductor die of claim 1, wherein, a polymer layer formed over the semiconductor die, such that the polymer layer at least partially covers the dielectric isolation layer; at least one redistribution interconnect formed in the polymer layer; and a first redistribution via forming an electrical connection between the first contact surface of the first through-silicon via and the at least one redistribution interconnect. The first redistribution via partially contacts the first contact surface of the first through-silicon via and partially contacts the dielectric isolation layer, and 3. The semiconductor die of claim 2, wherein, wherein the dielectric isolation layer prevents formation of a conductive path between the first redistribution via and the silicon substrate. Further comprising:

4. The semiconductor die of claim 1, wherein, a second through-silicon via comprising a second protruding portion protruding from the surface of the silicon substrate, wherein the dielectric isolation layer is further formed between the surface of the silicon substrate and a plane parallel to a second contact surface of the second through-silicon via, such that the dielectric isolation layer laterally surrounds the second protruding portion of the second through-silicon via, but does not cover the second contact surface of the second through-silicon via. The dielectric isolation layer comprises a single portion laterally surrounding both the first protruding portion of the first through-silicon via and the second protruding portion of the second through-silicon via.

5. The semiconductor die of claim 4, wherein, The dielectric isolation layer comprises a first portion laterally surrounding the first protruding portion of the first through-silicon via and a second portion laterally surrounding the second protruding portion of the second through-silicon via, such that the first portion and the second portion are disconnected from each other.

6. The semiconductor die of claim 4, wherein, Further comprising:

7. The semiconductor die of claim 6, wherein the first and second semiconductor dies are flip chip dies. a third through-silicon via comprising a third protruding portion protruding from the surface of the silicon substrate; and a fourth through-silicon via comprising a fourth protruding portion protruding from the surface of the silicon substrate, wherein the first portion of the dielectric isolation layer laterally surrounds the first protruding portion of the first through-silicon via and the third protruding portion of the third through-silicon via, and wherein the second portion of the dielectric isolation layer laterally surrounds the second protruding portion of the second through-silicon via and the fourth protruding portion of the fourth through-silicon via. comprises: a semiconductor die; and 8. An interposer, comprising: a mold encapsulation material laterally surrounding the semiconductor die, wherein the semiconductor die comprises: a semiconductor substrate; a first electrical contact comprising a first protruding portion protruding from a surface of the semiconductor substrate; and a second electrical contact comprising a second protruding portion protruding from the surface of the semiconductor substrate. ​ ​ a dielectric isolation layer formed between the surface of the semiconductor substrate and a plane parallel to a first contact surface of the first electrical contact, such that the dielectric isolation layer laterally surrounds the first protruding portion of the first electrical contact, but does not cover the first contact surface of the first electrical contact.

9. The interposer of claim 8, wherein, Further comprising a redistribution layer, the redistribution layer comprising: a polymer layer formed over the semiconductor die and the mold encapsulation material, such that the polymer layer at least partially covers the dielectric isolation layer; at least one redistribution via formed in the polymer layer; and a first redistribution through via electrically connecting the first contact surface of the first electrical contact and the at least one redistribution via.

10. The interposer of claim 9, wherein, Further comprising: a second electrical contact comprising a second protruding portion protruding from the surface of the semiconductor substrate, wherein the dielectric isolation layer is further formed between the surface of the semiconductor substrate and a plane parallel to a second contact surface of the second electrical contact, such that the dielectric isolation layer laterally surrounds the second protruding portion of the second electrical contact, but does not cover the second contact surface of the second electrical contact.

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