Packaging chip

Abstract

The utility model discloses a packaging chip. The packaging chip comprises a redistribution layer; the chip set is arranged on one side of the redistribution layer and comprises at least two chips stacked in a step shape, and contacts of the at least two chips are arranged on the sides, facing the redistribution layer, of the chips; the binding wires comprise a first binding wire and a second binding wire, the first binding wire is electrically connected with the two chips in the chip set through the contacts, the second binding wire is electrically connected with one chip and the redistribution layer, and each chip is electrically connected to the redistribution layer through the second binding wire or the first binding wire and the second binding wire; and the sealing structure covers the chip set and the binding wire. Through the above mode, the signal interference between the binding wires of the packaged chip can be reduced, and the performance of the packaged chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip packaging, in particular to a packaged chip. BACKGROUND

[0002] With the continuous development of semiconductor technology, the requirements for product miniaturization and computing power are increasingly high. Therefore, in order to meet the use requirements, a plurality of chips are stacked in the same package by using a multi-chip stacking technology to realize the reduction of product volume and the improvement of product performance. In the related art, the chips in the product are stacked into a chip group, and then the vertical binding lines are led out for glue filling mask, and then the package is performed. However, if too many vertical binding lines are provided, there will be signal integrity problems such as crosstalk reflection between the vertical binding lines. If there is a higher frequency signal requirement, the problem is more prominent. CONTENT OF THE UTILITY MODEL

[0003] The main purpose of the present application is to provide a packaged chip which can reduce the signal interference between the binding lines of the packaged chip and improve the performance of the packaged chip.

[0004] In a first aspect, the present application provides a packaged chip. The packaged chip comprises a redistribution layer; a chip group arranged on one side of the redistribution layer, comprising at least two chips stacked in a stepped manner, and the contacts of the at least two chips are arranged on the side of the chips facing the redistribution layer; a binding line comprising a first binding line and a second binding line, the first binding line electrically connecting two chips in the chip group through the contacts, and the second binding line electrically connecting one chip and the redistribution layer, each chip being electrically connected to the redistribution layer through the second binding line or the first binding line and the second binding line; and a sealing structure covering the chip group and the binding line.

[0005] The beneficial effects of the present application are that, in the packaged chip, for the chips stacked in a stepped manner, the second binding line is used to electrically connect the adjacent chips, the chips can be connected to other chips through the second binding line, and then connected to the redistribution layer through the first binding line on the other chips, thereby reducing the number of second binding lines directly connecting the chips to the redistribution layer, reducing the signal interference caused by the second binding lines to each other, and improving the product performance of the packaged chip. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0007] Figure 1is a structural schematic diagram of a related art package chip embodiment;

[0008] Figure 2 is a structural schematic diagram of a first embodiment of a package chip structure of the present application;

[0009] Figure 3 is a structural schematic diagram of a second embodiment of a package chip structure of the present application;

[0010] Figure 4 is a structural schematic diagram of a third embodiment of a package chip structure of the present application;

[0011] Figure 5 is a structural schematic diagram of a fourth embodiment of a package chip structure of the present application;

[0012] BRIEF DESCRIPTION OF DRAWINGS

[0013] chip set-10; chip-11; contact-12; bonding wire-13; sealing structure-14; redistribution layer-15;

[0014] chip set-100; chip-110; contact-120; bonding wire-200; first bonding wire-210; second bonding wire-220; redistribution layer-300; sealing structure-400; solder ball-500. DETAILED DESCRIPTION

[0015] The embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments of the present application, and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.

[0017] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to each other. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0018] In the description of the embodiments of the present application, the technical terms "first", "second" and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise explicitly specified and limited.

[0019] In the description of the embodiments of the present application, the term "and / or" is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0020] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two), and similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0021] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application.

[0022] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0023] IC(Integrated Circuit, integrated circuit) chip needs to be packaged when applied. The main functions of packaging are three points: protecting the chip, as the chip itself is relatively fragile, dust and moisture will affect or even damage the operation of the chip, packaging can isolate the chip and the external environment; scale up, as the chip itself is small in size, the scale can be enlarged after packaging, which is convenient for subsequent PCB(Printed Circuit Board, printed circuit board) board-level system use; electrical connection, through packaging, the chip and the external environment can stably transmit information.

[0024] With the increasing miniaturization and higher performance requirements of electronic products, chip packaging structures gradually adopt chip stacking technology to stack two or more chips in a packaging structure, achieving product packaging size reduction and improving product performance.

[0025] Referring to Figure 1 , Figure 1 is a structural schematic diagram of a related art packaged chip embodiment.

[0026] In the related art, the chip packaging structure includes a chip group 10, and the chip group 10 includes a plurality of chips 11 stacked in a stepped manner. The chip 11 is provided with a contact 12 on the side facing the redistribution layer 15. The chip 11 is electrically connected to the redistribution layer 15 through the contact 12 and the bonding wire 13. The sealing structure 14 is provided on the same side of the redistribution layer 15 as the chip group 10. The sealing structure 14 wraps the chip group 10 and the bonding wire 13 inside to protect the chip 11.

[0027] Generally, the bonding wire 13 of the chip 11 connected to the redistribution layer 15 is a vertical bonding wire perpendicular to the redistribution layer 15. However, when multiple vertical bonding wires are provided, signal crosstalk, reflection, and other problems may exist between the vertical bonding wires, affecting signal integrity. And when facing higher frequency signal requirements, it may not be met.

[0028] In order to improve the use performance of the packaged chip, the present application provides a packaged chip.

[0029] Referring to Figure 2 , Figure 2 is a structural schematic diagram of a first embodiment of the packaged chip structure of the present application.

[0030] The packaged chip structure includes a chip group 100, a bonding wire 200, a redistribution layer 300, and a sealing structure 400.

[0031] The chip group 100, disposed on one side of the redistribution layer 300, comprises at least two chips 110 stacked in a stepped manner, and the contacts 120 of the at least two chips 110 are disposed on the side of the chips facing the redistribution layer 300. The chips 110 are electrically connected to other chips 110 or the redistribution layer 300 through the contacts 120 and the bonding wires 200.

[0032] The redistribution layer 300 is an interconnection technology used to optimize the electrical connection between the chip 11 and the package. The redistribution layer redistributes the original contacts of the chip 11 to more flexible positions through the stacking of metal wiring layers and insulating layers to meet the needs of advanced packaging. The metal layer is usually made of metal materials such as copper, and fine wiring is formed through techniques such as photolithography, electroplating, and etching. The insulating layer is usually made of polyimide (PI) or inorganic materials (such as SiO2), which is used to isolate the metal layer and prevent short circuits.

[0033] The bonding wire 200 comprises a first bonding wire 210 and a second bonding wire 220. The first bonding wire 210 electrically connects two chips 110 in the chip group 100 through the contacts 120. The second bonding wire 220 electrically connects one chip 110 to the redistribution layer 300. Each chip 110 is electrically connected to the redistribution layer 300 through the second bonding wire 220, or the first bonding wire 210 and the second bonding wire 220. The material of the bonding wire 200 can include copper, silver, or alloy materials.

[0034] The sealing structure 400 covers the chip group 100 and the bonding wire 200. The sealing structure 400 wraps the chip group 100 inside, which can protect the chips 110 in the chip group 100 from the influence of external dust, moisture, and other impurities, and can also achieve electrical isolation between the chip group 100 and the outside world to ensure the working performance of the chips 110 in the chip group 100. Moreover, the sealing structure 400 also wraps the bonding wire 200 inside, which protects the bonding wire 200 from damage such as friction and scratching. At the same time, the sealing structure 400 can also support and fix the bonding wire 200, which can help maintain the shape of the bonding wire 200, ensure the stable connection of the bonding wire 200 and the chip 110, and facilitate the connection of the bonding wire 200 and the redistribution layer 300.

[0035] The forming of the sealing structure 400 can be that the plastic sealing material is wrapped around the chip set 100 and the bonding wires 200 in a molten state, and the sealing structure 400 is formed after cooling and solidification. The basic components of the plastic sealing material can include base resin, filler, curing agent and additive. The base resin includes main agent (o-cresol formaldehyde type or alicyclic modified epoxy resin, etc.), flame-retardant resin (anhydride epoxy resin, etc.), etc., and is used to provide adhesion and thermosetting properties, etc. The curing agent can include linear phenolic resin, acid dregs, aromatic amine, etc., and is used to initiate the cross-linking reaction of the epoxy resin to form a stable structure. The filler can include silicon dioxide (crystalline type, molten type), alumina, aluminum nitride, calcium silicate, etc., and is used to adjust the coefficient of thermal expansion (CTE), improve mechanical strength and thermal conductivity. The additive can include curing accelerator (imidazole, tertiary amine, phosphorus compound, etc.), release agent (aliphatic acid, fatty acid and its salt, etc.), toughening agent (organic silicone rubber, butadiene rubber, etc.), coupling agent (organic silane, stearic acid, etc.), colorant (carbon black, dye, etc.), flame-retardant aid (antimony trioxide, etc.) and modifier, etc.

[0036] The plastic sealing material used in the embodiment can be epoxy plastic sealing material EMC (Epoxy Molding Compound).

[0037] In the embodiment, for the chip stacked in a stepped manner, the chips are connected to each other through the second bonding wires, and then connected to the redistribution layer through the first bonding wires on the other chips, so that the number of the second bonding wires directly connecting the chips to the redistribution layer is reduced, the signal interference caused by the second bonding wires to each other is reduced, and the product performance of the packaged chip is improved.

[0038] Referring to Figure 3 , Figure 3 FIG. 2 is a structural schematic diagram of a packaged chip structure according to a second embodiment of the present application.

[0039] The packaged chip structure includes a chip set 100, a bonding wire 200, a redistribution layer 300, a sealing structure 400 and a solder ball 500.

[0040] The other side of the redistribution layer 300, on which the chip set 100 is arranged, is provided with the solder ball 500. The chip 110 connected to the redistribution layer 300 is electrically connected to the solder ball 500 through the traces on the redistribution layer 300.

[0041] For the convenience of description, the chip set 100 is taken as an example to be described below. Figure 3In some embodiments, the direction perpendicular to the redistribution layer 300 is set as direction A, and the direction parallel to the redistribution layer 300 is set as direction B. The first side and the second side of the redistribution layer 300 are along the direction A, respectively. The chip group 100, the bonding wire 200, and the encapsulation structure 400 are disposed on the first side of the redistribution layer 300, and the solder ball 500 is disposed on the second side of the redistribution layer 300.

[0042] Other similar structures can refer to the description in the above embodiments.

[0043] In the above embodiments, the chip 110 closest to the redistribution layer 300 is spaced apart from the redistribution layer 300.

[0044] Further, the chip 110 closest to the redistribution layer 300 is electrically connected to the redistribution layer 300 through the second bonding wire 220 and the contact 120.

[0045] The chip 110 closest to the redistribution layer 300 in the chip group 100 is not in direct contact with the redistribution layer 300. The encapsulation structure 400 spaces the chip 110 away from the redistribution layer 300, so that the chip 110 closest to the redistribution layer 300 is electrically connected to the redistribution layer 300 only through the second bonding wire 200 and the contact 120. This is to better protect the chip 110 in the chip group 100.

[0046] In some embodiments, the second bonding wire 220 is perpendicular to the redistribution layer 300.

[0047] The second bonding wire 220 is perpendicular to the redistribution layer 300, which realizes a shorter signal path, helps to reduce signal delay and parasitic inductance / capacitance, and improves the use performance.

[0048] In the above embodiments, only the chip 110 closest to the redistribution layer 300 is electrically connected to the redistribution layer 300 through the second bonding wire 220 and the contact 120, and the rest of the chips 110 are not directly electrically connected to the redistribution layer 300 through the second bonding wire 220 and the contact 120. The chips 110 are electrically connected to each other through the first bonding wire 210 and the contact 120. The two chips connected by the first bonding wire 210 can be adjacent or not adjacent.

[0049] Referring to Figure 3 In the above embodiments, at least two chips 110 in the chip group 100 are disposed parallel to the redistribution layer 300.

[0050] Further, in some embodiments, at least two chips 100 in the chip group 100 are stacked in a direction perpendicular to the redistribution layer 300.

[0051] Specifically, when the chip set 100 is set, the chips 110 are placed along the direction B, and then stacked along the direction A. The redistribution layer is set along the direction B.

[0052] In some embodiments, the chips 110 in the chip set 100 can be stacked on the bottom chip 110 in a gradually staggered manner along the positive direction of the direction B, so as to expose the contacts 120 near the left edge of each chip 110 below the top chip.

[0053] In some embodiments, the chips 110 in the chip set 100 can be stacked on the bottom chip 110 in a gradually staggered manner along the negative direction of the direction B, so as to expose the contacts 120 near the right edge of each chip 110 below the top chip.

[0054] In some embodiments, at least two chips 110 in the chip set 100 are stacked by chip bonding. The chip bonding can include adhesive bonding, including using non-conductive adhesive to bond the chips. The non-conductive adhesive only provides mechanical fixation. The non-conductive adhesive can include DAF adhesive, which has excellent bonding performance and thermal conductivity performance, and can remain stable in a high-temperature environment, providing reliable mechanical connection and thermal management for the chips.

[0055] In some embodiments, when the chips in the chip set 100 are stacked in a stepped manner and there are at least three chips, the staggered offset distances between the chips are the same.

[0056] Referring to Figure 4 , Figure 4 FIG. 3 is a structural schematic diagram of a third embodiment of the packaged chip structure of the present application.

[0057] The packaged chip structure includes a chip set 100, a bonding wire 200, a redistribution layer 300, a sealing structure 400, and a solder ball 500.

[0058] The bonding wire includes a first bonding wire 210 and a second bonding wire 220. The first bonding wire 210 connects two chips 110 through the contacts 120. The second bonding wire 220 is arranged perpendicular to the redistribution layer 300 and connects the chip 110 and the redistribution layer 300 through the contacts 120. In addition to the chip 110 closest to the redistribution layer 300 being electrically connected to the redistribution layer 300 by the second bonding wire 220, other chips 110 can also be electrically connected to the redistribution layer 300 by the second bonding wire 220. However, the more second bonding wires 220 are arranged, the more serious the signal interference between the second bonding wires 220 will be, and the greater the impact on the integrity of the transmitted signals will be.

[0059] Referring to Figure 5 , Figure 5Fig. 4 is a structural schematic diagram of a fourth embodiment of the packaged chip structure of the present application.

[0060] The packaged chip structure comprises a chip set 100, a bonding wire 200, a redistribution layer 300, a sealing structure 400, and a solder ball 500.

[0061] The bonding wire comprises a first bonding wire 210 and a second bonding wire 220. The first bonding wire 210 connects two chips 110 through the contact 120. The second bonding wire 220 is arranged perpendicularly to the redistribution layer 300 and connects the chip 110 and the redistribution layer 300 through the contact 120. The two chips 110 connected by the first bonding wire 210 can be adjacent chips or non-adjacent chips. The fewer (in length or in number) the bonding wires used in packaging, the smaller the interference between the bonding wires and the smaller the impact on the integrity of the transmission signal.

[0062] In summary, for the stepped stacked chips in the packaged chip, the second bonding wire is used to electrically connect the adjacent chips, the chip can be connected to other chips through the second bonding wire, and then connected to the redistribution layer through the first bonding wire on the other chip, which reduces the number of the second bonding wires directly connecting the chip to the redistribution layer, reduces the signal interference caused by the second bonding wires to each other, and improves the product performance of the packaged chip.

[0063] In the several embodiments provided in the present application, it should be understood that the disclosed method and device can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the modules or units is only a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0064] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0065] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0066] The integrated units in the above other embodiments, if implemented in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0067] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation made by using the content of the specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A packaged chip, comprising: Comprising: a redistribution layer; a chip set disposed on one side of the redistribution layer, comprising at least two chips stacked in a stepped manner, contacts of the at least two chips are disposed on a side of the chips facing the redistribution layer; bonding wires, comprising first bonding wires and second bonding wires, the first bonding wires electrically connecting two of the chips in the chip set through the contacts, the second bonding wires electrically connecting one of the chips and the redistribution layer, each of the chips is electrically connected to the redistribution layer through the second bonding wires, or the first bonding wires and the second bonding wires; a sealing structure covering the chip set and the bonding wires.

2. The chip package of claim 1, wherein The other side of the redistribution layer is provided with tin balls, the chips connected to the redistribution layer are electrically connected to the tin balls through traces on the redistribution layer.

3. The chip package of claim 1, wherein The chip closest to the redistribution layer is spaced apart from the redistribution layer.

4. The chip package of claim 3, wherein The chip closest to the redistribution layer is electrically connected to the redistribution layer through the second bonding wires and the contacts.

5. The chip package of claim 1, wherein The second bonding wires are perpendicular to the redistribution layer.

6. The chip package of claim 1, wherein The at least two chips are disposed parallel to the redistribution layer.

7. The chip package of claim 6, wherein The at least two chips are stacked in a direction perpendicular to the redistribution layer.

8. The chip package of claim 1, wherein The at least two chips are stacked by chip bonding.

9. The chip package of claim 1, wherein When the chips stacked in a stepped manner are at least three, the misalignment distances between the chips are the same.

10. The chip package of claim 1, wherein The two chips connected by the second bonding wires are adjacent chips.

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