Asynchronous frequency raising decoding circuit based on local master clock

Abstract

The utility model discloses an asynchronous frequency-raising decoding circuit based on a local main clock, and relates to the field of audio signal processing. The circuit comprises a low-quality IIS / DSD output module, a DSP chip and a DAC digital analog converter which are connected in sequence. According to the utility model, the problems of poor IIS / DSD quality, large time base jitter and serious noise of digital audio decoding are solved, and the index, the actual performance and the hearing feeling of a DA chip are improved. Through the regeneration of the FIFO and the local clock and the DSP processing, the quality of the output IIS / DSD is greatly improved, and the jitter is lower than 5ps, so that the rear-end DA process obtains more excellent analog output.

Description

Technical Field

[0001] This utility model relates to the field of audio signal processing, and more specifically to an asynchronous upsampling decoding circuit based on a local master clock. Background Technology

[0002] While low-quality IIS output may meet consumer needs in terms of output noise, clock accuracy, and clock-data matching precision, it falls short of high-end (Hi-Fi) or high-fidelity (Hi-End) requirements. Low-quality IIS directly impacts the performance of the DA chip and severely affects the realism and liveliness of the listening experience. Therefore, minimizing the impact on the DA chip and improving the realism and liveliness of the listening experience is a crucial area of ​​research for those skilled in the art. Utility Model Content

[0003] In view of this, the present invention provides an asynchronous upsampling decoding circuit based on a local master clock to solve the problems existing in the background art.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] An asynchronous upsampling decoding circuit based on a local master clock includes a low-quality IIS / DSD output module, a DSP chip, and a DAC digital-to-analog converter connected in sequence.

[0006] Optionally, a FIFO data buffer is also included, through which the low-quality IIS / DSD output module is connected to the DAC digital-to-analog converter.

[0007] Optionally, a resampling circuit is also included, and the DSP chip is connected to the resampling circuit.

[0008] Optionally, a pre-amplifier digital filter circuit may also be included, and the DSP chip is connected to the pre-amplifier digital filter circuit.

[0009] Optionally, the DSP chip is an AK4137.

[0010] Optionally, the power supply for the DSP chip and the DAC digital-to-analog converter is a HiFi power supply.

[0011] As can be seen from the above technical solution, compared with the prior art, this utility model discloses an asynchronous upsampling decoding circuit based on a local master clock, which solves the problems of poor IIS / DSD quality, large time base jitter, and severe noise in digital audio decoding, and improves the performance, actual performance, and listening experience of the DA chip. Through FIFO and DSP processing of local clock regeneration, the output IIS / DSD quality is greatly improved, with jitter below 5ps, thereby enabling the back-end DA process to obtain a better analog output. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of this utility model;

[0014] Figure 2 This is a schematic diagram of the DSP chip of this utility model;

[0015] Figure 3 This is a schematic diagram illustrating the principle of this utility model. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0017] See Figures 1-3 This utility model discloses an asynchronous upsampling decoding circuit based on a local master clock, including a low-quality IIS / DSD output module, a DSP chip, and a DAC digital-to-analog converter connected in sequence.

[0018] The DSP chip is AK4137.

[0019] Furthermore, this embodiment also includes a FIFO data buffer, through which the low-quality IIS / DSD output module and the DAC digital-to-analog converter are connected.

[0020] Furthermore, this embodiment also includes a resampling circuit, and the DSP chip is connected to the resampling circuit.

[0021] Furthermore, this embodiment also includes a pre-amplifier digital filter circuit, and the DSP chip is connected to the pre-amplifier digital filter circuit.

[0022] Furthermore, the power supply for both the DSP chip and the DAC digital-to-analog converter is a Hi-Fi power supply. The DSP and DAC power supplies must be clean, independent Hi-Fi power supplies to isolate them from the influence of dirty IIS / DSD output modules.

[0023] Furthermore, the DSP chip is used to independently implement the asynchronous IIS / DSD generation process, while sharing the same master clock with the DAC. The master clock and the output IIS / DSD must be synchronized, and the data is driven by the master clock. If SRC is involved, it is equivalent to the ASRC process.

[0024] If upsampling or similar processes are involved, a Digital Filter (resampling) is required. This allows for the direct use of NOS DA to achieve higher DA speeds and a more comprehensive DA solution.

[0025] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0026] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An asynchronous upsampling decoding circuit based on a local master clock, characterized in that, It includes a low-quality IIS / DSD output module, a DSP chip, and a DAC digital-to-analog converter connected in sequence.

2. The asynchronous upsampling decoding circuit based on a local master clock according to claim 1, characterized in that, It also includes a FIFO data buffer, through which the low-quality IIS / DSD output module is connected to the DAC digital-to-analog converter.

3. The asynchronous upsampling decoding circuit based on a local master clock according to claim 1, characterized in that, It also includes a resampling circuit, and the DSP chip is connected to the resampling circuit.

4. The asynchronous upsampling decoding circuit based on a local master clock according to claim 1, characterized in that, It also includes a pre-amplifier digital filter circuit, and the DSP chip is connected to the pre-amplifier digital filter circuit.

5. The asynchronous upsampling decoding circuit based on a local master clock according to claim 1, characterized in that, The DSP chip is AK4137.

6. The asynchronous upsampling decoding circuit based on a local master clock according to claim 1, characterized in that, The DSP chip and the DAC digital-to-analog converter are powered by a HIFI ultra-low noise power supply.

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