Fuse trimming circuit with false trigger protection function

Abstract

The utility model relates to an analog integrated circuit design, in particular to a fuse trimming circuit with a false trigger protection function, which comprises a fuse power supply module, a power supply switching module and a programming module, the fuse power supply module is used for supplying power to the power supply switching module and the programming module; the power supply switching module is used for power supply switching of the programming module; the programming module is used for trimming the fuse by using the output signal of the power supply switching module based on an external input signal and reading a trimming result; according to the technical scheme provided by the utility model, the defects of weak anti-interference capability and large occupied chip area of the circuit in the prior art can be effectively overcome.

Description

Technical Field

[0001] This utility model relates to analog integrated circuit design, specifically to a fuse adjustment circuit with false triggering protection function. Background Technology

[0002] The design of various high-precision references, operational amplifiers and other circuits in analog devices requires high precision in circuit parameters. However, the devices manufactured in factories have certain process deviations and cannot meet the requirements of high-precision circuit parameters.

[0003] Fuse trimming circuitry enables the trimming of devices based on process deviations and parameter requirements after wafer fabrication. Integrated within the device, the circuitry uses external excitation signals to program the fuses. Once programmed, the results are transmitted to the relevant internal module to adjust the circuit parameters.

[0004] The existing fuse adjustment circuit does not have a false trigger protection function, resulting in weak anti-interference capability and easy false triggering. At the same time, the existing fuse adjustment circuit occupies a large chip area. Utility Model Content

[0005] (a) Technical problems to be solved

[0006] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a fuse adjustment circuit with false trigger protection function, which can effectively overcome the defects of weak anti-interference ability and large chip area of ​​the existing technology.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, this utility model provides the following technical solution:

[0009] A fuse adjustment circuit with false trigger protection function includes a fuse power module, a power switching module and a programming module;

[0010] The fuse power module is used to provide power to the power switching module and the programming module;

[0011] Power switching module, used for power switching of the programming module;

[0012] The programming module adjusts the fuse based on the external input signal and the output signal of the power switching module, and reads out the adjustment result.

[0013] Preferably, the fuse power module includes MOSFETs P1, P2, P3, P4, P5, N1, N2, N3, and N4.

[0014] The gate of the MOS transistor P1 is connected to the external input signal PVB0, the source of the MOS transistor P1 is connected to the external input signal VIN, and the drain of the MOS transistor P1 is connected to the source of the MOS transistors P2 and P3.

[0015] The gate of the MOS transistor P2 is connected to the external input signal VBG, the drain of the MOS transistor P2 is connected to the gate and drain of the MOS transistor N1 and the gate of the MOS transistor N2, and the source of the MOS transistor N1 and the MOS transistor N2 is connected to GND.

[0016] The gate of the MOS transistor P3 is connected to resistors R1 and R2, the drain of the MOS transistor P3 is connected to the drain of the MOS transistor N2 and resistor R3, and resistor R3 is connected to GND through capacitor C1.

[0017] The gate of MOS transistor N3 is connected to the drain of MOS transistor P3, the source of MOS transistor N3 is connected to GND, and the drain of MOS transistor N3 is connected to the source of MOS transistor N4.

[0018] The gate of MOSFET N4 is connected to the external input signal EN. The drain of MOSFET N4 is connected to the gate and drain of MOSFET P4 and the gate of MOSFET P5. The sources of MOSFET P4 and MOSFET P5 are connected to the external input signal VIN. The drain of MOSFET P5 is connected to GND through resistors R1 and R2. The drain of MOSFET P5 is connected to GND through capacitor C2. The drain of MOSFET P5 outputs the output signal VCC.

[0019] Preferably, the power switching module includes MOSFET P6, MOSFET P7, MOSFET N5, MOSFET N6 and MOSFET N7;

[0020] The gate of the MOS transistor P6 is connected to the output signal VCC of the fuse power module through resistor R4. The gate of the MOS transistor P6 is connected to the drain of the MOS transistor N5 through resistor R7. The source of the MOS transistor P6 outputs the output signal PWR, the drain of the MOS transistor P7 and the drain of the MOS transistor P6. The drain of the MOS transistor P6 is connected to the output signal VCC of the fuse power module.

[0021] The gate of the MOS transistor N5 is connected to the external input signal EN1, and the source of the MOS transistor N5 is connected to GND.

[0022] The gate of the MOS transistor P7 is connected to resistors R5 and R6, and the source of the MOS transistor P7 and resistor R5 are connected to the external input signal VIN.

[0023] The gate of the MOS transistor N6 is connected to the external input signal EN2, and the source of the MOS transistor N6 is connected to GND.

[0024] The gate of the MOSFET N7 is connected to the external input signal EN3, the source of the MOSFET N7 is connected to GND, and the drain of the MOSFET N7 is connected to the resistor R6.

[0025] Preferably, the programming module includes a first level conversion module, a second level conversion module, an 8-bit anti-accidental touch circuit, an RS latch, a 6-bit counter, multiple 6-input NAND gates, multiple fuse modules, and multiple READ modules;

[0026] The input terminal of the first level conversion module receives an external input signal CLK, and the output terminal of the first level conversion module is connected to the input terminal of an 8-bit anti-accidental touch circuit. The output terminal of the 8-bit anti-accidental touch circuit is connected to the input terminal of an RS latch.

[0027] The input terminal of the second level conversion module receives the external input signal PG, and the output terminal of the second level conversion module is connected to the input terminal of the RS latch and the fuse module;

[0028] The output of the RS latch is connected to the input of a 6-bit counter. The output of the 6-bit counter is connected to the input of a 6-input NAND gate. The output of the 6-input NAND gate is connected to the input of its corresponding fuse module. The output of the fuse module is connected to the input of its corresponding READ module. The READ module receives an external input signal TRG and outputs an output signal ADJ. Finally, the READ module outputs a latch signal LOCK to the first level conversion module and the second level conversion module.

[0029] Among them, there are 33 input NAND gates, fuse modules, and READ modules.

[0030] (III) Beneficial Effects

[0031] Compared with the prior art, the fuse adjustment circuit with false trigger protection provided by this utility model has an external excitation signal that enters the adjustment mode only after passing through 8 anti-false trigger bit waveforms, which makes the overall circuit have stronger anti-interference ability. In addition, the application scope of this solution is wider and is not limited to resistor adjustment. At the same time, this solution occupies a smaller chip area. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a circuit diagram of the fuse power supply module in this utility model;

[0034] Figure 2 This is a circuit diagram of the power switching module in this utility model;

[0035] Figure 3 This is a circuit diagram of the programming module in this utility model;

[0036] Figure 4 This is a timing diagram for fuse adjustment according to this utility model. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0038] A fuse adjustment circuit with false trigger protection function includes a fuse power module, a power switching module and a programming module;

[0039] The fuse power module is used to provide power to the power switching module and the programming module;

[0040] Power switching module, used for power switching of the programming module;

[0041] The programming module adjusts the fuse based on the external input signal and the output signal of the power switching module, and reads out the adjustment result.

[0042] like Figure 1 As shown, the fuse power module includes MOSFETs P1, P2, P3, P4, P5, N1, N2, N3, and N4.

[0043] The gate of MOSFET P1 is connected to the external input signal PVB0, the source of MOSFET P1 is connected to the external input signal VIN, and the drain of MOSFET P1 is connected to the source of MOSFETs P2 and P3.

[0044] The gate of MOSFET P2 is connected to the external input signal VBG. The drain of MOSFET P2 is connected to the gate and drain of MOSFET N1 and the gate of MOSFET N2. The sources of MOSFET N1 and MOSFET N2 are connected to GND.

[0045] The gate of MOSFET P3 is connected to resistors R1 and R2, and the drain of MOSFET P3 is connected to the drain of MOSFET N2 and resistor R3. Resistor R3 is connected to GND through capacitor C1.

[0046] The gate of MOSFET N3 is connected to the drain of MOSFET P3, the source of MOSFET N3 is connected to GND, and the drain of MOSFET N3 is connected to the source of MOSFET N4.

[0047] The gate of MOSFET N4 is connected to the external input signal EN. The drain of MOSFET N4 is connected to the gate and drain of MOSFET P4 and the gate of MOSFET P5. The sources of MOSFET P4 and MOSFET P5 are connected to the external input signal VIN. The drain of MOSFET P5 is connected to GND through resistors R1 and R2. The drain of MOSFET P5 is connected to GND through capacitor C2. The drain of MOSFET P5 outputs the output signal VCC.

[0048] The external input signals of the fuse power module include PVB0, VIN, VBG, and EN, and the output signal includes VCC. The first stage of the fuse power module is a 5-transistor operational amplifier, consisting of MOSFETs P1, P2, P3, N1, and N2. MOSFETs P2 and P3 are the input pair. The second stage of the fuse power module uses MOSFET N3 for secondary amplification. MOSFET N4 is the enable transistor, switched by the external enable signal EN. Current folding is achieved through a current mirror composed of MOSFETs P4 and P5, finally outputting the output signal VCC. The output voltage VCC is divided by resistors R1 and R2 and fed back to the gate of MOSFET P3 for voltage regulation. Resistor R3 and capacitor C1 form a zero-point compensation circuit pole, and capacitor C2 prevents output voltage overshoot.

[0049] like Figure 2 As shown, the power switching module includes MOSFETs P6, P7, N5, N6, and N7.

[0050] The gate of MOSFET P6 is connected to the output signal VCC of the fuse power module through resistor R4. The gate of MOSFET P6 is connected to the drain of MOSFET N5 through resistor R7. The source of MOSFET P6 outputs the output signal PWR, the drain of MOSFET P7 and the drain of MOSFET P6. The drain of MOSFET P6 is connected to the output signal VCC of the fuse power module.

[0051] The gate of MOSFET N5 is connected to the external input signal EN1, and the source of MOSFET N5 is connected to GND.

[0052] The gate of MOSFET P7 is connected to resistors R5 and R6, and the source of MOSFET P7 and resistor R5 are connected to the external input signal VIN.

[0053] The gate of MOSFET N6 is connected to the external input signal EN2, and the source of MOSFET N6 is connected to GND;

[0054] The gate of MOSFET N7 is connected to the external input signal EN3, the source of MOSFET N7 is connected to GND, and the drain of MOSFET N7 is connected to the resistor R6.

[0055] The external input signals of the power switching module include VIN, EN1, EN2, and EN3, and the output signal includes PWR. During the programming stage, when the power is first turned on and the TRG signal changes from low to high, the EN3 signal is low and MOSFET P7 is not turned on. At the same time, the EN1 signal is high and MOSFET N5 is turned on. The EN2 signal is low and MOSFET N6 is not turned on. The PWR signal is provided by the output voltage VCC generated by the fuse power module, which is about 2.3V. This period is used to read out the initial state of the adjustment signal.

[0056] When the TRG signal changes from high to low, the EN1 signal changes from high to low, and MOSFETs N5 and P6 are not turned on. When the EN2 signal changes from low to high, MOSFET N6 is turned on, the PWR signal is pulled low, and VCC remains unchanged at 2.3V. This period is the waiting period, waiting for the CLK signal to arrive.

[0057] When the CLK signal arrives, after 8 anti-accidental touch bit waveforms, the EN3 signal changes from low to high, the EN2 signal changes from high to low, and the EN1 signal changes from low to high. MOSFETs P6 and P7 are both turned on. At this time, PWR+V... ds 7 =VIN,VCC+V ds 6 +V ds 7=VIN. Since the MOSFETs P6 and P7 are large in size and have low on-resistance, the voltage drop across the MOSFETs P6 and P7 is small. Therefore, VIN≈PWR≈VCC can be considered as the programming stage. At this time, the programming power supply is provided by the PWR signal.

[0058] like Figure 3 As shown, the programming module includes a first level conversion module, a second level conversion module, an 8-bit anti-accidental touch circuit, an RS latch, a 6-bit counter, multiple 6-input NAND gates, multiple fuse modules, and multiple READ modules;

[0059] The input terminal of the first level conversion module receives the external input signal CLK, and the output terminal of the first level conversion module is connected to the input terminal of the 8-bit anti-accidental touch circuit. The output terminal of the 8-bit anti-accidental touch circuit is connected to the input terminal of the RS latch.

[0060] The input terminal of the second level conversion module receives the external input signal PG, and the output terminal of the second level conversion module is connected to the input terminal of the RS latch and the fuse module.

[0061] The output of the RS latch is connected to the input of a 6-bit counter. The output of the 6-bit counter is connected to the input of a 6-input NAND gate. The output of the 6-input NAND gate is connected to the input of its corresponding fuse module. The output of the fuse module is connected to the input of its corresponding READ module. The READ module receives the external input signal TRG and outputs the signal ADJ. The last READ module outputs the latch signal LOCK to the first level conversion module and the second level conversion module.

[0062] Among them, there are 33 input NAND gates, fuse modules, and READ modules.

[0063] The external input signals of the programming module include CLK, PG and TRG, and the output signals include ADJ1 to ADJ32. The CLK signal is the bit selection signal of the programming module, the PG signal is the programming signal of the programming module, and the TRG signal is the enable signal of the programming module to read the adjustment result.

[0064] First, the CLK signal is normalized by the first level conversion module. The output signal of the first level conversion module is sent to the 8-bit anti-accidental touch circuit to shield the accidental touch signal. The output signal of the 8-bit anti-accidental touch circuit is sent to the RS latch. Similarly, the PG signal is normalized by the second level conversion module and then enters the RS latch. The two signals are generated by the RS latch to produce the CLK1 signal, which is used as the input of the 6-bit counter. The 6-bit counter produces outputs Q0 to Q5. The output signals act on each 6-input NAND gate to generate the selection signal for each fuse module, for a total of 33 selection signals. The selection signals and the FIRE signal output by the second level conversion module enter the fuse module together. The FIRE signal is a burn signal. When the rising edge of the FIRE signal is aligned with the rising edge of the output signal of the 6-input NAND gate, the fuse inside the fuse module is blown, and the output of the fuse module is high. The READ module reads the state of the fuse module and generates the corresponding ADJ signal to adjust the internal modules of the chip.

[0065] After the entire fuse adjustment process is completed, the fuse33 module is blown, and the fuse33 module outputs a high level. The last READ module reads the result and sends it to the first level conversion module and the second level conversion module to turn off the level conversion module, thus ending the fuse adjustment.

[0066] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A fuse trimming circuit having a mis-trigger protection function, characterized by: The fuse power module, the power switch module and the burning module are included. The fuse power module is used for providing power for the power switch module and the burning module. The power switch module is used for power switching of the burning module. The burning module adjusts the fuse based on the external input signal and reads the adjustment result by using the output signal of the power switch module.

2. The fuse trimmer circuit having a misfire protection function according to claim 1, characterized by: The fuse power module includes MOS tubes P1, P2, P3, P4, P5, N1, N2, N3 and N4. The gate of the MOS tube P1 is connected to the external input signal PVB0, the source of the MOS tube P1 is connected to the external input signal VIN, and the drain of the MOS tube P1 is connected to the sources of the MOS tubes P2 and P3. The gate of the MOS tube P2 is connected to the external input signal VBG, the drain of the MOS tube P2 is connected to the gate and drain of the MOS tube N1 and the gate of the MOS tube N2, and the sources of the MOS tubes N1 and N2 are connected to GND. The gate of the MOS tube P3 is connected to resistors R1 and R2, the drain of the MOS tube P3 is connected to the drain of the MOS tube N2 and resistor R3, and the resistor R3 is connected to GND through capacitor C1. The gate of the MOS tube N3 is connected to the drain of the MOS tube P3, the source of the MOS tube N3 is connected to GND, and the drain of the MOS tube N3 is connected to the source of the MOS tube N4. The gate of the MOS tube N4 is connected to the external input signal EN, the drain of the MOS tube N4 is connected to the gate and drain of the MOS tube P4 and the gate of the MOS tube P5, the sources of the MOS tubes P4 and P5 are connected to the external input signal VIN, the drain of the MOS tube P5 is connected to GND through resistors R1 and R2, the drain of the MOS tube P5 is connected to GND through capacitor C2, and the drain of the MOS tube P5 outputs the output signal VCC.

3. The fuse trimmer circuit having a misfire protection function according to claim 1, characterized by: The power switch module includes MOS tubes P6, P7, N5, N6 and N7. The gate of the MOS tube P6 is connected to the output signal VCC of the fuse power module through resistor R4, the gate of the MOS tube P6 is connected to the drain of the MOS tube N5 through resistor R7, the source of the MOS tube P6 outputs the output signal PWR, the drain of the MOS tube P7 and the drain of the MOS tube P6, and the drain of the MOS tube P6 is connected to the output signal VCC of the fuse power module. The gate of the MOS tube N5 is connected to the external input signal EN1, and the source of the MOS tube N5 is connected to GND. The gate of the MOS tube P7 is connected to resistors R5 and R6, and the source of the MOS tube P7 is connected to the external input signal VIN. The gate of the MOS tube N6 is connected to the external input signal EN2, and the source of the MOS tube N6 is connected to GND. The gate of the MOS transistor N7 is connected to an external input signal EN3, the source of the MOS transistor N7 is connected to GND, and the drain of the MOS transistor N7 is connected to the resistance R6.

4. The fuse trimmer circuit having a misfire protection function according to claim 1, characterized by: The burning and writing module comprises a first level conversion module, a second level conversion module, an 8-bit anti-misoperation circuit, an RS latch, a 6-bit counter, a plurality of 6-input NAND gates, a plurality of fuse modules and a plurality of READ modules. The input end of the first level conversion module is connected to an external input signal CLK, the output end of the first level conversion module is connected to the input end of the 8-bit anti-misoperation circuit, and the output end of the 8-bit anti-misoperation circuit is connected to the input end of the RS latch. The input end of the second level conversion module is connected to an external input signal PG, and the output end of the second level conversion module is connected to the input end of the RS latch and the fuse module. The output end of the RS latch is connected to the input end of the 6-bit counter, the output end of the 6-bit counter is connected to the input end of the 6-input NAND gate, the output end of the 6-input NAND gate is connected to the input end of the corresponding fuse module, the output end of the fuse module is connected to the input end of the corresponding READ module, the input end of the READ module is connected to an external input signal TRG, the READ module outputs an output signal ADJ, and the last READ module outputs a latch signal LOCK to the first level conversion module and the second level conversion module. Among them, the 6-input NAND gate, the fuse module and the READ module are all 33.

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