Semiconductor structure and packaging structure

Abstract

The utility model provides a semiconductor structure and a packaging structure, the semiconductor structure comprises a metal loop line and a plurality of bonding pads, the bonding pads are arranged above the metal loop line, a plurality of grooves penetrating through the metal loop line are arranged in the metal loop line which is not covered by the bonding pads, and the bonding pads are arranged in the grooves. And no groove is formed in the metal loop wire covered by the bonding pad. According to the utility model, the plurality of grooves penetrating through the metal loop wire are arranged in the metal loop wire which is not covered by the bonding pad, so that the current effect and the thermal stress effect of the metal loop wire are relieved, and meanwhile, no groove is arranged in the metal loop wire which is covered by the bonding pad, so that the height difference of a film layer is not introduced, and the reliability of the film layer is improved. Therefore, the film layer in the bonding pad area can be ensured to be highly flat, and cracks after bonding pad routing caused by overlarge local stress are avoided, so that the packaging yield is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor structure and a packaging structure. Background Technology

[0002] After chip manufacturing, when used in a circuit system, it needs to be electrically connected to the circuit board or other chips via pins. Wire bonding is a common chip packaging connection method, where the two ends of the metal wire are bonded to the chip pad and the lead frame, respectively. To save chip area, I / O (input / output) is designed as a CUP (circuit under pad). In CUP-type I / O units, the device and metal traces are placed under the pad. During the wire bonding process, stress is created in and below the pad area. If the stress is too high or the stack-up is uneven, the stress can cause cracks, affecting the chip's functionality and reliability.

[0003] The metal traces below the pads are connected to form power / ground rings. When the chip is powered on, a relatively large current flows through these rings. In order to alleviate the adverse effects such as thermal stress and electromigration caused by the large current, slot patterns are drawn on these large metal traces along the direction of current flow.

[0004] The slots on the power loops or ground loops below the IO pads can affect the flatness of the subsequent film layers. When stress is generated during the bonding of the pads, it can easily cause cracks in the pad metal, resulting in a loss of yield after packaging. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor structure and packaging structure that can alleviate the current effect and thermal stress effect caused by the metal ring, while not causing uneven film height at the pad position and not affecting the wire bonding stress distribution, thereby improving the packaging yield.

[0006] To solve the above-mentioned technical problems, this utility model provides a semiconductor structure, including: a metal ring and a plurality of pads, wherein the pads are located above the metal ring, and a plurality of grooves penetrating the metal ring are provided in the part of the metal ring not covered by the pads, while no grooves are provided in the part of the metal ring covered by the pads.

[0007] Optionally, the metal loop may include a power loop and / or a ground loop.

[0008] Optionally, the pads include input and output pads.

[0009] Optionally, the groove is located within the metal ring between adjacent pads.

[0010] Optionally, the groove has a strip-shaped cross-section.

[0011] Optionally, the extension direction of the strip is consistent with the extension direction of the metal ring.

[0012] Optionally, a plurality of the grooves are regularly arranged within the metal ring not covered by the pads.

[0013] Optionally, a plurality of the grooves are regularly arranged in a row and column direction to form an array, wherein the column direction is the extension direction of the metal ring and the row direction is a direction perpendicular to the extension direction of the metal ring.

[0014] Optionally, the plurality of grooves are regularly arranged in the column direction, each column being offset by a set distance relative to the adjacent column in the column direction, wherein the column direction is the extension direction of the metal ring, and the row direction is a direction perpendicular to the extension direction of the metal ring.

[0015] Accordingly, this utility model also provides a packaging structure, including the semiconductor structure described above.

[0016] The semiconductor structure and packaging structure provided by this utility model include a metal ring and multiple pads. The pads are located above the metal ring. Multiple grooves penetrating the metal ring are provided within the portion of the metal ring not covered by the pads, while no grooves are provided within the portion of the metal ring covered by the pads. The unexpected technical effect of this utility model is that the multiple grooves penetrating the metal ring within the portion not covered by the pads alleviate the current effect and thermal stress effect of the metal ring. Simultaneously, the absence of grooves within the portion of the metal ring covered by the pads prevents the introduction of film layer height differences, ensuring a flat film layer height within the pad area and avoiding cracks after wire bonding caused by excessive local stress, thereby improving packaging yield. Attached Figure Description

[0017] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

[0018] Figure 1 This is a schematic diagram of a semiconductor structure.

[0019] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention.

[0020] Figure 3This is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures:

[0022] 10-Pad; 20-Metallic ring; 21-Groove. Detailed Implementation

[0023] As described in the background art, in order to save chip area, the input / output unit is designed in the CUP manner, that is, metal traces are placed under the input / output pads, and the metal traces under the pads are connected to form a loop. In order to alleviate the adverse effects such as thermal stress and electromigration caused by the large current of the metal loop, it is necessary to cut grooves on the metal loop to form a groove that runs through the metal loop. Figure 1 This is a schematic diagram of a semiconductor structure. Please refer to it. Figure 1 As shown, the semiconductor structure includes a metal ring 20 and a pad 10. The metal ring 20 is located below the pad 10 to save chip area. Multiple grooves 21 are provided inside the metal ring 20 to avoid current and thermal stress effects when the chip is powered on. However, because the grooves 21 are formed inside the metal ring 20 below the pad 10, the film layer where the metal ring 20 is located has a height difference and the film layer is uneven. This causes excessive local stress when wire bonding is performed on the pad 10, which leads to metal cracking of the pad 10.

[0024] However, if the groove 21 is removed, the metal ring 10 film layer below the pad 10 will become flat, and the stress concentration and pad cracking during wire bonding will be significantly improved. However, the absence of the groove 21 in the metal ring 10 will affect the uniformity of the current.

[0025] To address the aforementioned problems, this utility model provides a semiconductor structure, comprising: a metal ring and a plurality of pads, wherein the pads are located above the metal ring, and a plurality of grooves penetrating the metal ring are provided within the metal ring not covered by the pads, while no grooves are provided within the metal ring covered by the pads.

[0026] This invention mitigates the current and thermal stress effects of the metal ring by providing multiple grooves penetrating the metal ring outside the pads. Meanwhile, the metal ring covered by the pads does not have grooves, thus avoiding the introduction of film height differences and ensuring a flat film height within the pad area. This prevents cracks after wire bonding caused by excessive local stress, thereby improving the packaging yield.

[0027] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0028] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used in this invention, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used in this invention, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used in this invention, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0029] Figure 2 This is a schematic diagram of a semiconductor structure provided in one embodiment of the present invention. Please refer to it. Figure 2 As shown, the semiconductor structure provided in this embodiment of the present invention includes: a metal ring 20 and a plurality of pads 10. The pads 10 are located above the metal ring 20. The metal ring 20 not covered by the pads 10 is provided with a plurality of grooves 21 penetrating the metal ring 20. The metal ring 20 covered by the pads 10 is not provided with grooves.

[0030] In this embodiment, multiple grooves 21 (i.e., metal wire slots) are provided through the metal ring 20 not covered by the pad 10, thereby optimizing the current effect and thermal stress effect of the metal ring during power-on operation. At the same time, no grooves are provided in the metal ring 20 covered by the pad 10, so that no difference in film height is introduced, which can ensure that the film height within the area of ​​the pad 10 is flat and avoid cracks in the pad 10 after wire bonding caused by excessive local stress.

[0031] In one embodiment of this utility model, the metal ring 20 includes a power ring and / or a ground ring, but is not limited to these; the metal ring 20 may also include other rings. In this embodiment, no groove needs to be provided in any metal ring 20 located below the pad 10, that is, no slot needs to be made in the metal ring 20 located below the pad 10, thereby ensuring the flatness of the film layer of the metal ring 20.

[0032] In one embodiment of this utility model, the pad 10 includes input and output pads, but it is not limited to these; it can also be any pad in other semiconductor structures that requires a CUP mode.

[0033] It should be noted that in this utility model, the pad 10 can be any pad required in the semiconductor structure, and the metal ring 20 can be any metal ring in the semiconductor structure. The structure described in this utility model can be adopted when the pad 10 is located above the metal ring 20. Multiple grooves 21 penetrating the metal ring 20 are provided in the metal ring 20 not covered by the pad 10, and no grooves are provided in the metal ring 20 covered by the pad 10. This alleviates the current effect and thermal stress effect of the metal ring 20, while preventing unevenness of the film layer height at the position of the pad 10 and not affecting the wire bonding stress distribution.

[0034] In one embodiment of this invention, the groove 21 is located within the metal ring 20 between adjacent pads 10. In another embodiment of this invention, the groove 21 is located not only within the metal ring 20 between adjacent pads 10, but also within the metal ring 20 at the edge of the pad 10 (the pad 10 itself is located at the edge). The groove 21 can be located in any area of ​​the metal ring 20 not covered by the pads 10.

[0035] In one embodiment of this utility model, the cross-section of the groove 21 is strip-shaped, and the extending direction of the strip can be consistent with the extending direction of the metal ring 20, or the extending direction of the strip can be consistent with the current direction within the metal ring 20. Please refer to... Figure 2 As shown, the metal ring 20 extends vertically, and the strip-shaped groove 21 also extends vertically, but it is not limited to this. Furthermore, the cross-section of the groove 21 can also be any other suitable shape.

[0036] In one embodiment of this utility model, a plurality of grooves 21 are regularly arranged within the metal ring 20 not covered by the pads 10. For example, the plurality of grooves 21 can be regularly arranged in the row and column directions to form a trench array, or the plurality of grooves 21 can be regularly arranged in the row direction, with each row offset to the left or right by a predetermined distance relative to the previous row, or the plurality of grooves 21 can be regularly arranged in the column direction, with each column offset upward or downward by a predetermined distance relative to the column to its left.

[0037] In one embodiment, please refer to Figure 2 As shown, the plurality of grooves 21 are regularly arranged in an array in the row and column directions, wherein the column direction is the extension direction of the metal ring 20 (i.e., Figure 2 The vertical direction in the middle), the row direction is the direction perpendicular to the extension direction of the metal ring 20 (i.e., the vertical direction in the middle). Figure 2 (Horizontal direction). The distance between adjacent grooves 21 in the horizontal direction can be equal to the distance between adjacent grooves 21 in the vertical direction. Of course, the distance between adjacent grooves 21 in the horizontal direction can also be greater than or less than the distance between adjacent grooves 21 in the vertical direction. In this embodiment, the distance between adjacent grooves 21 in the horizontal direction is greater than the distance between adjacent grooves 21 in the vertical direction.

[0038] In another embodiment, please refer to Figure 3 As shown, the plurality of grooves 21 are regularly arranged in the column direction, and each column is offset by a set distance relative to the adjacent column in the column direction, wherein the column direction is the extension direction of the metal ring 20, and the row direction is the direction perpendicular to the extension direction of the metal ring 20. Figure 3 In the middle, from left to right, the second column is offset downwards by a set distance relative to the first column, and the third column is offset upwards by the same set distance relative to the second column. The first and third columns are arranged in the same way, and the second and fourth columns are arranged in the same way.

[0039] Each of the pads 10 may cover a portion of the plurality of metal rings 20. Please refer to [link / reference]. Figure 2 and Figure 3 As shown, each of the pads 10 covers a portion of the two metal rings 20. Within the different metal rings 20 not covered by the pads 10, the arrangement of the grooves 21 can be the same or different.

[0040] The size and number of the grooves 21 can be determined according to actual needs. Compared with the prior art, the area where the grooves 21 are set is reduced, and the size of the grooves 21 can be appropriately reduced. The grooves 21 are set to avoid the metal ring 20 being too wide or too large in area. The size and number of the grooves 21 can be set according to specific needs.

[0041] The semiconductor structure provided by this utility model includes a metal ring 20 and multiple pads 10. The pads 10 are located above the metal ring 20. Multiple grooves 21 penetrating the metal ring 20 are provided within the portion of the metal ring 20 not covered by the pads 10, while no grooves are provided within the portion of the metal ring 20 covered by the pads 10. The unexpected technical effect of this utility model is that the multiple grooves 21 penetrating the metal ring 20 not covered by the pads 10 alleviate the current effect and thermal stress effect of the metal ring. Simultaneously, the absence of grooves within the portion of the metal ring 20 covered by the pads 10 prevents the introduction of film layer height differences, ensuring a flat film layer height within the pad area and avoiding cracks after wire bonding caused by excessive local stress.

[0042] Accordingly, this utility model also provides a packaging structure, including the semiconductor structure described above.

[0043] In summary, the semiconductor structure and packaging structure provided by this utility model include a metal ring and multiple pads. The pads are located above the metal ring. Multiple grooves penetrating the metal ring are provided within the portion of the metal ring not covered by the pads, while no grooves are provided within the portion of the metal ring covered by the pads. The unexpected technical effect of this utility model is that the multiple grooves penetrating the metal ring within the portion not covered by the pads alleviate the current effect and thermal stress effect of the metal ring. Simultaneously, the absence of grooves within the portion of the metal ring covered by the pads prevents the introduction of film layer height differences, ensuring a flat film layer height within the pad area and avoiding cracks after wire bonding caused by excessive local stress, thereby improving packaging yield.

[0044] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A semiconductor structure, characterized by, The metal ring line comprises a power ring line and / or a ground ring line. The pads comprise input and output pads.

2. The semiconductor structure of claim 1, wherein, The recesses are arranged in the metal ring line between adjacent pads.

3. The semiconductor structure of claim 1, wherein, The recesses are arranged in the metal ring line between adjacent pads.

4. The semiconductor structure of claim 1, wherein, The recesses are arranged in the metal ring line between adjacent pads.

5. The semiconductor structure of claim 1, wherein, The recesses are arranged in the metal ring line between adjacent pads.

6. The semiconductor structure of claim 5, wherein, The recesses are arranged in the metal ring line between adjacent pads.

7. The semiconductor structure of claim 1, wherein, The recesses are arranged in the metal ring line between adjacent pads.

8. The semiconductor structure of claim 7, wherein, The recesses are arranged in the metal ring line between adjacent pads.

9. The semiconductor structure of claim 7, wherein, The recesses are arranged in the metal ring line between adjacent pads.

10. A package structure, characterized by, The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line between adjacent pads. The recesses are arranged in the metal ring line

Images