Array substrate, display panel and display device
By setting a double-layer light-shielding strip on the LCD panel array substrate and combining it with the transition electrode, the light leakage problem near the gate line and data line is solved, the aperture ratio and transmittance are improved, the black matrix width is reduced, and a higher display effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-04-07
AI Technical Summary
Existing LCD panels suffer from light leakage due to the electric field near the gate lines and data lines, resulting in a low aperture ratio. Furthermore, existing light-shielding structures require a wide black matrix to be set on the color filter substrate, which affects the transmittance.
A first light-shielding strip on a different layer than the signal line and a second light-shielding strip on the same layer are set on the array substrate. By combining the two light-shielding strips, the light-shielding range can be precisely controlled, the light leakage range can be reduced, and the potential can be stabilized by the transfer electrode to avoid voltage fluctuations.
It significantly improves the aperture ratio and transmittance of the display panel, reduces the width of the black matrix, and avoids light leakage or crosstalk problems caused by signal line short circuits and voltage fluctuations.
Smart Images
Figure CN224096102U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] Liquid crystal displays (LCDs) are highly favored and have become the mainstream display technology due to their low power consumption, high image quality, small size, and light weight. Currently, LCDs are mainly based on thin film transistor (TFT) LCDs, whose display panels typically include a color filter substrate, a TFT array substrate, and a liquid crystal layer disposed between the two substrates. Utility Model Content
[0003] This utility model provides an array substrate, a display panel, and a display device. The array substrate includes:
[0004] Substrate;
[0005] The signal line is located on one side of the substrate;
[0006] At least one first light-shielding strip is located on one side of the substrate and on a different layer from the signal line, extends in the same direction as the signal line, is located on at least one side of the signal line, and at least a portion of the orthographic projection of the first light-shielding strip on the substrate does not overlap with the orthographic projection of the signal line on the substrate.
[0007] In one possible implementation, the array substrate further includes a second light-shielding strip on the same layer as the signal line and located on at least one side of the signal line, wherein the extension direction of the second light-shielding strip is the same as the extension direction of the signal line and the two are spaced apart from each other.
[0008] In one possible implementation, the first light-shielding strip has a first outer edge on the side away from the signal line; the second light-shielding strip has a second outer edge on the side away from the signal line.
[0009] In the first and second light-shielding strips on the same side of the signal line, the orthographic projection of the second outer edge on the substrate is located on the side of the first outer edge on the substrate that is away from the signal line.
[0010] In one possible implementation, the first light-shielding strip has a third outer edge near the signal line; the second light-shielding strip has a fourth outer edge near the signal line.
[0011] In the first and second light-shielding strips on the same side of the signal line, the third outer edge is projected onto the substrate, and the fourth outer edge is projected onto the substrate on the side closer to the signal line.
[0012] In one possible implementation, in the first and second light-shielding strips on the same side of the signal line, the third outer edge, in the orthographic projection of the substrate, is located between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the signal line on the substrate.
[0013] In one possible implementation, the array substrate includes: a plurality of gate lines extending along a first direction, and a plurality of data lines extending along a second direction; the data lines are located on the side of the gate lines facing away from the substrate.
[0014] The signal line includes the grid line; the first light-shielding strip is in the same layer and material as the data line, and does not overlap with the data line.
[0015] In one possible implementation, the array substrate further includes: a common electrode layer located on the side of the gate line facing the substrate, and a pixel electrode layer located on the side of the data line away from the substrate; the common electrode layer includes: a plurality of common electrodes; the pixel electrode layer includes: a plurality of pixel electrodes, and a plurality of transition electrodes; wherein, the pixel electrode includes: a plurality of slits;
[0016] The second light-shielding strip is in direct contact with the common electrode and electrically connected; the first light-shielding strip is electrically connected to the common electrode through the adapter electrode.
[0017] In one possible implementation, the first light-shielding strip is provided on both sides of the grid line in the vertical extension direction;
[0018] The two first light-shielding strips on both sides of the grid line are electrically connected to the common electrode through different vias.
[0019] In one possible implementation, the array substrate further includes: a connecting strip on the same layer as the data line; the connecting strip connects the first light-shielding strips on both sides of the gate line.
[0020] In one possible implementation, the extension line of the connecting strip is projected onto the substrate and passes through the central region of the pixel electrode's projection onto the substrate.
[0021] In one possible implementation, the first light-shielding strip is provided on both sides of the grid line in the vertical extension direction;
[0022] Of the two first light-shielding strips on both sides of the grid line, only one of the first light-shielding strips is electrically connected to the common electrode through a via.
[0023] In one possible implementation, the extension line of the connecting strip is projected onto the substrate in orthographic projection, and overlaps with the edge region of the pixel electrode in orthographic projection onto the substrate.
[0024] In one possible implementation, the array substrate further includes: a first common trace that is on the same layer as the gate line and extends along the first direction;
[0025] The second light-shielding strips on one side of the grid line are integrally connected and reused as the first common trace; the second light-shielding strips on the other side of the grid line are spaced apart from each other.
[0026] In one possible implementation, the array substrate further includes: a pixel electrode layer located on the side of the gate line facing the substrate, and a common electrode layer located on the side of the data line away from the substrate; the pixel electrode layer includes: a plurality of pixel electrodes; the common electrode layer includes: a plurality of common electrodes; the common electrodes have a plurality of slits;
[0027] The array substrate further includes: a first trace on the same layer as the data line and extending along the second direction; the first light-shielding strips are all connected to the first trace.
[0028] In one possible implementation, the common electrode layer further includes: a common connection portion extending along the second direction; two adjacent common electrodes in the second direction are connected through the common connection portion;
[0029] The second light-shielding strip is in direct contact with the pixel electrode and electrically connected; the portion of the first trace projected onto the substrate overlaps with the portion of the common connection projected onto the substrate, and a hole is drilled at the overlapping position for connection.
[0030] In one possible implementation, the array substrate includes: a plurality of gate line groups extending along the first direction and arranged along the second direction; the orthographic projection of the gate line group on the substrate is located between the orthographic projections of two adjacent pixel electrode rows on the substrate; the gate line group includes two gate lines.
[0031] The common connection portion includes: a first sub-common portion, and a second sub-common portion connected to both sides of the first sub-common portion; the width of the first sub-common portion in the first direction is greater than the width of the second sub-common portion in the first direction; the common connection portion is connected to the first trace through the first sub-common portion;
[0032] The first sub-common portion is projected onto the substrate, and the gap between the two gate lines of the gate line group is located within the projection of the substrate.
[0033] In one possible implementation, the orthographic projection of the gate line onto the substrate and the orthographic projection of the data line onto the substrate intersect at a point;
[0034] The first light-shielding strip has a bend at the intersection, and at least a portion of the bend in the orthographic projection onto the substrate is located on the side of the grating line in the orthographic projection onto the substrate away from the intersection.
[0035] In one possible implementation, the array substrate further includes: a transistor; the transistor includes: a control electrode, a first electrode, a second electrode, and an active pattern;
[0036] The control electrode reuses the gate line; at least a portion of the first electrode extends in the same direction as the gate line; at least a portion of the second electrode extends in the same direction as the gate line.
[0037] The active pattern includes: a channel portion; the orthographic projection of the channel portion onto the substrate overlaps with the orthographic projection of the gap between the first electrode and the second electrode onto the substrate; the extension direction of the channel portion is the same as the extension direction of the gate line.
[0038] In one possible implementation, the array substrate includes: a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of pixel electrodes; the data lines are located on the side of the gate lines facing away from the substrate; the length of the pixel electrodes along the first direction is greater than the length along the second direction.
[0039] The signal line includes the data line; the first light-shielding strip is in the same layer and material as the grid line, and does not overlap with the grid line.
[0040] In one possible implementation, the array substrate further includes: a common electrode layer located on the side of the gate line facing the substrate, and a pixel electrode layer located on the side of the data line away from the substrate; the common electrode layer includes: a plurality of common electrodes; the pixel electrode layer includes: a plurality of pixel electrodes, the pixel electrodes including a plurality of gaps and a plurality of strip electrodes, and a plurality of transition electrodes;
[0041] The first light-shielding strip is in direct contact with the common electrode and electrically connected; the second light-shielding strip is electrically connected to the common electrode through the adapter electrode.
[0042] In one possible implementation, the array substrate further includes: multiple first common traces on the same layer as the gate lines; the first light-shielding strip is directly connected to the first common traces.
[0043] In one possible implementation, the first light-shielding strip is a floating electrode; and / or the second light-shielding strip is a floating electrode.
[0044] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and further includes a counter substrate disposed opposite to the array substrate;
[0045] The opposing substrate has a black matrix; the black matrix has a light-shielding portion, the orthographic projection of the light-shielding portion on the substrate overlaps with the orthographic projection of the signal line on the substrate; and at least a portion of the outer edge of the light-shielding portion is located within the orthographic projection of the first light-shielding strip on the substrate.
[0046] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description
[0047] Figure 1A This is one of the top views of the array substrate provided in the embodiments of this disclosure;
[0048] Figure 1B for Figure 1A Schematic diagram of the film layers of the common electrode layer and the gate line layer;
[0049] Figure 1C for Figure 1A A schematic diagram of the film layer containing the data cable;
[0050] Figure 1D for Figure 1A Schematic diagram of the film layer of the middle pixel electrode layer;
[0051] Figure 2 It can be Figure 1A A schematic diagram of the cross section at point e1 along the dashed line in the middle;
[0052] Figure 3A This is a second top view of the array substrate provided in the embodiments of this disclosure;
[0053] Figure 3B for Figure 3A Schematic diagram of the film layers of the common electrode layer and the gate line layer;
[0054] Figure 3C for Figure 3A A schematic diagram of the film layer containing the data cable;
[0055] Figure 3D for Figure 3A Schematic diagram of the film layer of the middle pixel electrode layer;
[0056] Figure 4 It can be Figure 3A A schematic diagram of the cross-section at point e2 along the dashed line in the middle;
[0057] Figure 5This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure;
[0058] Figure 6A This is the fourth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;
[0059] Figure 6B for Figure 6A Schematic diagram of the film layers of the common electrode layer and the gate line layer;
[0060] Figure 6C for Figure 6A A schematic diagram of the film layer containing the data cable;
[0061] Figure 6D for Figure 6A Schematic diagram of the film layer of the middle pixel electrode layer;
[0062] Figure 7 It can be Figure 6A A schematic diagram of the cross-section at point e3 along the dashed line. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0065] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.
[0066] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.
[0067] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0068] As energy consumption requirements increase, the transmittance requirements for LCD panels also become more stringent. A key approach to improving panel transmittance is to increase the pixel aperture ratio. LCD panel pixels experience light leakage near gate lines or data lines due to the influence of electric fields. Structurally, a relatively wide black matrix is designed on the color filter substrate to block this light leakage. Simultaneously, a large black matrix shielding margin must be reserved to overcome the effects of cell misalignment between the color filter substrate and the array substrate. In other words, existing display panels, due to the need to shield dark patterns generated by the electric fields around gate lines and / or data lines, require a relatively wide black matrix shielding on the color filter substrate, resulting in a lower pixel aperture ratio.
[0069] In view of this, see Figures 1A-1D , Figure 2 As shown, where, Figure 1B for Figure 1A Schematic diagram of the film layers of the common electrode layer and the gate line layer. Figure 1C for Figure 1A A schematic diagram of the film layer containing the data cable. Figure 1D for Figure 1A Schematic diagram of the film layer of the middle pixel electrode layer. Figure 2 It can be Figure 1A A cross-sectional view along the dashed line e1 shows that this disclosure provides an array substrate, which includes:
[0070] Substrate 1;
[0071] Signal line L is located on one side of substrate 1;
[0072] At least one first light-shielding strip G1 is located on one side of the substrate 1 and on a different layer from the signal line L. Its extension direction is the same as that of the signal line L. It is located on at least one side of the signal line L, and at least a portion of the orthographic projection of the first light-shielding strip G1 onto the substrate 1 does not overlap with the orthographic projection of the signal line L onto the substrate 1. Optionally, the first light-shielding strip G1 may be provided on both sides of the signal line.
[0073] In this embodiment, the array substrate includes at least one first light-shielding strip G1 located on a different layer from the signal line L, and extending in the same direction as the signal line L. At least a portion of the orthographic projection of the first light-shielding strip G1 onto the substrate 1 does not overlap with the orthographic projection of the signal line L onto the substrate 1. That is, by setting the first light-shielding strip G1 around the signal line L, light leakage near the signal line L can be blocked, reducing the light leakage range, reducing the black matrix width, increasing the aperture ratio, and improving the transmittance of the display panel. Moreover, compared to using a light-shielding strip on the same layer as the signal line L for light shielding, the manufacturing process requires a larger distance between the two to avoid short circuits between the signal line and the light-shielding strip on the same layer (e.g., the second light-shielding strip), resulting in limited reduction of the light leakage range. However, by using a first light-shielding strip G1 on a different layer from the signal line L, since the first light-shielding strip G1 is on a different layer from the signal line L, it can be designed to be very close to the signal line L or even overlap without short circuits, thereby significantly reducing the light leakage range.
[0074] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the array substrate further includes a second light-shielding strip G2 on the same layer as the signal line L and located on at least one side of the signal line L. The extension direction of the second light-shielding strip G2 is the same as the extension direction of the signal line L, and the two are spaced apart from each other. Since the first light-shielding strip G1 and the signal line L are on different layers, there is an overlay deviation fluctuation between the different layers during the manufacturing process. It is difficult to ensure the distance from the outer edge of the first light-shielding strip G1 to the signal line L (the distance must be determined to ensure the minimum black matrix blocking width to achieve complete blocking of light leakage). Therefore, in addition to using the first light-shielding strip G1, the second light-shielding strip G2 on the same layer as the signal line L is also used in this embodiment. Since the second light-shielding strip G2 is on the same layer as the signal line L, there is no overlay deviation problem, and the distance from the outer edge to the signal line L can be accurately defined. By having the outer edge of the second light-shielding strip G2 extend beyond the first light-shielding strip G1 and the distance exceeds the overlay deviation fluctuation range, the combination of the two light-shielding strips can maximize the blocking of light leakage and minimize the overall width of the light-shielding strip. With this design, the black matrix blocking edge on the opposing substrate can be reduced to the range of the light-shielding strip, thus improving the pixel aperture ratio.
[0075] Compared to using a single-layer light-shielding strip, such as a second light-shielding strip G2 on the same layer as the signal line L, the manufacturing process requires a relatively large distance between the two to prevent short circuits between the signal line and the light-shielding strip (e.g., the second light-shielding strip), resulting in limited reduction in light leakage. However, using a double-layer light-shielding strip—that is, in addition to using the second light-shielding strip G2 on the same layer as the signal line L, a first light-shielding strip G1 on a different layer—can be designed to be very close to or even overlap with the signal line L without short-circuiting, thus significantly reducing the light leakage range. However, since the first light-shielding strip G1 is on a different layer than the signal line L, it can be designed to be very close to the signal line L, even overlapping, to avoid short circuits, thereby significantly reducing the light leakage range. During the process, there are fluctuations in the overlay deviation between different layers, making it difficult to ensure the distance from the outer edge of the first light-shielding strip G1 to the signal line L (a certain distance is necessary to ensure the minimum black matrix blocking width to achieve complete blocking of light leakage). Therefore, a second light-shielding strip G2 is added on the same layer as the signal line L. Since it is on the same layer as the signal line L, there is no overlay deviation problem, and the distance from the outer edge to the signal line L can be accurately defined. By having the outer edge of the second light-shielding strip G2 extend beyond the first light-shielding strip G1 and the distance exceeds the overlay deviation fluctuation range, the combination of the two light-shielding strips can maximize the blocking of light leakage and minimize the overall width of the light-shielding strip.
[0076] In one possible implementation, see Figure 1A , Figure 2 As shown, the first light-shielding strip G1 has a first outer edge f1 on the side away from the signal line L; the second light-shielding strip G2 has a second outer edge f2 on the side away from the signal line L; among the first light-shielding strip G1 and the second light-shielding strip G2 on the same side of the signal line L, the orthographic projection of the second outer edge f2 onto the substrate 1 is located on the side of the orthographic projection of the first outer edge f1 onto the substrate 1 away from the signal line L. That is, the first light-shielding strip G1, which is on a different layer from the signal line L, can be brought closer to the signal line L to avoid short circuits, thereby significantly reducing the light leakage range. Meanwhile, the distance from the outer edge of the first light-shielding strip G1 to the signal line L can be accurately determined using the second light-shielding strip G2, which is on the same layer as the signal line L.
[0077] In one possible implementation, see Figure 1A , Figure 2 As shown, the first light-shielding strip G1 has a third outer edge f3 near the signal line L; the second light-shielding strip G2 has a fourth outer edge f4 near the signal line L; among the first light-shielding strip G1 and the second light-shielding strip G2 on the same side of the signal line L, the orthographic projection of the third outer edge f3 on the substrate 1 is located on the side of the orthographic projection of the fourth outer edge f4 on the substrate 1 near the signal line L.
[0078] In one possible implementation, see Figure 1A , Figure 2As shown, in the first light-shielding strip G1 and the second light-shielding strip G2 on the same side of the signal line L, the orthographic projection of the third outer edge f3 on the substrate 1 is located between the orthographic projection of the fourth outer edge f4 on the substrate 1 and the orthographic projection of the signal line L on the substrate 1.
[0079] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the array substrate includes: multiple gate lines 2 extending along a first direction X, and multiple data lines 3 extending along a second direction Y; the data lines 3 are located on the side of the gate lines 2 away from the substrate 1; the signal line L includes the gate lines 2; the first light-shielding strip G1 is in the same layer and material as the data lines 3, and does not overlap with the data lines 3.
[0080] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the array substrate further includes: a common electrode layer located on the side of the gate line 2 facing the substrate 1, and a pixel electrode layer located on the side of the data line 3 away from the substrate 1; the common electrode layer includes: a plurality of common electrodes 5; the pixel electrode layer includes: a plurality of pixel electrodes 4, and a plurality of transition electrodes 6; the pixel electrode 41 includes: a plurality of slits F; the second light-shielding strip G2 is directly contacted and electrically connected to the common electrode 5; the first light-shielding strip G1 is electrically connected to the common electrode 5 through the transition electrode 6. In this embodiment, the second light-shielding strip G2 is directly contacted and electrically connected to the common electrode 5; the first light-shielding strip G1 is electrically connected to the common electrode 5 through the transition electrode 6, which can ensure the potential stability of the first light-shielding strip G1 and the second light-shielding strip G2, and avoid voltage fluctuations caused by the coupling effect of the gate line and / or data line, thereby causing light leakage or crosstalk problems.
[0081] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the grid line 2 has a first light-shielding strip G1 on both sides of its vertical extension direction; the two first light-shielding strips G1 on both sides of the grid line 2 are electrically connected to the common electrode 5 through different vias. For example, combined with Figure 1A As shown in the leftmost column of sub-pixels, the first light-shielding strip G1 on the upper side of the gate line 2 is electrically connected to the common electrode 5 above the gate line 2 through the second via K2, and the first light-shielding strip G1 on the lower side of the gate line 2 is electrically connected to the common electrode 5 below the gate line 2 through the third via K3.
[0082] In one possible implementation, see Figure 1A As shown, the array substrate also includes: a transistor T; the transistor includes: a control electrode, a first electrode TB, and a second electrode TC; the pixel electrode 4 can be electrically connected to the second electrode TC of the transistor through a first via K1.
[0083] In one possible implementation, see Figure 1AAs shown, the array substrate also includes: a connecting strip G3 on the same layer as the data line; the connecting strip G3 connects to the first light-shielding strips G2 on both sides of the gate line 2. For example, combined with Figure 1A As shown in the leftmost column of sub-pixels, the connecting strip G3 connects the first light-shielding strips G1 on both sides of the gate line 2. In this embodiment, the two first light-shielding strips G1 on both sides of the gate line 2 are electrically connected to the common electrodes 5 on the upper and lower sides through different vias, and are connected by the connecting strip G3 that spans the gate line 2. With this design, the common electrodes of the entire display panel are connected horizontally and vertically to form a network, resulting in good uniformity of the common voltage.
[0084] In one possible implementation, see Figure 1A As shown in the leftmost column of sub-pixels, the extension line of connecting strip G3 is projected onto the substrate and passes through the center region of the pixel electrode 4 projected onto the substrate.
[0085] In one possible implementation, see Figure 1A As shown in the middle column of sub-pixels, the gate line 2 has a first light-shielding strip G1 on both sides of its vertical extension direction; of the two first light-shielding strips G1 on both sides of the gate line 2, only one of the first light-shielding strips G1 is electrically connected to the common electrode 5 through a via. For example, see Figure 1A As shown in the middle column of sub-pixels, of the two first light-shielding strips G1 on both sides of the gate line 2, only the first light-shielding strip G1 on the lower side of the gate line 2 is electrically connected to the common electrode 5 through the fourth via K4. In this embodiment, the first light-shielding strips G1 on both sides of the gate line 2 are connected by a connecting strip G3 that spans the gate line 2, but only one side of the first light-shielding strip G1 is connected to the common electrode 5 through the fourth via K4. This design results in a larger aperture ratio.
[0086] In one possible implementation, see Figure 1A As shown in the middle column of sub-pixels, the orthographic projection of the extension line of connecting strip G3 onto the substrate overlaps with the orthographic projection of the edge region of pixel electrode 4 onto the substrate.
[0087] In one possible implementation, see Figure 1A As shown in the rightmost column of sub-pixels, no connecting strip G3 is set. The first light-shielding strips G1 on both sides of the gate line 2 are connected to the common electrode 5 through vias. Under this design, the load on the gate line 2 is minimized.
[0088] In practical applications, the entire display panel can use only such as Figure 1A The setting of the first light-shielding strip G1 in the leftmost column; or the entire display panel can only use such a setting. Figure 1A The first light-shielding strip G1 in the middle column can be configured in such a way; alternatively, the entire display panel can use only such a method. Figure 1A The setting method for the first light-shielding strip G1 in the rightmost column; or, all three setting methods can be combined and used simultaneously on the same display panel, such as... Figure 1A As shown.
[0089] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the array substrate further includes: a first common trace 71 extending along the first direction X on the same layer as the gate line 2; a plurality of second light-shielding strips G2 on one side of the gate line 2 integrally connected and reused as the first common trace 71; and second light-shielding strips G2 on the other side of the gate line 2 spaced apart from each other. For example, a plurality of second light-shielding strips G2 on the lower side of the gate line 2 integrally connected and reused as the first common trace 71; and second light-shielding strips G2 on the upper side of the gate line 2 spaced apart from each other and not connected to each other. The second light-shielding strips G2 on the upper side of the gate line 2 can be disconnected at the position where they intersect with the data line 3.
[0090] In one possible implementation, see Figures 1A-1D , Figure 2 As shown, the array substrate also includes a first pattern 90 on the same layer as the active pattern 9. The first pattern 90 can overlap with the pattern on the layer where the data line 3 is located. For example, the orthographic projection of part of the first pattern 90 on the substrate can overlap with the orthographic projection of the first light-shielding strip G1 on the substrate.
[0091] In one possible implementation, see Figures 3A-3D , Figure 4 As shown, where, Figure 3B for Figure 3A Schematic diagram of the film layers of the common electrode layer and the gate line layer. Figure 3C for Figure 3A A schematic diagram of the film layer containing the data cable. Figure 3D for Figure 3A Schematic diagram of the film layer of the middle pixel electrode layer. Figure 4 It can be Figure 3A A cross-sectional view along the dashed line e2 shows that the array substrate further includes: a pixel electrode layer located on the side of the gate line 2 facing the substrate 1, and a common electrode layer located on the side of the data line 3 away from the substrate 1; the pixel electrode layer includes: a plurality of pixel electrodes 4; the common electrode layer includes: a plurality of common electrodes 5; the common electrodes 5 have a plurality of slits F; the array substrate further includes: a first trace 30 on the same layer as the data line 3 and extending along the second direction Y; the first light-shielding strips G1 are all connected to the first trace 30. In this embodiment, when the pixel electrode 4 is below and the common electrode 5 is above, the first light-shielding strip G1 and the second light-shielding strip G2 can also be provided around the gate line 2 to shield the area around the gate line 2, thereby reducing the width of the black matrix and improving the aperture ratio.
[0092] In one possible implementation, see Figures 3A-3D , Figure 4As shown, the common electrode layer further includes: a common connection portion 50 extending along the second direction Y; two adjacent common electrodes 5 in the second direction Y are connected through the common connection portion 50; the second light-shielding strip G2 is in direct contact with the pixel electrode 4 for electrical connection; the portion of the first trace 30 projected onto the substrate 1 overlaps with the projected portion of the common connection portion 50 onto the substrate 1, and a hole is drilled at the overlapping position for connection. For example, see... Figure 3A As shown, the first trace 30 and the common connection portion 50 are connected at their overlap position through a fifth via K5. In this embodiment, by making the second light-shielding strip G2 directly contact and electrically connect to the pixel electrode 4, and the first light-shielding strip G1 is connected to the first trace 30, and the first trace 30 and the common connection portion 50 are connected at their overlap position through a fifth via K5, the first light-shielding strip G1 is electrically connected to the common electrode 5, ensuring the potential stability of the first light-shielding strip G1 and the second light-shielding strip G2, and avoiding voltage fluctuations caused by the coupling effect of the gate line and / or data line, which could lead to light leakage or crosstalk problems.
[0093] In one possible implementation, see Figures 3A-3D , Figure 4 As shown, the array substrate includes: a plurality of gate line groups 20 extending along a first direction X and arranged along a second direction Y; the orthographic projection of the gate line group 20 onto the substrate 1 is located between the orthographic projections of two adjacent pixel electrode rows onto the substrate 1; the gate line group 20 includes two gate lines 2; the common connection portion 50 includes: a first sub-common portion 501, and a second sub-common portion 502 connected to both sides of the first sub-common portion 501; the width a1 of the first sub-common portion 501 in the first direction X is greater than the width a2 of the second sub-common portion 502 in the first direction X; the common connection portion 50 is connected to the first trace 30 through the first sub-common portion 501; the orthographic projection of the first sub-common portion 501 onto the substrate is located within the orthographic projection of the substrate 2, where the gap between the two gate lines 2 of the gate line group 20 is within the orthographic projection of the substrate 2.
[0094] In one possible implementation, see Figure 5 As shown, the orthographic projection of the gate line 2 onto the substrate and the orthographic projection of the data line 3 onto the substrate intersect at a point; the first light-shielding strip G1 has a bent portion G11 at the intersection point, and at least a portion of the orthographic projection of the bent portion G11 onto the substrate is located on the side of the orthographic projection of the gate line 2 onto the substrate away from the intersection point. When the first light-shielding strip G1 has a bent portion G11, a black matrix protrusion 85 can be provided at the position corresponding to the bent portion G11 to block the bent portion G11.
[0095] In one possible implementation, combined with Figures 1A-1D , Figure 2 , Figures 3A-3D , Figure 4As shown, the array substrate further includes: a transistor T; the transistor includes: a control electrode, a first electrode TB, a second electrode TC, and an active pattern 9; the control electrode uses a multiplexed gate line 2; at least a portion of the first electrode TB extends in the same direction as the gate line 2; at least a portion of the second electrode TC extends in the same direction as the gate line 2; the active pattern 9 includes: a channel portion 90; the orthographic projection of the channel portion 90 onto the substrate 1 overlaps with the orthographic projection of the gap between the first electrode TB and the second electrode TC onto the substrate; the extension direction of the channel portion 90 is the same as the extension direction of the gate line 2. In this embodiment, the extension direction of the channel portion 90 is the same as the extension direction of the gate line 2, at least a portion of the first electrode TB extends in the same direction as the gate line 2, and at least a portion of the second electrode TC extends in the same direction as the gate line 2, which can improve the aperture ratio and transmittance of the display panel.
[0096] In one possible implementation, combined with Figures 1A-1D , Figure 2 , Figures 3A-3D , Figure 4 As shown, the active pattern 9 can be an oxide semiconductor.
[0097] In one possible implementation, combined with Figures 6A-6D , Figure 7 As shown, where, Figure 6B for Figure 6A Schematic diagram of the film layers of the common electrode layer and the gate line layer. Figure 6C for Figure 6A A schematic diagram of the film layer containing the data cable. Figure 6D for Figure 6A Schematic diagram of the film layer of the middle pixel electrode layer. Figure 7 It can be Figure 6A A cross-sectional schematic diagram along the dashed line e3 shows that the array substrate includes: multiple gate lines 2 extending along a first direction X, multiple data lines 3 extending along a second direction Y, and multiple pixel electrodes 4; the data lines 3 are located on the side of the gate lines 2 facing away from the substrate 1; the length b1 of the pixel electrode 4 along the first direction X is greater than the length b2 along the second direction Y; the signal line L includes the data line 3; the first light-shielding strip G1 is in the same layer and material as the gate lines 2 and does not overlap with the gate lines 2. In this embodiment, the signal line L can also be the data line 3, that is, the first light-shielding strip G1 and the second light-shielding strip G2 can also be provided around the data line 3 to block the periphery of the data line 3.
[0098] In one possible implementation, combined with Figures 6A-6D , Figure 7As shown, the array substrate further includes: a common electrode layer located on the side of the gate line 2 facing the substrate 1, and a pixel electrode layer located on the side of the data line 3 away from the substrate 1; the common electrode layer includes: a plurality of common electrodes 5; the pixel electrode layer includes: a plurality of pixel electrodes 4, and a plurality of transition electrodes 6; the pixel electrode 4 includes a plurality of slits F; the first light-shielding strip G1 is directly contacted and electrically connected to the common electrode 5; the second light-shielding strip G2 is electrically connected to the common electrode 5 through the transition electrode 6. In this embodiment, for the first light-shielding strip G1 and the second light-shielding strip G2 disposed around the data line 3, the first light-shielding strip G1 can be directly contacted and electrically connected to the common electrode 5; the second light-shielding strip G2 is electrically connected to the common electrode 5 through the transition electrode 6, ensuring the potential stability of the first light-shielding strip G1 and the second light-shielding strip G2, avoiding voltage fluctuations caused by the coupling effect of the gate line and / or data line, which could lead to light leakage or crosstalk problems.
[0099] In one possible implementation, combined with Figures 6A-6D , Figure 7 As shown, the array substrate also includes: multiple first common traces 71 on the same layer as the gate line 2; the first light-shielding strip G1 is directly connected to the first common traces 71. Combined with... Figure 6A As shown, the first common trace 71 can extend along the first direction X, and the first light-shielding strip G1 can extend entirely along the second direction Y, but can be bent locally. For example, it can be bent at the point where the gate line intersects with the data line to avoid bending of the gate line at that location.
[0100] In one possible implementation, the first light-shielding strip G1 is a floating electrode; and / or the second light-shielding strip G2 is a floating electrode. That is, in specific implementations, if the coupling effect of the grid line or data line on the light-shielding strip is small, the first light-shielding strip G1 and the second light-shielding strip G2 can be electrically connected without a common electrode or pixel electrode, which can simplify the manufacturing of the display panel.
[0101] Based on the same inventive concept, this disclosure also provides a display panel, wherein, in conjunction with Figure 2 , Figure 4 , Figure 7 As shown, the display panel includes an array substrate 100 as provided in the embodiments of this disclosure, and a counter substrate 200 disposed opposite to the array substrate 100. The counter substrate 200 has a black matrix. The black matrix has a light-shielding portion 8, the orthographic projection of the light-shielding portion 8 on the substrate 1 overlaps with the orthographic projection of the signal line L on the substrate 1. At least a portion of the outer edge of the light-shielding portion 8 is located within the orthographic projection of the first light-shielding strip G1 on the substrate 1 in the orthographic projection. That is, the width of the light-shielding portion 8 can be reduced to within the first light-shielding strip G1, thereby reducing the width of the light-shielding portion 8 and increasing the aperture ratio of the display panel.
[0102] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel as provided in the embodiments of this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.
[0103] The pixel architecture in this disclosure is applicable to display pixel modes such as TN (Twisted Nematic), IPS (In-Plane Switching), ADS (Advanced Super Dimension Switch) / FFS (Fringe Field Switching), and VA (Vertical Alignment).
[0104] The pixel architecture in this disclosure is applicable to backplane processes such as a-Si (amorphous silicon), Oxide, LTPS (low-temperature polycrystalline silicon), and LTPO (low-temperature polycrystalline oxide).
[0105] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.
[0106] Based on the same inventive concept, this disclosure also provides a display device, comprising the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).
[0107] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, greater resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.
[0108] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0109] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0110] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate; The signal line is located on one side of the substrate; At least one first light-shielding strip is located on one side of the substrate and on a different layer from the signal line, extends in the same direction as the signal line, is located on at least one side of the signal line, and at least a portion of the orthographic projection of the first light-shielding strip on the substrate does not overlap with the orthographic projection of the signal line on the substrate.
2. The array substrate as claimed in claim 1, wherein, The array substrate further includes a second light-shielding strip on the same layer as the signal line and located on at least one side of the signal line, wherein the extension direction of the second light-shielding strip is the same as the extension direction of the signal line and the two are spaced apart from each other.
3. The array substrate as described in claim 2, wherein, The first light-shielding strip has a first outer edge on the side away from the signal line; the second light-shielding strip has a second outer edge on the side away from the signal line. In the first and second light-shielding strips on the same side of the signal line, the orthographic projection of the second outer edge on the substrate is located on the side of the first outer edge on the substrate that is away from the signal line.
4. The array substrate as claimed in claim 3, wherein, The first light-shielding strip has a third outer edge near the signal line; the second light-shielding strip has a fourth outer edge near the signal line. In the first and second light-shielding strips on the same side of the signal line, the orthographic projection of the third outer edge on the substrate is located on the side of the orthographic projection of the fourth outer edge on the substrate closer to the signal line.
5. The array substrate as claimed in claim 4, wherein, In the first and second light-shielding strips on the same side of the signal line, the orthographic projection of the third outer edge onto the substrate is located between the orthographic projection of the fourth outer edge onto the substrate and the orthographic projection of the signal line onto the substrate.
6. The array substrate according to any one of claims 2-5, wherein, The array substrate includes: a plurality of gate lines extending along a first direction, and a plurality of data lines extending along a second direction; the data lines are located on the side of the gate lines opposite to the substrate. The signal line includes the grid line; the first light-shielding strip is in the same layer and material as the data line, and does not overlap with the data line.
7. The array substrate as claimed in claim 6, wherein, The array substrate further includes: a common electrode layer located on the side of the gate line facing the substrate, and a pixel electrode layer located on the side of the data line away from the substrate; the common electrode layer includes: a plurality of common electrodes; the pixel electrode layer includes: a plurality of pixel electrodes, and a plurality of transition electrodes; wherein, the pixel electrode includes: a plurality of slits; The second light-shielding strip is in direct contact with the common electrode and electrically connected; the first light-shielding strip is electrically connected to the common electrode through the adapter electrode.
8. The array substrate as claimed in claim 7, wherein, The first light-shielding strip is provided on both sides of the grid line in the vertical extension direction; The two first light-shielding strips on both sides of the grid line are electrically connected to the common electrode through different vias.
9. The array substrate as claimed in claim 7, wherein, The array substrate further includes: a connecting strip on the same layer as the data line; the connecting strip connects the first light-shielding strips on both sides of the gate line.
10. The array substrate as claimed in claim 9, wherein, The extension line of the connecting strip is projected onto the substrate and passes through the central region of the pixel electrode's projection onto the substrate.
11. The array substrate as claimed in claim 7, wherein, The first light-shielding strip is provided on both sides of the grid line in the vertical extension direction; Of the two first light-shielding strips on both sides of the grid line, only one of the first light-shielding strips is electrically connected to the common electrode through a via.
12. The array substrate as claimed in claim 9, wherein, The extension line of the connecting strip is projected onto the substrate, and its projection overlaps with the edge region of the pixel electrode on the substrate.
13. The array substrate as claimed in claim 6, wherein, The array substrate further includes: a first common trace that is on the same layer as the gate line and extends along the first direction; The second light-shielding strips on one side of the grid line are integrally connected and reused as the first common trace; the second light-shielding strips on the other side of the grid line are spaced apart from each other.
14. The array substrate as claimed in claim 6, wherein, The array substrate further includes: a pixel electrode layer located on the side of the gate line facing the substrate, and a common electrode layer located on the side of the data line away from the substrate; the pixel electrode layer includes: a plurality of pixel electrodes; the common electrode layer includes: a plurality of common electrodes; the common electrodes have a plurality of slits; The array substrate further includes: a first trace on the same layer as the data line and extending along the second direction; the first light-shielding strips are all connected to the first trace.
15. The array substrate as claimed in claim 14, wherein, The common electrode layer further includes: a common connection portion extending along the second direction; two adjacent common electrodes in the second direction are connected through the common connection portion; The second light-shielding strip is in direct contact with the pixel electrode and electrically connected; the portion of the first trace projected onto the substrate overlaps with the portion of the common connection projected onto the substrate, and a hole is drilled at the overlapping position for connection.
16. The array substrate as claimed in claim 15, wherein, The array substrate includes: a plurality of gate line groups extending along the first direction and arranged along the second direction; the orthographic projection of the gate line group on the substrate is located between the orthographic projections of two adjacent pixel electrode rows on the substrate; the gate line group includes two gate lines. The common connection portion includes: a first sub-common portion, and a second sub-common portion connected to both sides of the first sub-common portion; the width of the first sub-common portion in the first direction is greater than the width of the second sub-common portion in the first direction; the common connection portion is connected to the first trace through the first sub-common portion; The first sub-common portion is projected onto the substrate, and the gap between the two gate lines of the gate line group is located within the projection of the substrate.
17. The array substrate as claimed in claim 6, wherein, The orthographic projection of the gate line onto the substrate and the orthographic projection of the data line onto the substrate intersect at a point; The first light-shielding strip has a bend at the intersection, and at least a portion of the bend in the orthographic projection onto the substrate is located on the side of the grating line in the orthographic projection onto the substrate away from the intersection.
18. The array substrate as claimed in claim 6, wherein, The array substrate further includes: transistors; the transistors include: a control electrode, a first electrode, a second electrode, and an active pattern; The control electrode reuses the gate line; at least a portion of the first electrode extends in the same direction as the gate line; at least a portion of the second electrode extends in the same direction as the gate line. The active pattern includes: a channel portion; the orthographic projection of the channel portion onto the substrate overlaps with the orthographic projection of the gap between the first electrode and the second electrode onto the substrate; the extension direction of the channel portion is the same as the extension direction of the gate line.
19. The array substrate according to any one of claims 2-5, wherein, The array substrate includes: multiple gate lines extending along a first direction, multiple data lines extending along a second direction, and multiple pixel electrodes; the data lines are located on the side of the gate lines facing away from the substrate; the length of the pixel electrodes along the first direction is greater than the length along the second direction. The signal line includes the data line; the first light-shielding strip is in the same layer and material as the grid line, and does not overlap with the grid line.
20. The array substrate as claimed in claim 19, wherein, The array substrate further includes: a common electrode layer located on the side of the gate line facing the substrate, and a pixel electrode layer located on the side of the data line away from the substrate; the common electrode layer includes: a plurality of common electrodes; the pixel electrode layer includes: a plurality of pixel electrodes, the pixel electrodes including a plurality of gaps and a plurality of strip electrodes, and a plurality of transition electrodes; The first light-shielding strip is in direct contact with the common electrode and electrically connected; the second light-shielding strip is electrically connected to the common electrode through the adapter electrode.
21. The array substrate as claimed in claim 20, wherein, The array substrate further includes: multiple first common traces on the same layer as the gate lines; the first light-shielding strip is directly connected to the first common traces.
22. The array substrate according to any one of claims 2-5, wherein, The first light-shielding strip is a floating electrode; and / or the second light-shielding strip is a floating electrode.
23. A display panel, wherein, The array substrate as described in any one of claims 1-22 is further comprising a counter substrate disposed opposite to the array substrate; The opposing substrate has a black matrix; the black matrix has a light-shielding portion, the orthographic projection of the light-shielding portion on the substrate overlaps with the orthographic projection of the signal line on the substrate; and at least a portion of the outer edge of the light-shielding portion is located within the orthographic projection of the first light-shielding strip on the substrate.
24. A display device, wherein, Includes the display panel as described in claim 23.