Semiconductor passive device electric connection structure

Abstract

The utility model is suitable for the technical field of semiconductors, and provides an electric connection structure of a semiconductor passive device. Comprising a substrate layer, capacitor parts which are symmetrically arranged on the substrate layer and are used for forming capacitor devices, dielectric layers which are symmetrically arranged on the substrate layer and are used for forming insulating layers, inductance coil parts which are symmetrically arranged on the substrate layer and are used for forming inductance devices, and bridging structures which are arranged in the two capacitor parts and the two inductance coil parts and are used for connection. The device solves the problems that the connection process is complicated and the high-frequency transmission loss is relatively large when a bridge connection structure is adopted by an electric connection structure of a passive device, and achieves the effects that the bridge connection structure is further simplified on the basis of simplifying the electric connection structure of the passive device, and one substrate is adopted for preparation; the production cost is reduced; and meanwhile, the loss under high-frequency transmission signals is reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and more specifically, to an electrical connection structure for a semiconductor passive device. Background Technology

[0002] With the continuous development of semiconductor technology, integrated circuits and large-scale integrated circuits are widely used. The components that make up an integrated circuit can be passive or active. When the components are passive, they are called integrated passive devices (IPD). IPD provides the integration of passive devices such as high-precision capacitors and high-performance inductors.

[0003] The passive components in integrated passive devices mainly consist of various types such as passive resistors, passive capacitors, and passive inductors. To address the problem that the conductive connection structure in integrated passive devices is relatively complex, leading to complicated processes, existing technologies have simplified the structure of the conductive connection part of integrated passive devices, thereby reducing manufacturing costs and manufacturing time.

[0004] Meanwhile, achieving localized high-density interconnects between chips through bridging structures has become a mainstream advanced packaging solution in the semiconductor field. The fabrication of bridging structures for passive devices generally requires two substrates. On the one hand, this involves complex processes such as substrate bonding, resulting in high costs. On the other hand, the wiring from the chip end to the substrate end is complex. In high-frequency applications, when signals are transmitted to passive devices, the wires need to be connected to the lines at both ends of the passive device, leading to a reduction in the cross-sectional area of ​​the wires, an increase in resistance, and ultimately, excessive signal loss during transmission. Utility Model Content

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a semiconductor passive device electrical connection structure that simplifies the bridging structure, is fabricated using a single substrate, reduces production costs, and minimizes losses during high-frequency signal transmission.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A semiconductor passive device electrical connection structure includes a substrate layer, capacitor portions symmetrically disposed on the substrate layer for forming capacitors, dielectric layers symmetrically disposed on the substrate layer for forming insulating layers, inductor coil portions symmetrically disposed on the substrate layer for forming inductors, and a bridge structure disposed inside the two capacitor portions and the two inductor coil portions for connection.

[0008] The present invention is further configured such that: the capacitor portion includes a conductive layer disposed on a substrate layer, a capacitor dielectric layer disposed on the conductive layer, a lower electrode outlet portion, and an upper electrode outlet portion disposed on the capacitor dielectric layer.

[0009] The present invention is further configured such that the upper electrode outlet and the lower electrode outlet are separated from each other, and at least one of the upper electrode outlet and the lower electrode outlet is electrically connected to the lower electrode outlet.

[0010] The present invention is further configured such that a bridging structure is provided between the two conductive layers for connection.

[0011] The present invention is further configured such that: the dielectric layer partially covers the capacitor portion and the inductor coil portion, and the thickness of the dielectric layer is greater than the thickness of the capacitor portion and the inductor coil portion.

[0012] The present invention is further configured such that: the bridging structure includes a first metal interconnect layer formed on the surface of the substrate, a second metal interconnect layer formed on the other surface of the substrate, and a metal interconnect hole formed inside the substrate, wherein the two ends of the metal interconnect hole are respectively connected to the first metal interconnect layer and the second metal interconnect layer.

[0013] By employing the above technical solution, two conductive layers are connected via a bridging structure, achieving interconnection between the two capacitor sections, thereby forming a 3D capacitor structure on both sides of the substrate. Similarly, two inductor coil sections are connected via a bridging structure, achieving interconnection between the two inductor coil sections, thereby forming a 3D inductor structure on both sides of the substrate.

[0014] The present invention is further configured such that: the first metal connection layer can be formed by depositing metal on the surface of the substrate layer and above the metal interconnect hole by means of photolithography, electroplating, etc., so that a portion of the first metal connection layer can be electrically connected to the metal interconnect hole.

[0015] The present invention is further configured such that: the second metal interconnect layer is formed by depositing metal on the other surface of the substrate layer and in the exposed portion of the metal interconnect hole by means of photolithography, electroplating, etc.

[0016] The beneficial effects of this utility model are:

[0017] By integrating 3D passive devices formed by 3D capacitor and 3D inductor structures onto a substrate using a bridging structure, the connection can be completed using only one substrate. This makes the electrical connection structure of the passive device thinner and more integrated. At the same time, the electrical signals of the wires can be directly transmitted to both sides of the passive device using the 3D capacitor and 3D inductor structures, avoiding the problem of excessive electrical signal loss under high-frequency signal transmission. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1This is a schematic diagram of the electrical connection structure of the semiconductor passive device of this utility model.

[0020] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the electrical connection structure of a semiconductor passive device.

[0021] Figure labeling: 1. Substrate layer;

[0022] 2. Capacitor section; 21. Conductive layer; 22. Capacitor dielectric layer; 23. Upper electrode lead-out section; 24. Lower electrode lead-out section;

[0023] 3. Dielectric layer;

[0024] 4. Inductor coil section;

[0025] 5. Bridge structure; 51. First metal connection layer; 52. Metal interconnect hole; 53. Second metal interconnect layer. Detailed Implementation

[0026] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will now be described in detail with reference to the accompanying drawings. This drawing is a simplified schematic diagram, illustrating only the basic aspects of the present utility model, and therefore only shows the components relevant to the present utility model. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0027] Please refer to Figure 1-2 A semiconductor passive device electrical connection structure includes a substrate layer 1, capacitor portions 2 symmetrically disposed on the substrate layer 1 for forming capacitors, dielectric layers 3 symmetrically disposed on the substrate layer 1 for forming insulating layers, inductor coil portions 4 symmetrically disposed on the substrate layer 1 for forming inductors, and a bridge structure 5 disposed inside the two capacitor portions 2 and the two inductor coil portions 4 for connection.

[0028] Please refer to Figure 1-2The capacitor section 2 includes a conductive layer 21 disposed on a substrate layer 1, a capacitor dielectric layer 22 disposed on the conductive layer 21, a lower electrode outlet section 24 disposed on the conductive layer 21, and an upper electrode outlet section 23 disposed on the capacitor dielectric layer 22. The upper electrode outlet section 23 and the lower electrode outlet section 24 are separated from each other, and at least one of the upper electrode outlet section 23 and the lower electrode outlet section 24 is electrically connected to the lower electrode outlet section 24. The independently disposed upper electrode outlet section 23 and the lower electrode outlet section 24 are formed by sequentially depositing the conductive layer 21 and the capacitor dielectric layer 22 on the substrate layer 1, and then performing patterning processes such as deposition, etching, or stripping. In addition, a conductive layer can be further disposed on the upper electrode outlet section 23 to electrically connect the upper electrode outlet section 23 to the inductor coil section 4 to meet the power connection requirements of the capacitor and the inductor. With the above structure, the thickness of the conductive layer 21 can be designed and manufactured to be relatively thin while the thickness of the inductor coil section 4 can be designed and manufactured to be relatively thick, ensuring the normal use of the integrated passive device. This not only meets the high-performance requirements of the inductor coil section 4, but also avoids defects such as microcracks that are prone to occur due to the use of silicon dioxide layer, which could lead to device failure. It can effectively improve the device quality factor of the inductor in the integrated passive device and improve the reliability of the device.

[0029] Please refer to Figure 1-2 The dielectric layer 3 partially covers the capacitor section 2 and the inductor coil section 4, and the thickness of the dielectric layer 3 is greater than the thickness of the capacitor section 2 and the inductor coil section 4. The dielectric layer 3 can be made of any material or combination of spin-coated glass (SGS), polyimide, and epoxy resin, so as to adjust its thickness and achieve coverage of the capacitor section 2 and the inductor coil section 4.

[0030] Please refer to Figure 1-2 A bridging structure 5 is provided between the two conductive layers 21 for connection, and a bridging structure 5 is provided between the two inductor coil portions 4 for connection. The bridging structure 5 includes a first metal interconnect layer 51 formed on the surface of the substrate layer 1, a second metal interconnect layer 53 formed on the other surface of the substrate layer 1, and a metal interconnect hole 52 formed inside the substrate layer 1. The two ends of the metal interconnect hole 52 are respectively connected to the first metal interconnect layer 51 and the second metal interconnect layer 53. Blind holes of different sizes are prepared on the surface of the substrate layer 1 using processes such as etching or laser, and the blind holes are metallized to form the metal interconnect hole 52 by combining metal electroplating or deposition. The first metal interconnect layer 51 can be formed by depositing metal on the surface of the substrate layer 1 and above the metal interconnect hole 52 by photolithography, electroplating, etc., so that a portion of the first metal interconnect layer 51 can be electrically connected to the metal interconnect hole 52. The second metal interconnect layer 53 can be formed by depositing metal on the other surface of the substrate layer 1 and in the exposed portion of the metal interconnect hole 52 by photolithography, electroplating, etc.

[0031] Please refer to Figure 1-2Two conductive layers 21 are connected by a bridging structure 5, interconnecting the two capacitor sections 2 and forming a 3D capacitor structure on both sides of the substrate layer 1. Two inductor coil sections 4 are also connected by the bridging structure 5, interconnecting the two inductor coil sections 4 and forming a 3D inductor structure on both sides of the substrate layer 1. By integrating the 3D capacitor and 3D inductor structures into a 3D passive device on the substrate layer 1 using the bridging structure 5, the connection can be completed using only one substrate layer 1. This results in a thinner and more highly integrated passive device electrical connection structure. Furthermore, the 3D capacitor and 3D inductor structures can directly transmit electrical signals from the wires to both sides of the passive device, avoiding excessive signal loss during high-frequency signal transmission.

[0032] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0033] It should be understood that the terms "length", "width", "up", "down", "front and back", "left and right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0034] Based on the preferred embodiments of this utility model described above, those skilled in the art can make various changes and modifications without departing from the scope of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An electrical connection structure for a semiconductor passive device, characterized in that: It includes a substrate layer (1), a capacitor portion (2) symmetrically disposed on the substrate layer (1) for forming a capacitor, a dielectric layer (3) symmetrically disposed on the substrate layer (1) for forming an insulating layer, an inductor coil portion (4) symmetrically disposed on the substrate layer (1) for forming an inductor, and a bridge structure (5) disposed inside the two capacitor portions (2) and the two inductor coil portions (4) for connection.

2. The semiconductor passive device electrical connection structure according to claim 1, characterized in that: The capacitor section (2) includes a conductive layer (21) disposed on a substrate layer (1), a capacitor dielectric layer (22) disposed on the conductive layer (21), a lower electrode outlet section (24), and an upper electrode outlet section (23) disposed on the capacitor dielectric layer (22).

3. The semiconductor passive device electrical connection structure according to claim 2, characterized in that: A bridging structure (5) is provided between the two conductive layers (21) for connection.

4. The semiconductor passive device electrical connection structure according to claim 1, characterized in that: The dielectric layer (3) partially covers the capacitor portion (2) and the inductor coil portion (4), and the thickness of the dielectric layer (3) is greater than the thickness of the capacitor portion (2) and the inductor coil portion (4).

5. The semiconductor passive device electrical connection structure according to claim 1, characterized in that: The bridging structure (5) includes a first metal interconnect layer (51) formed on the surface of the substrate layer (1), a second metal interconnect layer (53) formed on the other surface of the substrate layer (1), and a metal interconnect hole (52) formed inside the substrate layer (1). The two ends of the metal interconnect hole (52) are connected to the first metal interconnect layer (51) and the second metal interconnect layer (53) respectively.

6. The semiconductor passive device electrical connection structure according to claim 5, characterized in that: The first metal interconnect layer (51) can be formed by depositing metal on the surface of the substrate layer (1) and above the metal interconnect hole (52) through photolithography and electroplating, so that a portion of the first metal interconnect layer (51) can be electrically connected to the metal interconnect hole (52).

7. The semiconductor passive device electrical connection structure according to claim 6, characterized in that: The second metal interconnect layer (53) can be formed by photolithography and electroplating on the other surface of the substrate layer (1) and in the exposed portion of the metal interconnect hole (52).

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