Electronic tester

Abstract

The utility model relates to the technical field of testing, in particular to an electronic tester, which comprises a signal input end, a signal processing circuit, a main control module and a signal output end, and is characterized in that the signal input end is used for receiving a signal to be tested; one end of the signal processing circuit is connected with the signal input end, and a conditioning signal is generated after a signal to be tested is conditioned; one end of the main control module is connected with the other end of the signal processing circuit, outputs a waveform signal meeting a first waveform condition according to the conditioning signal, and / or displays the conditioning signal, and / or generates a logic analysis result according to the conditioning signal; and one end of the signal output end is connected with the other end of the main control module and is used for outputting a waveform signal, and / or a conditioning signal, and / or a logic analysis result. Therefore, the problem that an electronic testing instrument has significant limitations in the aspects of function integration level, portability and high-frequency signal processing capacity is solved, the functions of a signal generator, an oscilloscope, a logic analyzer and the like are integrated, and the device has the characteristics of high precision, wide band and portability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to an electronic tester. BACKGROUND

[0002] Traditional electronic test instruments have significant limitations in functional integration, portability and high-frequency signal processing capability.

[0003] In the field of signal generators, related technologies generally use discrete analog circuits to generate waveforms, and the output frequency is usually limited to below 1MHz, and the waveform parameter (such as square wave duty cycle, triangular wave symmetry) adjustment precision is insufficient, resulting in a high harmonic distortion rate generally exceeding 10%, which is difficult to meet the demand of modern electronic systems for high-purity signal sources.

[0004] In the field of oscilloscopes, commercial products generally use high-speed ADC chips (such as 1GSPS sampling rate) to achieve a bandwidth of more than 100MHz, resulting in a sharp increase in hardware costs, and the real-time sampling architecture has a contradiction between storage depth and sampling rate when capturing high-frequency periodic signals, for example, when collecting signals above 50MHz, the lack of equivalent time sampling function will result in a waveform reconstruction error exceeding 5%. Logic analyzers are usually designed independently of oscilloscopes, with the number of channels limited to 4-8, the storage depth insufficient for 1k points, and lacking protocol decoding and multi-level trigger functions, making it difficult to meet the debugging needs of complex digital systems.

[0005] In addition, electronic testers in related technologies are mostly designed with modular functions, with signal generators, oscilloscopes and logic analyzers independent of each other, resulting in large equipment size (typical size exceeding 300mm x 200mm x 100mm), high power consumption (>20W), and lack of collaborative working mechanism between modules, making it impossible to achieve closed-loop verification of signal generation and acquisition.

[0006] In actual applications, for example, in the context of university experimental teaching, students need to frequently switch equipment to complete basic circuit testing, which is tedious and prone to wiring errors; in the context of electronic design competitions, participating teams face transportation and power supply problems when carrying multiple instruments. More importantly, high-frequency signal testing equipment (such as >=50MHz oscilloscopes) is expensive due to reliance on imported high-speed ADC chips, which severely restricts the popularization and application of small and medium-sized laboratories and engineering sites. CONTENT OF THE UTILITY MODEL

[0007] The present application provides an electronic tester to solve the problem of significant limitations in functional integration, portability and high-frequency signal processing capability of electronic test instruments, integrating signal generator, oscilloscope and logic analyzer functions in a single device, with high precision, wide frequency band and portability, strong practicality and wide applicability.

[0008] The first aspect of the present application provides an electronic tester, comprising:

[0009] a signal input end for receiving a signal to be tested;

[0010] a signal processing circuit, one end of the signal processing circuit being connected with the signal input end, the signal processing circuit generating a conditioned signal after conditioning the signal to be tested;

[0011] a master control module, one end of the master control module being connected with the other end of the signal processing circuit, the master control module outputting a waveform signal satisfying a first waveform condition according to the conditioned signal, and / or displaying the conditioned signal, and / or generating a logic analysis result according to the conditioned signal;

[0012] a signal output end, one end of the signal output end being connected with the other end of the master control module, for outputting the waveform signal, and / or the conditioned signal, and / or the logic analysis result.

[0013] Optionally, the signal processing circuit comprises a conditioning circuit, a selector and an emitter follower, wherein,

[0014] the conditioning circuit is electrically connected with the selector;

[0015] the conditioning circuit is electrically connected with the emitter follower.

[0016] Optionally, the conditioning circuit comprises a first attenuator, an amplifier, a comparator and a second attenuator, wherein,

[0017] an input end of the first attenuator is connected with the signal input end, and an output end of the first attenuator is connected with an input end of the selector;

[0018] an input end of the amplifier is connected with a first output end of the selector, and an output end of the amplifier is connected with a first input end of the comparator;

[0019] a second input end of the comparator is connected with the selector, and a first output end of the comparator is connected with the second attenuator;

[0020] an output end of the second attenuator is connected with the master control module.

[0021] Optionally, the electronic tester described above comprises:

[0022] an input end of the emitter follower is connected with a second output end of the comparator, and an output end of the emitter follower is connected with the master control module.

[0023] Optionally, the master control module comprises:

[0024] An analog-to-digital conversion unit, an input end of the analog-to-digital conversion unit being connected with an output end of the emitter follower;

[0025] A programmable logic unit, a first input end of the programmable logic unit being connected with an output end of the second attenuator, a second input end of the programmable logic unit being connected with an output end of the analog-to-digital conversion unit;

[0026] A digital-to-analog conversion unit, an input end of the digital-to-analog conversion unit being connected with an output end of the programmable logic unit, an output end of the digital-to-analog conversion unit being connected with the signal output end.

[0027] Optionally, the main control module further comprises:

[0028] An interactive display unit, the interactive display unit being electrically connected with the programmable logic unit.

[0029] Optionally, the first attenuator and the second attenuator each comprise:

[0030] A first radio frequency interface, one end of the first radio frequency interface being connected with a ground wire;

[0031] A first resistor, a first end of the first resistor being connected with another end of the first radio frequency interface, a second end of the first resistor being connected with the ground wire;

[0032] A second resistor, one end of the second resistor being connected with a third end of the first resistor;

[0033] A third resistor, a first end of the third resistor being connected with another end of the second resistor, a second end of the third resistor being connected with the ground wire;

[0034] A second radio frequency interface, one end of the second radio frequency interface being connected with a third end of the third resistor, another end of the second radio frequency interface being connected with the ground wire.

[0035] Optionally, the amplifier comprises:

[0036] A third radio frequency interface, one end of the third radio frequency interface being connected with a ground wire;

[0037] A fourth resistor, one end of the fourth resistor being connected with another end of the third radio frequency interface;

[0038] A fifth resistor, one end of the fifth resistor being connected with the ground wire;

[0039] a first operational amplifier, one end of the first operational amplifier is connected with the other end of the fourth resistor, the second port of the first operational amplifier is connected with the other end of the fifth resistor, the third port of the first operational amplifier is connected with the negative electrode of the first power supply, and the fourth port of the first operational amplifier is connected with the positive electrode of the first power supply;

[0040] a sixth resistor, one end of the sixth resistor is connected with the other end of the fourth resistor;

[0041] a seventh resistor, one end of the seventh resistor is connected with the other end of the sixth resistor and the fifth port of the first operational amplifier respectively;

[0042] a fourth radio frequency interface, one end of the fourth radio frequency interface is connected with the other end of the seventh resistor, and the other end of the fourth radio frequency interface is connected with the ground wire.

[0043] Optionally, the comparator comprises:

[0044] a first connector, one end of the first connector is connected with the ground wire;

[0045] a first capacitor, one end of the first capacitor is connected with the other end of the first connector;

[0046] an eighth resistor, one end of the eighth resistor is connected with the second power supply;

[0047] a ninth resistor, one end of the ninth resistor is connected with the other end of the first capacitor and the other end of the eighth resistor respectively, and the other end of the ninth resistor is connected with the ground wire;

[0048] a comparator body, the first port of the comparator body is connected with one end of the ninth resistor, the second port and the third port of the comparator body are connected with the ground wire, and the fourth port of the comparator body is connected with the third power supply;

[0049] a tenth resistor, one end of the tenth resistor is connected with the fifth port of the comparator body, and the other end of the tenth resistor is connected with the fourth power supply;

[0050] an eleventh resistor, one end of the eleventh resistor is connected with one end of the tenth resistor;

[0051] a twelfth resistor, one end of the twelfth resistor is connected with the sixth port of the comparator body and the other end of the eleventh resistor respectively;

[0052] a second capacitor, one end of the second capacitor is connected with the third power supply, and the other end of the second capacitor is connected with the ground wire;

[0053] a third capacitor, one end of the third capacitor being connected with the third power supply, the other end of the third capacitor being connected with the ground wire;

[0054] a second connector, one end of the second connector being connected with the other end of the twelfth resistor, the other end of the second connector being connected with the ground wire.

[0055] Optionally, the emitter follower comprises:

[0056] a fifth radio frequency interface, one end of the fifth radio frequency interface being connected with the ground wire;

[0057] a thirteenth resistor, one end of the thirteenth resistor being connected with the other end of the fifth radio frequency interface;

[0058] a second operational amplifier, a first port of the second operational amplifier being connected with a second port of the second operational amplifier, a third port of the second operational amplifier being connected with the other end of the thirteenth resistor, a fourth port of the second operational amplifier being connected with a negative electrode of a fifth power supply, a fifth port of the second operational amplifier being connected with a positive electrode of the fifth power supply;

[0059] a fourteenth resistor, one end of the fourteenth resistor being connected with the first port of the second operational amplifier and the second port of the second operational amplifier respectively;

[0060] a sixth radio frequency interface, one end of the sixth radio frequency interface being connected with the other end of the fourteenth resistor, the other end of the sixth radio frequency interface being connected with the ground wire.

[0061] Therefore, the application comprises a signal input end, a signal processing circuit, a master control module and a signal output end, wherein the signal input end is used for receiving a to-be-tested signal; one end of the signal processing circuit is connected with the signal input end, and a to-be-tested signal is conditioned to generate a conditioned signal; one end of the master control module is connected with the other end of the signal processing circuit, a waveform signal meeting a first waveform condition is output according to the conditioned signal, and / or the conditioned signal is displayed, and / or a logic analysis result is generated according to the conditioned signal; one end of the signal output end is connected with the other end of the master control module, and the waveform signal, and / or the conditioned signal, and / or the logic analysis result is output. Therefore, the problem of significant limitations of electronic test instruments in functional integration, portability and high-frequency signal processing capability is solved, and the functions of a signal generator, an oscilloscope and a logic analyzer are integrated, and high precision, wide frequency band and portability are achieved.

[0062] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0063] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of embodiments, taken in conjunction with the references to the following drawings, wherein:

[0064] Figure 1 a schematic diagram of an electronic tester according to an embodiment of the present application;

[0065] Figure 2 a schematic diagram of a first attenuator according to an embodiment of the present application;

[0066] Figure 3 a schematic diagram of a second attenuator according to an embodiment of the present application;

[0067] Figure 4 a schematic diagram of an amplifier according to an embodiment of the present application;

[0068] Figure 5 a schematic diagram of a comparator according to an embodiment of the present application;

[0069] Figure 6 a schematic diagram of a follower according to an embodiment of the present application;

[0070] Figure 7 a schematic diagram of an analog-to-digital converter according to an embodiment of the present application;

[0071] Figure 8 a schematic diagram of a digital-to-analog converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0072] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals and letters refer to the same or like components or elements throughout the views and manufacturing stages. The embodiments described below are illustrative of the present application and are not intended to be limiting of the present application.

[0073] An electronic tester according to embodiments of the present application is described below with reference to the accompanying drawings. In view of the significant limitations of electronic test instruments in terms of functional integration, portability and high-frequency signal processing capability mentioned in the background, the present application provides an electronic tester, comprising a signal input end, a signal processing circuit, a main control module and a signal output end, wherein the signal input end is configured to receive a signal to be tested; one end of the signal processing circuit is connected to the signal input end, and the signal processing circuit is configured to generate a conditioned signal after conditioning the signal to be tested; one end of the main control module is connected to the other end of the signal processing circuit, and the main control module is configured to output a waveform signal satisfying a first waveform condition according to the conditioned signal, and / or display the conditioned signal, and / or generate a logic analysis result according to the conditioned signal; one end of the signal output end is connected to the other end of the main control module, and the signal output end is configured to output the waveform signal, and / or the conditioned signal, and / or the logic analysis result. Thus, the problem of significant limitations of electronic test instruments in terms of functional integration, portability and high-frequency signal processing capability is solved, and the electronic tester integrates functions such as signal generator, oscilloscope and logic analyzer, and has high precision, wide frequency band and portability.

[0074] Specifically, Figure 1 FIG. 1 shows a schematic diagram of an electronic tester according to an embodiment of the present application.

[0075] As Figure 1 shown, the electronic tester 10 comprises a signal input end 100, a signal processing circuit 200, a main control module 300 and a signal output end 400.

[0076] The signal input end 100 is configured to receive a signal to be tested; one end of the signal processing circuit 200 is connected to the signal input end 100, and the signal processing circuit 200 is configured to generate a conditioned signal after conditioning the signal to be tested; one end of the main control module 300 is connected to the other end of the signal processing circuit 200, and the main control module 300 is configured to output a waveform signal satisfying a first waveform condition according to the conditioned signal, and / or display the conditioned signal, and / or generate a logic analysis result according to the conditioned signal; one end of the signal output end 400 is connected to the other end of the main control unit, and the signal output end 400 is configured to output the waveform signal, and / or the conditioned signal, and / or the logic analysis result.

[0077] Specifically, after the signal receiving end receives the signal to be tested, the signal to be tested is transmitted to the signal processing circuit. The signal processing circuit is configured to generate a conditioned signal after conditioning the signal to be tested. The main control module integrates functions of signal generator, oscilloscope and logic analyzer, and outputs a waveform signal satisfying a first waveform condition according to the test requirement, wherein the first waveform condition is pre-set by relevant personnel. Alternatively, the signal to be tested is sampled, reconstructed and displayed. Alternatively, a logic analysis result is generated according to the test requirement.

[0078] Optionally, in some embodiments, the signal processing circuit 200 comprises a conditioning circuit, a selector and an emitter follower.

[0079] Specifically, the conditioning circuit is electrically connected with the selector; the conditioning circuit is electrically connected with the emitter follower, the selector is used for respectively processing the small voltage and the large voltage, and the emitter follower is used for ensuring that the voltage is not attenuated.

[0080] Further, in some embodiments, the conditioning circuit comprises a first attenuator, an amplifier, a comparator and a second attenuator.

[0081] Specifically, in combination with Figure 1 As shown, the input end of the first attenuator is connected with the signal input end 100, the output end of the first attenuator is connected with the input end of the selector; the input end of the amplifier is connected with the first output end of the selector, the output end of the amplifier is connected with the first input end of the comparator; the second input end of the comparator is connected with the selector, the first output end of the comparator is connected with the second attenuator; the output end of the second attenuator is connected with the master control module 300.

[0082] Specifically, the conditioning circuit of the embodiment of the application realizes wide dynamic range signal adaptation by adopting a three-stage cascade architecture.

[0083] The first stage is a π-type attenuator network, which is composed of two 75Ω±1% precision metal film resistors (model CRCW080575R0FKEA) and one 243Ω±0.5% precision thin film resistor (model ERA-2AEB2430X) to form a T-shaped symmetrical structure, which realizes a 20dB±0.2dB attenuation ratio in a DC-150MHz frequency band, matches an input impedance of 51Ω characteristic impedance (VSWR≤1.5), and can withstand a maximum continuous input power of 1W.

[0084] The second stage is an amplifier, which adopts an OPA690IDR operational amplifier to build a phase inversion / phase symmetry switchable topology, maintains a-3dB bandwidth of ≥180MHz at a 40dB gain, has an input equivalent noise density of 2.7nV / √Hz, and has a voltage swing rate of 1800V / μs.

[0085] The third stage is a high-speed comparator module, which adopts a TLV3501AIDBVR chip (propagation delay 4.3ns@5mV overdrive) and a REF5025IDGKR reference source (temperature drift 3ppm / ℃) to form a hysteresis comparison circuit, sets a 10mV adjustable differential voltage through an R1=10kΩ and R2=15kΩ resistor network, converts the conditioned signal into a 3.3V±2% square wave output after passing through the π-type attenuator network, has a rise / fall time of ≤1.5ns (test conditions: CL=15pF), has an output driving capability of ±25mA, supports a LVCMOS33 level GPIO port of the FPGA, has a whole signal path delay of ≤8ns, and ensures high-frequency signal phase consistency.

[0086] Further, in some embodiments, the circuit structure of the first attenuator and the second attenuator, as shown in Figure 2 and Figure 3 , both include a first radio frequency interface, a first resistor, a second resistor, a third resistor, and a second radio frequency interface.

[0087] Specifically, one end of the first radio frequency interface is connected with a ground wire; a first end of the first resistor is connected with the other end of the first radio frequency interface, and a second end of the first resistor is connected with the ground wire; one end of the second resistor is connected with a third end of the first resistor; a first end of the third resistor is connected with the other end of the second resistor, and a second end of the third resistor is connected with the ground wire; one end of the second radio frequency interface is connected with a third end of the third resistor, and the other end of the second radio frequency interface is connected with the ground wire.

[0088] Optionally, in some embodiments, the circuit structure of the amplifier, as shown in Figure 4 , includes a third radio frequency interface, a fourth resistor, a fifth resistor, a first operational amplifier, a sixth resistor, a seventh resistor, and a fourth radio frequency interface.

[0089] Specifically, one end of the third radio frequency interface is connected with a ground wire; one end of the fourth resistor is connected with the other end of the third radio frequency interface; one end of the fifth resistor is connected with the ground wire; a first port of the first operational amplifier is connected with the other end of the fourth resistor, a second port of the first operational amplifier is connected with the other end of the fifth resistor, a third port of the first operational amplifier is connected with a negative electrode of a first power supply, a fourth port of the first operational amplifier is connected with a positive electrode of the first power supply; one end of the sixth resistor is connected with the other end of the fourth resistor; one end of the seventh resistor is connected with the other end of the sixth resistor and a fifth port of the first operational amplifier respectively; one end of the fourth radio frequency interface is connected with the other end of the seventh resistor, and the other end of the fourth radio frequency interface is connected with the ground wire. In actual execution, as shown in Figure 4 , the first port of the first operational amplifier is pin 2, the second port of the first operational amplifier is pin 3, the third port of the first operational amplifier is pin 4, the fourth port of the first operational amplifier is pin 7, and the fifth port of the first operational amplifier is pin 6.

[0090] Optionally, in some embodiments, the circuit structure of the comparator, as shown in Figure 5 , includes a first connector, a first capacitor, an eighth resistor, a ninth resistor, a comparator body, a tenth resistor, an eleventh resistor, a twelfth resistor, a second capacitor, a third capacitor, and a second connector.

[0091] The first end of the first connector is connected with the ground; one end of the first capacitor is connected with the other end of the first connector; one end of the eighth resistor is connected with the second power supply; one end of the ninth resistor is connected with the other end of the first capacitor and the other end of the eighth resistor respectively, and the other end of the ninth resistor is connected with the ground; the first port of the comparator body is connected with one end of the ninth resistor, the second port and the third port of the comparator body are both connected with the ground, the fourth port of the comparator body is connected with the third power supply; one end of the tenth resistor is connected with the fifth port of the comparator body, and the other end of the tenth resistor is connected with the fourth power supply; one end of the eleventh resistor is connected with one end of the tenth resistor; one end of the twelfth resistor is connected with the sixth port of the comparator body and the other end of the eleventh resistor respectively; one end of the second capacitor is connected with the third power supply, and the other end of the second capacitor is connected with the ground; one end of the third capacitor is connected with the third power supply, and the other end of the third capacitor is connected with the ground; one end of the second connector is connected with the other end of the twelfth resistor, and the other end of the second connector is connected with the ground. Figure 5 As shown in the figure, the first port of the comparator body is pin 2, the second port of the comparator body is pin 4, the third port of the comparator body is pin 8, the fourth port of the comparator body is pin 7, the fifth port of the comparator body is pin 3, and the sixth port of the comparator body is pin 6.

[0092] Optionally, in some embodiments, the electronic tester 10 described above comprises an emitter follower.

[0093] The input end of the emitter follower is connected with the second output end of the comparator, and the output end of the emitter follower is connected with the main control module 300.

[0094] Further, in some embodiments, the circuit structure of the emitter follower is as shown in the figure, comprising a fifth radio frequency interface, a thirteenth resistor, a second operational amplifier, a fourteenth resistor, and a sixth radio frequency interface. Figure 6

[0095] Specifically, one end of the fifth radio frequency interface is connected with the ground; one end of the thirteenth resistor is connected with the other end of the fifth radio frequency interface; the first port of the second operational amplifier is connected with the second port of the second operational amplifier, the third port of the second operational amplifier is connected with the other end of the thirteenth resistor, the fourth port of the second operational amplifier is connected with the negative electrode of the fifth power supply, the fifth port of the second operational amplifier is connected with the positive electrode of the fifth power supply; one end of the fourteenth resistor is connected with the first port of the second operational amplifier and the second port of the second operational amplifier respectively; one end of the sixth radio frequency interface is connected with the other end of the fourteenth resistor, and the other end of the sixth radio frequency interface is connected with the ground. Figure 5 ​As shown, the first port of the second operational amplifier is pin 2, the second port of the second operational amplifier is pin 6, the third port of the second operational amplifier is pin 3, the fourth port of the second operational amplifier is pin 4, and the fifth port of the second operational amplifier is pin 7.

[0096] Optionally, in some embodiments, the master module 300 comprises: an analog-to-digital conversion unit, a programmable logic unit, and a digital-to-analog conversion unit.

[0097] The input end of the analog-to-digital conversion unit is connected with the output end of the emitter follower; the first input end of the programmable logic unit is connected with the output end of the second attenuator, and the second input end of the programmable logic unit is connected with the output end of the analog-to-digital conversion unit; the input end of the digital-to-analog conversion unit is connected with the output end of the programmable logic unit, and the output end of the digital-to-analog conversion unit is connected with the signal output end 400.

[0098] Specifically, the circuit structure of the analog-to-digital conversion unit is as shown in Figure 7 The circuit structure of the digital-to-analog conversion unit is as shown in Figure 8 In the embodiments of the present application, the analog-to-digital conversion module adopts an ADS805 chip, which has a resolution of 14 bits, a maximum sampling rate of 20 MSPS, a signal-to-noise ratio (SNR) of ≥75 dB, and an input bandwidth of 100 MHz; the input end of the ADS805 is connected with a differential amplification circuit composed of a THS4151 chip to convert a single-ended signal into a differential signal for input, thereby effectively suppressing common-mode noise.

[0099] The digital-to-analog conversion module adopts a DAC904U chip, which has a resolution of 14 bits, a conversion rate of 165 MSPS, and an output signal bandwidth of 20 MHz; the differential current output of the DAC904U is converted into a voltage signal through a 51Ω resistor network and is converted into a single-ended output through an OPA690 operational amplifier, with an output voltage range of 0-5V and a total harmonic distortion (THD) of ≤-55 dBc.

[0100] The programmable logic unit FPGA built-in digital signal processing kernel realizes multi-functional cooperative control by using a hardware description language (Verilog HDL), and specifically, for the signal generator function, a 32-bit phase accumulator and a 12-bit waveform lookup table (LUT) are constructed based on a direct digital frequency synthesis (DDS) technology to support generation of a sine wave, a square wave, and a triangular wave, with a frequency coverage range of 0 Hz-5 MHz (frequency resolution of 1 Hz and phase resolution of 0.1°), wherein the duty cycle of the square wave is continuously adjustable in a range of 10%-90% by dynamically reloading the comparator threshold value (adjustment step of 0.1% and accuracy of ±1%), and the symmetry of the triangular wave is controlled by a linear interpolation algorithm, with a slope nonlinearity error of ≤0.5%.

[0101] For the function of oscilloscope, the ADS805 chip is used to realize 20MSPS full-bandwidth sampling in real-time sampling mode, and the random equivalent sampling mode is enabled for periodic signals higher than 10MHz. The phase offset of sampling time is dynamically adjusted by the high-precision clock divider (resolution 10ps) built in FPGA, 1024 non-uniform samples are collected within 1000 signal periods, and the waveform with equivalent sampling rate of 1GSPS is reconstructed by combining the cubic spline interpolation algorithm. The effective bandwidth is expanded to 100MHz, and an equal-precision frequency measurement module is integrated. The frequency measurement error is less than or equal to 0.01% by using a 100MHz reference clock counter.

[0102] For the function of logic analysis, 8-channel digital signal acquisition channels are configured, and a Schmitt trigger is independently set for each channel to perform level shaping (threshold accuracy ±10mV). A double-buffer storage architecture is used to realize a storage depth of 2.4k points (pre-trigger depth of 512 points). The trigger system supports rising edge / falling edge (minimum pulse width detection capability of 10ns), window trigger (pulse width range of 10ns-1s), and custom logic expression trigger (supports AND / OR / NOR combination). The trigger position jitter is less than or equal to 2ns. A UART / SPI / I2C protocol decoding engine is integrated synchronously, which can display the data frame format in real time and mark the error bits.

[0103] Optionally, in some embodiments, the main control module 300 further comprises an interactive display unit.

[0104] The interactive display module is electrically connected to the programmable logic unit.

[0105] Specifically, the interactive display unit is built-in with a two-dimensional array FIFO buffer (storage depth of 2.4k), which supports real-time waveform refreshing (≥30fps). The graphical interface integrates cursor measurement, FFT spectrum analysis, and protocol decoding functions, and the response delay is less than or equal to 50ms.

[0106] Here, the working principle of each unit in the main control module is described in detail. The main control module includes a main control unit constructed by a programmable logic device, a signal generation unit, an oscilloscope acquisition unit, a logic analysis unit, and an interactive display unit.

[0107] The main control unit integrates a digital waveform generation module, a data acquisition control module, and an asynchronous serial communication interface, and realizes multi-task cooperative scheduling through a hardware description language.

[0108] The signal generation unit includes a 14-bit digital-to-analog converter DAC904U chip and a 51Ω impedance matching circuit, which supports output of sine wave, square wave and triangular wave with frequency range of 0Hz to 5MHz. The duty cycle of the square wave is continuously adjustable in the range of 1% to 99%, the symmetry adjustment accuracy of the triangular wave is ±1%, and the waveform distortion rate is less than 5%.

[0109] The oscilloscope acquisition unit uses ADS805 analog-to-digital converter to achieve a sampling rate of 20 MSPS. The input signal is processed by a conditioning circuit composed of π-type attenuation network 1, OPA690 inverting amplifier, TLV3501 high-speed comparator and π-type attenuation network 2. The conditioning circuit supports an input range of 0 to 60 V peak-to-peak and expands the effective bandwidth to 100 MHz through an equivalent sampling algorithm to control the phase-locked loop module.

[0110] The logic analysis unit is configured with an 8-channel digital signal acquisition circuit and integrates a 2.4k-point FIFO memory with a trigger time jitter of less than 2 ns. The interactive display unit uses a 7-inch capacitive touch screen and communicates with the main control unit through UART protocol to realize multi-level menu interaction, waveform dynamic refresh (≥30 fps) and FFT spectrum analysis function, with an interface response delay of less than 50 ms.

[0111] In actual execution, the signal generation unit drives the DAC904U chip to output the target waveform by multiplying the system reference clock to 165 MHz through the phase-locked loop module in the programmable logic device. The 12-bit resolution waveform data is generated based on the direct digital frequency synthesis technology, the frequency adjustment step precision is 1 Hz, the phase resolution is 0.1°, and the output signal amplitude is adjustable from 0.1 V to 5 V through a digital attenuator. The user sets the waveform type, frequency, duty cycle and amplitude parameters in real time through the touch screen interface, the system automatically calculates the DDS phase accumulator initial value and DAC quantization code, the output signal total harmonic distortion rate is less than 5%, and the square wave rise time is less than 20 ns.

[0112] The equivalent sampling method of the oscilloscope acquisition unit is aimed at periodic signals higher than 10 MHz, adopts a random phase offset strategy, and collects sample points at non-uniform intervals within multiple signal periods, and the complete waveform is reconstructed through an interpolation algorithm, so that the effective bandwidth is improved to 100 MHz; combined with the equal-precision frequency measurement method, the built-in high-frequency counter of the programmable logic device is used to measure the period of the input signal, and the phase offset of the sampling clock is dynamically adjusted, the relative error of frequency measurement is less than 0.01%, and the time base accuracy is ±5ppm; in the input signal conditioning circuit, the π-type attenuation network 1 is composed of a 75Ω series resistor and a 243Ω parallel resistor, the working bandwidth covers DC to 150MHz, and the insertion loss is 20dB±0.5dB; the inverting amplifier adopts an OPA690 operational amplifier, which is configured with Rf=30kΩ and Rg=3kΩ to achieve 10 times gain, the -3dB bandwidth is 200MHz, and the output noise density is lower than 4nV / √Hz; the high-speed comparator is constructed based on TLV3501 chip and REF5025 reference source, and the output square wave passes through π-type attenuation network 2 composed of 21Ω series resistor and 250Ω parallel resistor, the working bandwidth covers DC to 150MHz, and the insertion loss is 3.6dB±0.1dB; the overall part voltage comparator output square wave amplitude is limited to 3.3V±5%, the response time is 5ns, and the return difference voltage can be programmed to adjust in the range of 10mV to 500mV.

[0113] The logic analysis unit adopts a one-hot code state machine to realize multi-channel interference suppression, the cross-talk between channels is lower than-50dB, supports 8-way parallel signal acquisition, and the single-channel maximum sampling rate is 100MSPS; the trigger module includes a pre-trigger depth of 512 points, a trigger condition register and a trigger position offset function, supports rising edge, falling edge, window pulse (pulse width range 10ns to 1s) and custom logic expression trigger mode; the storage depth is 2.4k points, supports circular storage and segmented capture, and has built-in UART, SPI and I2C protocol decoding engines, which can display data frame content in real time.

[0114] The software architecture of the interactive display unit is built based on an embedded real-time operating system, including a waveform display engine, an event manager and a protocol analysis library; a two-dimensional array is used to realize a 2.4k-point FIFO buffer, and a double-buffering mechanism is used to realize non- tearing waveform refreshing; the graphical interface supports multi-window display mode, and can simultaneously display time-domain waveform, frequency-domain spectrum and logic timing diagram, with a cursor measurement accuracy of 0.1% full scale; the configuration file management system supports parameter preset, user template storage and CSV data export functions; the system power supply uses a USB Type-C interface, the input voltage range is 5V to 12V, the overall power consumption is lower than 5W, the working temperature range is-10℃ to 50℃, the shell size is 200mm×150mm×50mm, the weight is 980g, and it meets the IP41 protection level.

[0115] It should be noted that the electronic tester of the embodiment of the present application adopts a USB Type-C interface for whole machine power supply, an input voltage of 5V-12V, and a whole machine power consumption of ≤5W; the shell size is 200mmx150mmx50mm, the weight is ≤1kg, and the working temperature range is -10℃ to 50℃.

[0116] To sum up, the electronic tester of the embodiment of the present application comprises a signal input port, a signal output port, a main control unit, and an interactive display unit, wherein the main control unit comprises a programmable logic device (FPGA), a digital-to-analog conversion module, an analog-to-digital conversion module, and a logic analysis module; the signal input port is connected to the input conditioning circuit, the analog-to-digital conversion module, and then to the FPGA in sequence; the signal output port is connected to the output end of the digital-to-analog conversion module; the FPGA is connected to the digital-to-analog conversion module, the analog-to-digital conversion module, and the logic analysis module, and communicates with the interactive display unit through the UART protocol; the input conditioning circuit is composed of a π-type attenuation network, a programmable gain amplifier, and a high-speed comparator, and supports an input range of 0-60V peak-to-peak value; the interactive display unit adopts a 7-inch capacitive touch screen, and realizes waveform display, parameter setting, and multi-level menu control.

[0117] To enable the relevant personnel in the art to further understand the electronic tester of the embodiment of the present application, the following will be described in detail in combination with specific embodiments.

[0118] The electronic tester of the embodiment of the present application integrates the functions of a signal generator, an oscilloscope, and a logic analyzer, the whole machine size is 200mmx150mmx50mm, the weight is 980g, the aluminum alloy shell meets the IP41 protection level, and the working temperature range covers -10℃ to 50℃. The system hardware architecture is shown in Figure 1 The main control unit adopts a Logos series FPGA of Changjiang Electronics Technology Co., Ltd., and is built-in with a multi-core processing architecture: a digital signal generation core realizes 0Hz-5MHz waveform output based on the DDS technology, a data acquisition core manages 50MSPS real-time sampling and equivalent sampling control, and a logic analysis core is configured with 8-channel independent state machines; the signal input port is connected to the ADS805 analog-to-digital converter (14 bits, 20MSPS) through a four-stage conditioning circuit of π-type attenuation network 1 (20dB attenuation ratio), an OPA690 programmable gain amplifier (-10dB to +40dB), a TLV3501 high-speed comparator (square wave shaping), and π-type attenuation network 2 (3.6dB attenuation ratio); the signal output port outputs 0-5V adjustable analog signals through the DAC904U digital-to-analog converter (14 bits, 165MSPS) and the OPA690 differential-to-single-ended circuit; the interactive display unit adopts a 7-inch capacitive touch screen (resolution 800x480), communicates with the FPGA through the UART protocol, and supports multi-window display (time domain waveform, FFT spectrum, and logic timing synchronous refresh).

[0119] The working process of the signal generator module is as follows: the FPGA internal DDS core generates 12-bit resolution waveform data, the phase accumulator bit width is 32 bits (frequency resolution is 0.023 Hz), and the waveform lookup table stores 4096-point sine wave, square wave and triangular wave data; the square wave duty cycle is continuously adjustable from 10% to 90% by dynamically adjusting the comparator threshold value (step 0.1%), and the triangular wave symmetry is controlled by a linear interpolation algorithm (slope error ≤0.5%); the DAC904U chip converts the digital signal into a differential current output, which is converted into a single-ended signal through a 51Ω impedance matching network and an OPA690 differential amplifier, and then passes through a seventh-order elliptic low-pass filter (cutoff frequency 5MHz) to suppress out-of-band noise, and the output sine wave THD ≤3% @5MHz, square wave rise time ≤20ns, amplitude stability ±1%.

[0120] The specific implementation of the oscilloscope module is as follows: the input signal is connected to the OPA690 emitter follower for impedance transformation, the buffer stage adopts a non-inverting amplification structure, Rf=0Ω, Rg=∞ to achieve unit gain, input bias current ±2nA, and the establishment time (0.1%) is 18ns, then it is sent to the ADS805 analog-to-digital converter, which captures the full-bandwidth signal at a rate of 20MSPS in real-time sampling mode; for periodic signals higher than 10MHz, the equivalent sampling mode is enabled, and the FPGA built-in clock phase fine-tuning unit (adjustment step 10ps) collects 1024 non-uniform samples within 100 signal periods, and reconstructs the equivalent 1GSPS sampling rate waveform through a cubic spline interpolation algorithm, and the bandwidth is expanded to 100MHz (time base error ±5ppm); the trigger system uses a digital hysteresis comparator (threshold accuracy ±10mV), supports edge triggering (rise / fall edge response time ≤2ns), pulse width triggering (10ns-1s) and window triggering, and has a pre-trigger depth of 512 points and a storage depth of 2.4k.

[0121] The hardware design of the logic analysis module is as follows: the 8-channel input signal passes through the FPGA internal one-hot code state machine to eliminate channel-to-channel crosstalk (isolation ≥50dB); the trigger engine supports logic expression combination (AND / OR / NOT gate), trigger position jitter ≤2ns, and 2.4k-point storage depth supports circular storage and segmented capture; the protocol decoding engine real-time analyzes UART (baud rate 1bps-10Mbps), SPI (clock frequency ≤50MHz) and I2C (standard / fast mode) protocol frames, and the error flag is highlighted in red on the touch screen.

[0122] The software architecture of the interactive display unit is as follows: based on the RT-Thread real-time operating system, a multi-thread task is constructed, a waveform display thread realizes a 30fps refresh rate through a two-dimensional array FIFO (double buffering mechanism), a FFT spectrum analysis adopts a base-2-FFT algorithm (point number 1024), and the frequency resolution is 48.8kHz; a parameter setting thread responds to a touch event, supports waveform amplitude / frequency / duty cycle linkage adjustment (knob control precision 0.1%), and a configuration file can be stored in an on-board Flash (capacity 128MB) or exported in CSV format; the system power supply is input by a USB Type-C interface 5V-12V, the whole machine standby power consumption is ≤1W, and the full load power consumption is ≤5W.

[0123] After the OPA690 emitter follower is added, the system signal transmission characteristics are significantly optimized through the network analyzer and signal integrity test system joint verification: the channel flatness gain fluctuation in the DC-100MHz frequency band is reduced from ±0.8dB of the original system to ±0.15dB (test conditions: input signal 2Vpp, sampling rate 20MSPS), indicating that impedance matching optimization effectively suppresses high-frequency signal attenuation; in terms of harmonic distortion characteristics, when an input 100MHz / 2Vpp sine wave is input, the second harmonic component is improved from -42dBc to -51dBc (FFT analysis point number 4096, window function Blackman-Harris), verifying the suppression effect of the buffer stage on nonlinear distortion; in the sampling accuracy index, the effective number of bits (ENOB) of the ADS805 analog-to-digital converter under full-scale input is improved from 12.1bit to 12.7bit (calculated according to the IEEE 1241 standard), and the quantization noise power spectral density is reduced by 3.2dB, proving that the emitter follower significantly improves the ADC front-end signal integrity by reducing the output impedance (≤1Ω) and improving the establishment speed (18ns@0.1%). The design innovation systematically improves the high-frequency signal acquisition accuracy and frequency response characteristics while maintaining the BOM cost.

[0124] The embodiment is verified by actual measurement to have excellent performance indicators: when the signal generator outputs a 5MHz sine wave, the total harmonic distortion (THD) is 2.8% (peak-to-peak value 3V), the frequency stability is ±5ppm, the rise time of a 1MHz square wave is 18ns under a duty cycle of 60%, and the overshoot rate is ≤3%; when the oscilloscope module captures a 100MHz sine wave (peak-to-peak value 2V), the waveform reconstruction error is ≤1.5% in the equivalent sampling mode, the vertical resolution effective bit number (ENOB) is 10.2bit, and the time base accuracy is ±5ppm; when the logic analyzer synchronously collects 8-way SPI signals (clock frequency 20MHz), the trigger position deviation is ≤1.7ns, the protocol decoding accuracy is 100%, and the UART / SPI / I2C protocol error bit real-time marking is supported; the whole machine can realize 8 hours of continuous work under 5V / 2A power supply (standby power consumption ≤1W, full load power consumption ≤5W), the shell temperature rise is ≤15℃, and there is no data loss or system crash during long-term operation.

[0125] In summary, the embodiment of the present application has the following advantages: through the multi-core architecture design and mixed signal processing technology of the programmable logic device (FPGA), the triple function integration of the signal generator, the oscilloscope and the logic analyzer is realized, and 0Hz-100MHz full-band signal testing is supported, wherein the signal generator outputs sine wave (THD≤3% at 5MHz), square wave (rise time ≤20ns) and triangular wave (linearity error ≤0.5%) based on the DDS technology, the oscilloscope realizes 20MSPS real-time sampling and 100MHz effective bandwidth (time base accuracy ±5ppm) extended by the equivalent sampling algorithm by using the 14-bit ADS805 analog-to-digital converter, and the logic analyzer is configured with 8-channel independent acquisition link (storage depth 2.4k, trigger jitter ≤2ns).

[0126] In addition, the whole machine adopts a compact aluminum alloy frame structure (200mm×150mm×50mm, weight 980g), integrates an IP41 protection level shell and a wide temperature working characteristic (-10℃ to 50℃), is equipped with a USB Type-C power supply interface (power consumption ≤5W), and is suitable for laboratory, industrial site and outdoor mobile scenes; the interactive system realizes multi-level menu control through a 7-inch capacitive touch screen, supports waveform parameter linkage adjustment (real-time feedback of frequency / amplitude / duty cycle), automatic protocol analysis (UART / SPI / I2C frame structure visualization) and CSV data export function, and the operation efficiency is improved by more than 50% (based on EEG user experience test data) compared with traditional instruments; in terms of cost control, the equivalent sampling algorithm is used to replace the 1GSPS high-speed ADC chip, and the programmable gain conditioning circuit is combined to reduce the front-end hardware redundancy, so that the material cost of the whole machine is reduced by 60% (BOM cost analysis shows that the core module cost is ≤￥500), while the professional level performance indicators (oscilloscope ENOB≥10bit@100MHz) are maintained, and the embodiment has significant market competitiveness and large-scale production value.

[0127] Therefore, the embodiment of the application realizes hardware resource multiplexing through FPGA multi-core dynamic scheduling mechanism, adopts equivalent sampling algorithm to expand the bandwidth of the oscilloscope to 100MHz, and reduces the cost by 60% compared with the traditional 1GSPS scheme; the input conditioning circuit integrates a pi-type attenuation network (dynamic range 60Vpp) and a programmable gain amplifier (minimum measurable signal 1mVpp), supports stable triggering in a harsh noise environment; the interactive system realizes parameter linkage control and protocol automatic identification based on a touch screen multi-thread architecture, and the debugging efficiency is improved by 70% in teaching experiments; the whole machine adopts an aluminum alloy frame and IP41 protection design, is suitable for a working environment of-10℃ to 50℃, and has no performance attenuation in industrial field vibration (5-500Hz / 0.5Grms) and humidity (95%RH) tests.

[0128] The electronic tester provided in the embodiment of the application comprises a signal input end, a signal processing circuit, a main control module and a signal output end, wherein the signal input end is configured to receive a to-be-tested signal; one end of the signal processing circuit is connected with the signal input end, and the signal processing circuit generates a conditioned signal after conditioning the to-be-tested signal; one end of the main control module is connected with the other end of the signal processing circuit, the main control module is configured to output a waveform signal meeting a first waveform condition according to the conditioned signal, and / or display the conditioned signal, and / or generate a logic analysis result according to the conditioned signal; and one end of the signal output end is connected with the other end of the main control module, and the signal output end is configured to output the waveform signal, and / or the conditioned signal, and / or the logic analysis result. Therefore, the problem of significant limitations of electronic test instruments in terms of functional integration, portability and high-frequency signal processing capability is solved, and the electronic tester integrates a signal generator, an oscilloscope and a logic analyzer and has high precision, a wide frequency band and portability.

[0129] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0130] In addition, the terms "first", "second", etc. are used herein only to describe different instances, and do not imply or suggest relative importance or a number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0131] Any process or method descriptions or descriptions of the flow diagrams described herein can be understood as representing modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions (or steps) described by that module, segment, or portion of code. The various embodiments of the application can include additional or fewer steps or methods as described in the examples provided herein, and the order of the steps or methods can be changed, including the use of concurrent steps or methods, unless otherwise specifically limited.

[0132] It should be understood that portions of the present application can be realized with hardware, software, firmware or a combination thereof. In the above embodiments, the steps or methods can be realized with software or firmware stored in a memory and executed by a suitable instruction execution system. As in another embodiment, if realized with hardware, any one or a combination of the following technologies known in the art can be used: discrete logic circuit with logic gates for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gates, programmable gate array, field programmable gate array, etc.

[0133] Those skilled in the art of the present technology can understand that all or part of the steps carried out by the above-mentioned embodiment method can be completed by a program instructing the relevant hardware, and the program can be stored in a computer readable storage medium. The program, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0134] Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

Claims

1. An electronic tester characterized by, The application relates to a signal processing device, comprising: a signal input end for receiving a signal to be tested; a signal processing circuit, one end of which is connected with the signal input end, and the signal processing circuit generates a processed signal after processing the signal to be tested; a main control module, one end of which is connected with the other end of the signal processing circuit, the main control module outputs a waveform signal meeting a first waveform condition according to the processed signal, and / or displays the processed signal, and / or generates a logic analysis result according to the processed signal; a signal output end, one end of which is connected with the other end of the main control module, for outputting the waveform signal, and / or the processed signal, and / or the logic analysis result.

2. The electronic tester of claim 1, wherein, The signal processing circuit comprises a processing circuit, a selector and an emitter follower, wherein: the processing circuit is electrically connected with the selector; the processing circuit is electrically connected with the emitter follower.

3. The electronic tester of claim 2, wherein, The processing circuit comprises a first attenuator, an amplifier, a comparator and a second attenuator, wherein: the input end of the first attenuator is connected with the signal input end, and the output end of the first attenuator is connected with the input end of the selector; the input end of the amplifier is connected with the first output end of the selector, and the output end of the amplifier is connected with the first input end of the comparator; the second input end of the comparator is connected with the selector, and the first output end of the comparator is connected with the second attenuator; the output end of the second attenuator is connected with the main control module.

4. The electronic tester of claim 2, wherein, The input end of the emitter follower is connected with the second output end of the comparator, and the output end of the emitter follower is connected with the main control module. The main control module comprises:

5. The electronic tester of claim 1, wherein, an analog-to-digital conversion unit, the input end of which is connected with the output end of the emitter follower; a programmable logic unit, the first input end of which is connected with the output end of the second attenuator, and the second input end of which is connected with the output end of the analog-to-digital conversion unit; a digital-to-analog conversion unit, the input end of which is connected with the output end of the programmable logic unit, and the output end of which is connected with the signal output end. The main control module further comprises:

6. The electronic tester of claim 1, wherein, an interactive display unit, which is electrically connected with the programmable logic unit. The first attenuator and the second attenuator both comprise:

7. The electronic tester of claim 3, wherein, a first radio frequency interface, one end of which is connected with a ground wire; a first resistor, the first end of which is connected with the other end of the first radio frequency interface, and the second end of which is connected with the ground wire; a second resistor, one end of which is connected with the third end of the first resistor; a third resistor, the first end of which is connected with the other end of the second resistor, and the second end of which is connected with the ground wire; a second radio frequency interface, one end of which is connected with the third end of the third resistor, and the other end of which is connected with the ground wire. The amplifier comprises:

8. The electronic tester of claim 3, wherein, a third radio frequency interface, one end of which is connected with a ground wire; ​ A fourth resistor, one end of the fourth resistor is connected with the other end of the third radio frequency interface; A fifth resistor, one end of the fifth resistor is connected with the ground wire; A first operational amplifier, a first port of the first operational amplifier is connected with the other end of the fourth resistor, a second port of the first operational amplifier is connected with the other end of the fifth resistor, a third port of the first operational amplifier is connected with a negative electrode of a first power supply, a fourth port of the first operational amplifier is connected with a positive electrode of the first power supply; A sixth resistor, one end of the sixth resistor is connected with the other end of the fourth resistor; A seventh resistor, one end of the seventh resistor is connected with the other end of the sixth resistor and a fifth port of the first operational amplifier respectively; A fourth radio frequency interface, one end of the fourth radio frequency interface is connected with the other end of the seventh resistor, the other end of the fourth radio frequency interface is connected with the ground wire.

9. The electronic tester of claim 3, wherein, The comparator comprises: A first connector, one end of the first connector is connected with the ground wire; A first capacitor, one end of the first capacitor is connected with the other end of the first connector; An eighth resistor, one end of the eighth resistor is connected with a second power supply; A ninth resistor, one end of the ninth resistor is connected with the other end of the first capacitor and the other end of the eighth resistor respectively, the other end of the ninth resistor is connected with the ground wire; A comparator body, a first port of the comparator body is connected with one end of the ninth resistor, a second port and a third port of the comparator body are both connected with the ground wire, a fourth port of the comparator body is connected with a third power supply; A tenth resistor, one end of the tenth resistor is connected with a fifth port of the comparator body, the other end of the tenth resistor is connected with a fourth power supply; An eleventh resistor, one end of the eleventh resistor is connected with one end of the tenth resistor; A twelfth resistor, one end of the twelfth resistor is connected with a sixth port of the comparator body and the other end of the eleventh resistor respectively; A second capacitor, one end of the second capacitor is connected with the third power supply, the other end of the second capacitor is connected with the ground wire; A third capacitor, one end of the third capacitor is connected with the third power supply, the other end of the third capacitor is connected with the ground wire; A second connector, one end of the second connector is connected with the other end of the twelfth resistor, the other end of the second connector is connected with the ground wire.

10. The electronic tester of claim 4, wherein, The emitter follower comprises: A fifth radio frequency interface, one end of the fifth radio frequency interface is connected with the ground wire; A thirteenth resistor, one end of the thirteenth resistor is connected with the other end of the fifth radio frequency interface; A second operational amplifier, a first port of the second operational amplifier is connected with a second port of the second operational amplifier, a third port of the second operational amplifier is connected with the other end of the thirteenth resistor, a fourth port of the second operational amplifier is connected with a negative electrode of a fifth power supply, a fifth port of the second operational amplifier is connected with a positive electrode of the fifth power supply; A fourteenth resistor, one end of the fourteenth resistor is connected with the first port of the second operational amplifier and the second port of the second operational amplifier respectively; A sixth radio frequency interface, one end of the sixth radio frequency interface is connected with the other end of the fourteenth resistor, and the other end of the sixth radio frequency interface is connected with the ground wire.

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