Electronic equipment and chip stacking framework thereof

Abstract

The embodiment of the utility model discloses electronic equipment and a chip stacking framework thereof. The chip stacking framework comprises a first circuit board, a chip, a memory and a first capacitor, the first circuit board comprises a first face and a second face which are oppositely arranged, the chip is connected to the first face of the first circuit board, the second face, opposite to the memory, of the first circuit board is provided with a groove, the first capacitor is arranged in the groove and connected with the chip through the first circuit board, and the memory is connected to the second face on the periphery of the groove. According to the arrangement, the vertical heat dissipation path of the chip can be shortened, and the thermal resistance is effectively reduced. Meanwhile, the first capacitor is arranged in the groove of the side face where the memory is located, and the area utilization efficiency of the circuit board can be improved. In addition, the memory and the chip can jointly reinforce the board body strength of the first circuit board, the length of an interconnection link between the memory and the chip is effectively shortened, and the signal transmission loss is further reduced.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of terminal equipment, in particular to an electronic device and a chip stacking architecture thereof. BACKGROUND

[0002] With the increasing performance and computing power of terminal electronic devices, the heat dissipation problem of processor chips is increasingly prominent. In the related art, the packaging of a chip and a memory is implemented by using a typical package-on-package (POP) technology, the chip is assembled on a printed circuit board (PCB), and the memory is packaged and stacked on the top of the chip package. The packaging architecture forms a vertical heat dissipation path of the chip, and the heat generated by the chip is sequentially dissipated through the memory, a thermal interface material (TIM) and a uniform plate. Based on the configuration mode that the memory is located on the heat dissipation path of the chip, the vertical thermal resistance is large, and in particular, the heat generated by the operation of the chip is difficult to release quickly, which directly affects the performance of the chip. CONTENT OF THE UTILITY MODEL

[0003] The embodiment of the present application provides an electronic device and a chip stacking architecture thereof, which effectively improves the heat dissipation performance of the chip through structural optimization.

[0004] The first aspect of the embodiment of the present application provides a chip stacking architecture, which comprises a first circuit board, a chip, a memory and a first capacitor. The first circuit board comprises a first surface and a second surface arranged oppositely, the chip is connected to the first surface of the first circuit board, the second surface has a groove, the first capacitor is arranged in the groove and connected to the chip through the first circuit board, and the memory covers the groove and is electrically connected to the part of the second surface located at the outer periphery of the groove. In the prior art, based on the configuration mode that the memory is located on the heat dissipation path of the chip, the vertical thermal resistance is large. The present application moves the memory from the heat dissipation path to the second surface, but the capacitor is placed on the second surface, so the memory and the capacitor conflict with each other. The present application sets a groove on the second surface, the capacitor is placed in the groove, the memory covers the groove and is connected to the part of the second surface located at the outer periphery of the groove, that is, the capacitor and the memory are stacked in the direction perpendicular to the first circuit board. In this way, the capacitor and the memory are accommodated on the second surface without increasing the area of the second surface, which solves the problem of conflict between the memory and the capacitor. Therefore, the chip stacking architecture of the present application can shorten the vertical heat dissipation path of the chip, reduce the thermal resistance and effectively improve the heat dissipation performance of the chip without changing the size.

[0005] In addition, the memory is connected with the part of the second surface located at the outer periphery of the groove, and can be used together with the chip on the first surface to reinforce the strength of the board body of the first circuit board, and reasonably balance the influence of the opening of the groove on the strength of the board body. In actual application, the first capacitor and the memory can have a spacing therebetween to avoid the memory from being pressed against the first capacitor to generate assembly stress, and ensure the reliability of the operation of the device.

[0006] In addition, based on the structural feature that the chip and the memory are arranged on two sides of the first circuit board respectively, the distance between the corresponding pins of the memory and the chip is short, the length of the interconnection link between the two is effectively shortened, the signal transmission loss is further reduced, the high-speed communication between the chip and the memory is met, and technical support is provided for improving the signal transmission rate.

[0007] Exemplarily, the chip can be a processor chip of an electronic device.

[0008] Based on the first aspect, the embodiments of the present application further provide a first implementation manner of the first aspect: the chip stacking architecture further comprises a second capacitor, the chip comprises a packaging substrate, and the second capacitor is arranged on the packaging substrate of the chip, and the first capacitor and the second capacitor are used to build a power delivery network (PDN). In this way, the second capacitor is arranged close to the power port of the chip, and the low-frequency noise filtering effect is good, and the power integrity can be improved.

[0009] In actual application, the second capacitor is provided as a plurality of second capacitors and is arranged on the packaging substrate beside the chip. In this way, on the one hand, the problem of branch bypass caused by the lengthening of the link in the PDN can be overcome, and on the other hand, the power integrity requirement of the local power network can also be met.

[0010] Based on the first aspect or the first implementation manner of the first aspect, the embodiments of the present application further provide a second implementation manner of the first aspect: the chip stacking architecture further comprises a third capacitor used to build a power delivery network, and the third capacitor is arranged between the second surface at the outer periphery of the groove and the memory. In this way, the arrangement space between the memory and the first circuit board is fully utilized, so that each capacitor is located on the power supply link, and at the same time, the third capacitor is arranged close to the power port of the chip to meet the power integrity requirement. Overall, it has good integration, can effectively reduce the thermal resistance under the same area, and takes into account the good power integrity requirement.

[0011] Exemplarily, the third capacitor can be an ultra-thin packaging capacitor.

[0012] In the third implementation of the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, the bottom edge of the groove is provided with a copper sheet. In this way, the groove can be formed by laser processing, the copper sheet can block the laser during the groove forming process, and the laser can not penetrate too deep to affect the inner layer traces, and the copper sheet can also prevent the groove from being too shallow to affect the assembly of the first capacitor.

[0013] For example, the copper sheet can be located on the inner layer of the board and have a certain width to reliably block the laser. For another example, the inner layer copper sheet can be used as a mark point to assist the laser in positioning and controlling the size and position accuracy of the groove on the board.

[0014] In actual applications, the copper sheet can be connected to the inner layer traces of the board as needed.

[0015] In the fourth implementation of the first aspect based on the third implementation of the first aspect, a PI film layer is arranged on the bottom of the groove. In the processing of the first circuit board, the PI film layer can be pasted on the bottom of the groove, so that the removed part of the board can be easily removed after cutting, and the opening operation can be quickly realized.

[0016] In the fifth implementation of the first aspect based on the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, the signal traces between the chip and the memory are arranged on the trace layer close to the first surface. In actual applications, the modified semi-additive process (mSAP) can be applied to the signal fan-out layer, and the micro-via process can be applied to the whole board to improve the trace density and concentrate the fan-out signals. In this way, more trace area can be reserved for the PDN link, and relatively wide power supply traces can be arranged to make the link impedance between the power supply end and the power consumption end as small as possible to meet the power integrity requirement.

[0017] In the sixth implementation of the first aspect based on the fifth implementation of the first aspect, the signal fan-out traces of the chip are arranged on the trace layer close to the first surface or the trace layer close to the second surface. In this way, more trace area can be reserved for the PDN link.

[0018] In the seventh implementation of the first aspect based on the sixth implementation of the first aspect, the power distribution network traces are arranged on the middle trace layer of the first circuit board. Overall, the signal fan-out is concentrated in the shallow layer and close to the outer side of the chip, and the power distribution network is concentrated in the deep layer and close to the middle of the chip, which effectively avoids the mutual interference of the two in space and electrical performance.

[0019] According to the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, the eighth implementation of the first aspect is provided. The chip includes the core particle and the packaging substrate. The surface of the core particle opposite to the packaging substrate is not covered by the packaging material, that is, the core particle is exposed to the chip packaging body. In actual application, the chip can be attached to the vapor chamber through the thermal interface material. In this way, the core particle as the heat source can be in contact with the vapor chamber through the thermal interface material, the shielding cover and / or the vapor chamber, for example but not limited to, the heat can be transferred to the device frame. The heat dissipation path is further shortened, and the thermal resistance can be effectively reduced.

[0020] Exemplarily, the thermal interface material can be of different types, for example but not limited to, thermal conductive gel, silicone grease, graphene material, silver layer or copper block, to improve the heat conduction efficiency according to actual needs.

[0021] In other actual applications, an on-chip fan can also be used for heat dissipation on the chip. In this way, the chip temperature can be managed by controlling the fan speed, and the chip heat dissipation can be optimized in an active heat dissipation manner, to improve the system performance and reliability.

[0022] According to the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, or the seventh implementation of the first aspect, the ninth implementation of the first aspect is provided. The chip stacking architecture further includes a second circuit board connected to the first circuit board through a frame plate. The first circuit board, the second circuit board and the frame plate form a containing space, and the memory is located in the containing space. The chip stacking architecture further includes a power management unit for constructing a power distribution network. The power management unit is connected to the second surface and located in the containing space. In this way, the overall integration of the architecture is further improved, and the board area is effectively controlled.

[0023] Exemplarily, the second circuit board can be a radio frequency board provided with a radio frequency component, to realize the data transmission and communication function of the electronic device. In actual application, a connector for adapting to the battery side can also be arranged on the second circuit board.

[0024] The second aspect of the embodiments of the present application provides an electronic device, which comprises a shell, a middle frame and the chip stack architecture as described above, the chip stack architecture is mounted on the shell, or the chip stack architecture is mounted on the middle frame.

[0025] Exemplarily, the electronic device can be a mobile phone, a tablet computer or a computer, etc. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A chip stack architecture schematic diagram of an electronic device provided by the embodiments of the present application;

[0027] Figure 2 A partial enlarged schematic diagram of part I in FIG. 1; Figure 1

[0028] Figure 3 A partial front projection view of the second surface of the first circuit board shown in FIG. 1; Figure 1

[0029] Figure 4 A partial assembly relationship schematic diagram of the first circuit board, the memory and the recess shown in FIG. 1; Figure 1

[0030] Figure 5 A planning diagram of the memory wiring layer of the first circuit board shown in FIG. 1; Figure 1

[0031] Figure 6 A simple wiring trend diagram of an inner layer of the first circuit board shown in FIG. 1; Figure 1

[0032] Figure 7 A chip stack architecture schematic diagram of another electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application provide an implementation scheme which can effectively improve the heat dissipation capacity of the chip architecture, and at the same time, meet the chip heat dissipation requirement and provide technical support for ensuring the chip performance.

[0034] ​​​​​With the development of terminal electronic equipment performance, the power consumption of processor chip increases, and the integration improves, so that the heat dissipation problem of the processor chip is increasingly prominent. If the heat generated during the operation of the chip is not dissipated in time, the temperature will be too high, which will cause the performance of the chip to decrease or even damage. At the same time, high temperature will also accelerate the aging of electronic components and shorten the service life of electronic equipment. In a typical chip POP packaging architecture, the chip is assembled on the surface of the PCB, and the memory is stacked on the top of the chip. The memory can be in contact with the heat sink, such as but not limited to a vapor chamber (VC), to exchange heat in the vertical direction to form a heat dissipation path of the chip. The heat generated by the chip is sequentially dissipated through the memory, the TIM and the VC, the memory makes the thermal resistance of the heat dissipation path larger, which affects the heat dissipation effect, causes the temperature of the chip to rise, and affects the performance and reliability of the chip.

[0035] Based on this, the electronic device provided by the embodiments of the present application includes a first circuit board, a chip, a memory and a first capacitor. The first circuit board includes a first surface and a second surface arranged oppositely, the chip is connected to the first surface of the circuit board, the second surface has a groove, the first capacitor is arranged in the groove, and the memory is connected to the power supply contact of the chip through the first circuit board. The contact of the memory is electrically connected to the part of the second surface located outside the periphery of the groove. In the prior art, based on the configuration mode that the memory is located on the heat dissipation path of the chip, the vertical thermal resistance is large. The present application moves the memory from the heat dissipation path to the second surface, but the capacitor is placed on the second surface, so the memory and the capacitor conflict. The present application sets a groove on the second surface, the capacitor is placed in the groove, the memory covers the groove, and is connected to the part of the second surface located outside the periphery of the groove, that is, the capacitor and the memory are stacked in the direction perpendicular to the first circuit board. In this way, the capacitor and the memory are accommodated on the second surface without increasing the area of the second surface, which solves the problem of conflict between the memory and the capacitor. Therefore, the chip stacking architecture of the present application can still shorten the vertical heat dissipation path of the chip, reduce the thermal resistance, and effectively improve the heat dissipation performance of the chip under the condition that the size does not change.

[0036] In addition, the memory is connected to the second surface of the first circuit board outside the periphery of the groove, and together with the chip located on the first surface, it reinforces the board body strength of the first circuit board, effectively balancing the influence of the opening of the groove on the board body strength. In addition, based on the structural characteristics that the chip and the memory are arranged on the two side surfaces of the first circuit board respectively, the distance between the corresponding pins of the memory and the chip is small, which effectively shortens the length of the interconnection link between the two, further reduces the signal transmission loss, and meets the high-speed communication between the chip and the memory, providing technical support for improving the signal transmission rate.

[0037] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below. Please refer to Figure 1The circle is a schematic diagram of a chip stacking architecture of an electronic device provided by an embodiment of the present application.

[0038] In the embodiment, the chip stacking architecture 100 comprises a first circuit board 10 and a second circuit board 20, the first circuit board 10 and the second circuit board 20 are connected by a frame board 30, and a containing space is formed between the first circuit board 10, the second circuit board 20 and the frame board 30. Devices can be arranged in the containing space according to product design requirements, so as to improve the internal space utilization of the electronic device. In a specific implementation, the frame board 30 can connect the first circuit board 10 and the second circuit board 20 to realize electrical connection. For example, but not limited to, a welding process is used to realize the corresponding electrical connection. Details are not described here.

[0039] Exemplarily, the chip stacking architecture 100 can be used in electronic devices such as mobile phones, tablets or computers. Here, the first circuit board 10 is a main board provided with electronic elements such as chips and memories, and the second circuit board 20 is a radio frequency board (RF Board) provided with radio frequency (RF) components 7 to realize data transmission and communication functions. As shown in the figure, the connector 8 can be provided on the second circuit board 20 for side docking with the battery (not shown in the figure).

[0040] Among them, the chip 1 and the memory 2 are respectively arranged on the two sides of the first circuit board 10, the chip 1 is connected to the first side of the first circuit board 10, that is, the chip grain (DIE) 11 of the chip 1 is electrically connected to the top layer of the first circuit board 10 through the contacts on the bottom of the packaging substrate 12, and the memory 2 is attached to the second side of the first circuit board 10 relative to the chip 1, which can reduce the thermal resistance of the vertical heat dissipation path of the chip top surface.

[0041] Here, the chip 1 can be a system on chip (SoC) package formed based on the packaging substrate 12. In order to further reduce the thermal resistance, the chip grain 11 of the chip 1 can be exposed to the package, that is, the surface of the chip grain 11 opposite to the packaging substrate 12 is not covered by packaging material, and is in a bare state. In this way, as a heat source, the chip grain 11 can be in contact with the heat-conducting interface material 3, the shielding cover 4 and / or the uniform plate 5, for example but not limited to, heat can be transferred to the device middle frame 40, or the device shell or the screen side, the heat dissipation path is further shortened, the thermal resistance can be effectively reduced, and the SoC heat dissipation is optimized. The simulation optimization results show that, compared with the related typical stacking architecture, under the same conditions at 15W power consumption, the chip 1 of the chip stacking architecture 100 can increase the continuous time in high performance mode to more than 200s.

[0042] In a specific implementation, the shielding cover 4 can be a copper shielding cover, which provides good electromagnetic interference shielding performance and is also a good thermal conductor. The vapor chamber 5 can have an adaptive concave-convex surface to tightly fit the heat exchange surface. The thermal interface material 3 can be of different types, such as but not limited to thermal conductive gel, silicone grease, graphene material, silver layer or copper block, to improve the thermal conduction efficiency according to actual needs. Among them, the silver layer as the TIM can be sprayed on the surface of the chip 1, has strong adhesion, high process reliability, high thermal conductivity, and good electromagnetic shielding effect. In a possible implementation scheme, an electromagnetic interference (EMI) silver layer can be used to replace the shielding cover 4 to provide electromagnetic shielding effect, and the space occupation can be reduced.

[0043] In addition, in addition to selectively configuring the thermal interface material 3, the shielding cover 4 and / or the vapor chamber 5, an on-chip fan can also be used. In this way, the chip temperature can be managed by controlling the fan speed to actively dissipate heat, optimize SoC heat dissipation, and improve system performance and reliability. The specific implementation can be determined according to the overall design requirements of the product, and the embodiments of the present application are not limited.

[0044] At the same time, the first circuit board 10 is also provided with a first capacitor 61 for building a PDN, and the second surface of the first circuit board 10 opposite to the memory 2 has a recess 101, and a plurality of first capacitors 61 are built in the recess 101 and connected with the power supply contacts on the chip 1 side through the first circuit board 10 to filter out the noise interference on the power supply link. It should be understood that the specific constituent elements of the PDN can be realized by using the prior art, and the overall design requirements of the product architecture can be determined to obtain good power integrity requirements.

[0045] As shown in the figure, the memory 2 is located in the accommodation space between the first circuit board 10, the second circuit board 20 and the frame plate 30. In order to make full use of the accommodation space, other electronic elements for building a PDN such as a power management unit (PMU) 62 can also be arranged in the accommodation space, and the overall design requirements of the product can be arranged. The embodiments of the present application are not limited.

[0046] Please see Figure 2 and Figure 3 , wherein, Figure 2 is Figure 1 , the first part is an enlarged schematic view, Figure 3 is Figure 1 , the second surface of the first circuit board is shown in a local orthographic projection view, which shows the recess 101 and the pad layout of the outer periphery, that is, the corresponding layout of the inclusions in the projection area of the second surface.

[0047] Combination Figure 1 and Figure 2 As shown, memory 2 is connected to the second side of the first circuit board 10 around the groove 101. That is, the contacts 21 of memory 2 are electrically connected to the bottom layer of the first circuit board 10, and are electrically connected to the signal pins of chip 1 through vias and traces arranged in the first circuit board 10. In this embodiment, memory 2 is connected to the second side of the first circuit board 10 around the groove 101, and chip 1 is connected to the first side of the first circuit board 10, thereby forming a relatively stable physical connection structure. In this way, the board strength of the first circuit board 10 is reinforced by memory 2 and chip 1, which can avoid structural stress at the groove position and improve the overall reliability of the stacked architecture.

[0048] In a specific implementation, the groove depth D of the recess 101 formed on the first circuit board 10 needs to be adapted to the package size of the first capacitor 61, while also meeting the requirement of maintaining a safe distance between the first capacitor 61 and the memory 2, so as to avoid the memory 2 pressing against the first memory 3 and generating assembly stress, thus ensuring the reliability of device operation. For example, the first capacitor 61 can be a 01005 packaged capacitor, and correspondingly, the groove depth D of the recess 101 can be 200um. Of course, the groove depth D of the recess 101 can be adjusted adaptively for different selections of the first capacitor 61. This application embodiment does not limit this.

[0049] like Figure 3 As shown, capacitor pads 10a are arranged at the bottom of the groove 101, and memory pads 10b are arranged on the bottom layer of the first circuit board 10 on the outer periphery of the groove 101. The pins of each first capacitor 61 can be soldered to the corresponding capacitor pad 10a to achieve electrical connection, thereby filtering out noise interference. The contacts 21 of the memory 2 are soldered to the memory pads 10b on the outer periphery of the groove 101 to achieve electrical connection.

[0050] To avoid the potential impact on noise filtering caused by placing capacitors of some power distribution networks far from the corresponding power pins (e.g., solder balls) of the SoC, multiple electronic components that form a PDN can include a second capacitor 63 placed on the packaging substrate 12 of the chip 1. That is, multiple on-chip capacitors can be placed next to the chip of the SoC substrate. On the one hand, this can overcome the problem of branch bypass caused by link lengthening in the PDN, and on the other hand, it can also meet the power integrity requirements of the local power network.

[0051] Additionally, for the multiple electronic components that construct the PDN, a third capacitor 64 may also be included, which is disposed on the outer periphery of the recess 101 between the memory 2 and the second surface of the first circuit board 10, for example... Figure 2 and Figure 3As shown, the third capacitor 64 is an ultra-thin package capacitor, for example, a 0202 ultra-thin package capacitor with a capacitance of 220 nF can be used, the height of the ultra-thin package capacitor is 90 um, which is significantly lower than the height of the solder ball (about 150 um) of the contact 21 of the memory 2, and the available space between the memory 2 and the first circuit board 10 is fully utilized, so that each capacitor is located on the PMU 62 to the chip 1 power supply link, and the second capacitor 63 and the third capacitor 64 are arranged close to the power supply port (power supply solder ball) of the chip 1, and the low-frequency noise filtering effect is good, thereby meeting the power integrity requirement. In this way, the chip stacking architecture 100 has good integration, can effectively reduce the thermal resistance under the same area, and meets the good power integrity requirement.

[0052] In the embodiment, the plurality of third capacitors 64 are arranged at intervals, and can be arranged on the first circuit board 10. Figure 3 The number and arrangement position of the third capacitors 62 can be determined according to actual needs.

[0053] In other specific implementations, the second capacitor 63 and the third capacitor 64 can be selectively arranged, and the specific arrangement can be determined according to the overall design requirement of the product architecture. The embodiment of the present application is not limited. In addition, in order to further improve the power integrity, a fourth capacitor 65 can be arranged on the first surface of the first circuit board 10, and a fifth capacitor 66 can be arranged on the second surface of the first circuit board 10, which are collectively used as electronic elements of the PDN for transmitting current and delivering power, and achieve the functions of decoupling, filtering or energy compensation.

[0054] For the groove 101 opened on the board body of the first circuit board 10, a laser slotting method can be used. For example Figure 1 And Figure 4 Wherein, Figure 4 is Figure 1 A partial assembly relationship schematic diagram of the first circuit board, the memory and the groove shown in the embodiment.

[0055] In order to improve the groove depth D size accuracy of the groove 101, a copper skin 1011 can be arranged at the edge of the groove bottom area of the groove 101. In this way, the laser can be blocked during slotting to avoid the laser from breaking through too deep to affect the inner layer wiring, and at the same time, the first capacitor 61 can be avoided from being affected by being too shallow. In specific implementations, the copper skin 1011 can be located in the board internal wiring layer with consistent height position and has a certain width to reliably block the laser and accurately control the groove depth D size accuracy of the groove 101; in addition, the inner layer copper skin 1011 can be used as a mark point to assist the laser in positioning and controlling the size position accuracy of the groove 101 in the board. In other specific implementations, the copper skin 1011 can also be connected to the internal wiring as needed. Here, further description is not given.

[0056] In addition, in order to facilitate opening of the cover after laser cutting, a PI film layer 1012 can be pasted at the groove bottom position of the groove 101 in the processing procedure of the first circuit board 10, so as to facilitate removal of the completed cut board body part and quickly realize the opening operation.

[0057] In addition, the capacitor pad 10a at the groove bottom of the groove 101 can be realized by different processes, for example, but not limited to, tin spraying or 3D steel screen printing tin can be used to make tin, which can be realized by the prior art. Here, no longer tedious.

[0058] In the embodiment, based on the configuration mode of the groove 101 and the memory 2, the signal fan-out and PDN power integrity of the chip 1 and the memory 2 need to be reasonably considered. In the specific implementation, the wiring layer close to the surface of the first circuit board 10 can be used as a fan-out wiring layer, for example, the top layer wiring layer close to the first surface of the first circuit board 10 and one or two layers of wiring layer adjacent to the top layer wiring layer can be used as the signal fan-out layer of the chip 1 and the memory 2.

[0059] Specifically, the mSAP process is applied in the signal fan-out layer, and the micro-hole process is applied throughout the board, which improves the wiring density and concentrates the fan-out signals. In this way, more wiring area can be reserved for the PDN link, and relatively wide power supply wiring (not shown in the figure) can be arranged to make the link impedance between the power management unit 62 (power supply end) and the chip 1 (power consumption end) as small as possible, so as to meet the power integrity requirement.

[0060] Of course, the fan-out wiring of the chip 1 can be realized only by the top layer wiring layer, that is, all wiring networks related to data transmission between the memory 2 and the chip 1 can be completed in the same layer. In this way, more layers of intermediate wiring layers can be provided for PDN link wiring. Please refer to Figure 5 and Figure 6 wherein, Figure 5 is Figure 1 the planning diagram of the wiring layer where the memory wiring of the first circuit board shown in FIG. 1 is located, Figure 6 is Figure 1 the inner layer wiring trend diagram of the first circuit board shown in FIG. 1.

[0061] As shown in FIG. 1, Figure 5 The four corner areas A can be used to concentrate the wiring of the pins of the chip 1 and the pins of the memory 2, and the outer side area B of the remaining area can be used for signal fan-out wiring of the chip 1, and the middle area C is used for middle power network wiring of the chip 1, so that the wiring layer space can be effectively utilized. As shown in Figure 6As shown, the fan-out signal lines of the chip 1 and the memory 2 are schematically shown by thin lines, and the power supply lines of the power management unit 62 are schematically shown by thick lines. Here, to ensure the power integrity, the signal fan-out is concentrated in the shallow layer (the top routing layer and / or the adjacent routing layer close to the top routing layer) and close to the outer side of the chip 1, and the power distribution network is concentrated in the deep layer and close to the middle of the chip, thereby avoiding the mutual interference of the two in space and electrical performance to the greatest extent.

[0062] It should be noted that, based on the chip stacking architecture 100 provided in the embodiments of the present application, the signal fan-out routing and the PDN link routing are not limited to Figure 5 and Figure 6 The exemplary schematic routing trend can be adjusted according to actual product design requirements. The embodiments of the present application are not limited.

[0063] In a specific implementation, the routing width of the signal fan-out routing layer can be reduced to 30 um, and the via hole pad diameter can be reduced to 130 um. According to an example calculation, the BGA (Ball Grid Array) fan-out density can be improved by about 50% as a whole, so that the power integrity routing requirements can be met on the basis of completing the fan-out. The simulation optimization result shows that, based on the process technology, the area yield is obtained by reasonably allocating the routing resources, and the corresponding routing increased by the recess 101 and the memory 2 arrangement can be compatible with the same area as the traditional scheme, while the power integrity requirements are met.

[0064] The chip stacking architecture scheme described in the foregoing embodiments takes the first circuit board 10, the second circuit board 20 and the frame board 30 as the architecture basis. In other specific implementations, the chip stacking architecture can only be provided with the first circuit board. Please refer to Figure 7 , which is a schematic diagram of another chip stacking architecture of an electronic device provided in the embodiments of the present application. In order to clearly show the difference and connection between the present embodiment and the foregoing Figure 1 described scheme, the same functions and structures are schematically shown by the same reference signs in the figure.

[0065] Compared with Figure 1 the chip stacking architecture described in the foregoing embodiments, the difference of the present embodiment is that the chip stacking architecture 100 takes the first circuit board 10 as the architecture basis. In a specific implementation, when the chip stacking architecture 100 is applied to an electronic device with data transmission and communication functions, the radio frequency components (not shown in the figure) can be arranged on the first circuit board 10. Similarly, the connector 8 for adapting to the battery side can also be arranged on the first circuit board 10.

[0066] The specific implementation of other functional components can adopt the implementation manner consistent with the foregoing embodiments. Here, no longer be described in detail.

[0067] Compared withFigure 1 The chip stacking architecture described can be used in electronic devices such as mobile phones, which have limited planar arrangement space, Figure 2 The chip stacking architecture described can be used in electronic devices such as tablets, which have unlimited planar arrangement space.

[0068] The chip stacking architecture described in the foregoing embodiments can be widely applied to different application scenarios. For example, electronic devices such as mobile phones, tablets, or computers. In specific implementation, the chip stacking architecture can be mounted on the shell of the electronic device, or can also be mounted on the middle frame of the electronic device. The specific implementation can be determined according to the overall design requirements of the product, and the embodiments of the present application are not limited.

[0069] It should be understood that other main functions of the electronic device can be implemented by using existing technologies, and therefore, the present application will not be described herein.

[0070] The above is only a preferred embodiment of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A chip stack architecture, comprising: The chip stacking architecture comprises a first circuit board, a chip, a memory and a first capacitor; the first circuit board comprises a first surface and a second surface arranged oppositely, the chip is connected to the first surface, the second surface has a recess, the first capacitor is arranged in the recess and connected to the chip through the first circuit board, the memory covers the recess and is connected to the part of the second surface located outside the periphery of the recess, and the memory is electrically connected to the chip.

2. The chip stack architecture of claim 1, wherein, The chip stacking architecture further comprises a second capacitor, the chip comprises a packaging substrate, and the second capacitor is arranged on the packaging substrate; the first capacitor and the second capacitor are used to build a power distribution network.

3. The chip stack architecture of claim 1 or 2, wherein, The chip stacking architecture further comprises a third capacitor used to build the power distribution network, the third capacitor is arranged outside the recess and between the second surface and the memory.

4. The chip stack architecture of claim 1, wherein, The bottom edge of the recess is provided with a copper skin.

5. The chip stack architecture of claim 4, wherein, The bottom of the recess is covered with a PI film layer.

6. The chip stack architecture of claim 2, wherein, The signal wiring between the chip and the memory is arranged in the wiring layer close to the first surface.

7. The chip stack architecture of claim 6, wherein, The signal fan-out wiring of the chip is arranged in the wiring layer close to the first surface or the wiring layer close to the second surface.

8. The chip stack architecture of claim 6 or 7, wherein, The wiring of the power distribution network is arranged in the middle wiring layer of the first circuit board.

9. The chip stack architecture of claim 1, wherein, The chip comprises a core particle and a packaging substrate, the core particle and the packaging substrate are arranged in a stack, and the surface of the core particle opposite to the packaging substrate is not covered with packaging material.

10. The chip stack architecture of claim 1 or 9, wherein, The chip is attached to a vapor chamber through a thermally conductive interface material.

11. The chip stack architecture of claim 1 or 9, wherein, An on-chip fan is arranged on the chip.

12. The chip stack architecture of claim 1, wherein, The chip stacking architecture further comprises a second circuit board, the second circuit board is connected to the first circuit board through a frame board, a containing space is formed between the first circuit board, the second circuit board and the frame board, and the memory is located in the containing space. The chip stacking architecture further comprises a power management unit, the power management unit is connected to the second surface and located in the containing space.

13. An electronic device, comprising: The chip stacking architecture comprises a housing, a middle frame and the chip stacking architecture according to any one of claims 1 to 12, the chip stacking architecture is mounted on the housing, or the chip stacking architecture is mounted on the middle frame.

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