PLC (Programmable Logic Controller) power-down retaining circuit
By using a switching power supply chip and a supercapacitor bank in the PLC power-off retention circuit design, the problems of high cost and insufficient stability of long-term data storage after PLC power failure are solved, achieving low-cost and stable data storage and protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUXI XINJIE ELECTRICAL
- Filing Date
- 2025-03-27
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, PLC power-off retention circuits are costly and lack stability when storing data for extended periods, especially when using large-capacity capacitors, which can lead to difficulties in power-on or unstable operation.
The circuit design combines a switching power supply chip and a supercapacitor bank. Through charging circuit, discharging circuit and voltage monitoring circuit, it ensures that the supercapacitor bank protects against power abnormalities and continues to supply power after power failure, thereby realizing data storage.
It achieves low-cost, stable, and reliable long-term data storage, avoids problems such as difficulty in power-on and unstable operation, and has overvoltage protection and multi-channel monitoring functions.
Smart Images
Figure CN224138736U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of PLC circuit protection technology, and in particular to a PLC power-off retention circuit. Background Technology
[0002] A PLC (Programmable Logic Controller) is a digital electronic system specifically designed for industrial applications. It uses a programmable memory to store instructions for performing logical operations, sequential control, timing, counting, and arithmetic operations, controlling various types of machinery or production processes through digital or analog inputs and outputs.
[0003] When using a PLC, it's often necessary to configure internal data to suit specific application needs. Furthermore, it's required that this data be retained after the system is powered off, so that it can be read and used upon the next power-on. Therefore, many PLCs are designed with a power-off retention function to save specific data after a power outage.
[0004] As users demand increasingly higher data utilization, PLCs are often required to store large amounts of real-time data during power outages. This places higher demands on power-off retention circuits, requiring them to retain more data for a longer period after a system power failure. Several methods exist to achieve this, such as adding batteries and charging circuits, but these are relatively expensive. Lower-cost methods exist, such as adding large-capacity aluminum electrolytic capacitors to the power supply. In applications requiring long power-off retention times, capacitors with capacities of 10000uF or higher are often needed. This necessitates a power supply with sufficiently high capacitive load capacity; otherwise, problems such as difficulty starting the power supply or unstable operation may occur.
[0005] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Utility Model Content
[0006] The purpose of this utility model is to overcome the problems of the prior art and provide a PLC power-off retention circuit to solve the problems of high cost of adding batteries and charging circuits to maintain long-term storage in the prior art, and the addition of large-capacity aluminum electrolytic capacitors at the power supply end. In some cases where the power-off retention time is required to be long, capacitors with a capacity of 10000uF or even higher are often required. The capacitive load capacity of the power supply is required to be large enough, otherwise it will cause technical problems such as difficulty in power-on or unstable operation.
[0007] The above objectives are achieved through the following technical solutions:
[0008] A PLC power-down retention circuit includes a power input port, a power supply circuit, a charging circuit, a discharging circuit, and a system power supply connected in sequence. The charging circuit is also connected to a charging voltage monitoring circuit, a supercapacitor bank, and a capacitor voltage monitoring circuit. The power supply circuit includes a first diode connected to the power input port, the cathode of the first diode being connected in series with a first energy storage capacitor and a switching power supply chip. The switching power supply chip is connected to the charging circuit and the system power supply.
[0009] Furthermore, the switching power supply chip is model SCT2632STER.
[0010] Furthermore, the charging circuit includes a first PNP transistor and a second PMOS transistor. The base of the first PNP transistor is connected to a second resistor, and the other end of the second resistor is connected to the first resistor and the cathode of a Zener diode. The emitter of the first PNP transistor is connected to the cathode of a third reverse polarity protection diode, the third resistor, the second capacitor, and the source of the second PMOS transistor. The anode of the third reverse polarity protection diode and the first resistor are respectively connected to the switching power supply chip. The collector of the first PNP transistor is connected to the third resistor, the second capacitor, the fourth resistor, the gate of the second PMOS transistor, and the charging voltage monitoring circuit. The drain of the second PMOS transistor is connected to a fuse, the other end of the fuse is connected to an NTC thermistor, and the other end of the NTC thermistor is connected to the supercapacitor bank.
[0011] Furthermore, the charging voltage monitoring circuit includes a third PNP transistor. The collector of the third PNP transistor is connected to the first I / O port of the MCU chip and a sixth resistor. The other end of the sixth resistor is connected to the MCU power supply. The base of the third PNP transistor is connected to a fifth resistor. The other end of the fifth resistor is connected to the gate of the second PMOS transistor. The emitter of the third PNP transistor is connected to signal ground.
[0012] Furthermore, the supercapacitor bank includes a third supercapacitor, a fourth supercapacitor, and a fifth supercapacitor that are smoothly connected. The positive terminal of the third supercapacitor is connected to the NTC thermistor. The two ends of the third supercapacitor are connected in parallel with an eighth resistor, the two ends of the fourth supercapacitor are connected in parallel with a ninth resistor, and the two ends of the fifth supercapacitor are connected in parallel with a tenth resistor, and are connected to signal ground.
[0013] Furthermore, the capacitor voltage monitoring circuit includes a fourth PNP transistor and a fifth PNP transistor. The base of the fourth PNP transistor is connected to an eleventh resistor and a twelfth resistor. The other end of the eleventh resistor and the emitter of the fourth PNP transistor are connected to the NTC thermistor. The collector of the fourth PNP transistor is connected to a thirteenth resistor and a fourteenth resistor. The other end of the thirteenth resistor is connected to the base of the fifth PNP transistor. The other end of the fourteenth resistor is connected to the emitter of the fifth PNP transistor and is connected to signal ground. The collector of the fifth PNP transistor is connected to the second I / O port of the MCU chip and a fifteenth resistor. The other end of the fifteenth resistor is connected to the MCU power supply.
[0014] Furthermore, the discharge circuit includes a sixth PMOS transistor, the gate of which is connected to a sixth capacitor, a sixteenth resistor, and the anode of a fourth diode, and the cathode of the fourth diode is connected to the third I / O port of the MCU chip; the drain of the fifth PNP transistor is connected to the anode of the fifth transistor, and the cathode of the fifth transistor is connected to the system power supply; the source of the fifth PNP transistor, the sixth capacitor, and the sixteenth resistor are also connected to the emitter of the fourth PNP transistor.
[0015] This utility model provides a PLC power-down retention circuit that uses a switching power supply chip U1 to transform the input power voltage. The transformed voltage supplies power to the system power supply Vsys and the charging circuit. When the power input port is powered, the DC 5V, stepped down by the switching power supply chip U1, can charge the supercapacitor bank through the charging circuit. The capacitor voltage monitoring circuit detects the voltage of the supercapacitor bank. When the voltage of the supercapacitor bank exceeds a threshold, external power is cut off, and the supercapacitor bank supplies power to the system power supply Vsys through a discharge circuit, thus ensuring the completion of data storage operation after power failure. When the DC 5V voltage rises abnormally, the charging voltage monitoring circuit will cut off the charging circuit to protect the supercapacitor bank. This PLC power-down retention circuit has the following advantages:
[0016] 1. Low cost and fully domestically produced: The components used in the circuit are discrete components such as resistors, capacitors, and transistors, which are low cost and can be designed using fully domestically produced components. At the same time, the parameters are adjustable, which is more flexible.
[0017] 2. Multi-channel monitoring, stable and reliable: To ensure safety during the supercapacitor charging process, the circuit design includes overvoltage protection, overcurrent protection, and a soft-start circuit. Overvoltage protection will cut off the charging circuit and feed back to the MCU. Simultaneously, to ensure sufficient time for data preservation after power failure, the supercapacitor voltage is continuously monitored and fed back to the MCU. The MCU will only save the data if power is cut off after the voltage exceeds a threshold. Attached Figure Description
[0018] Figure 1 This is a frame diagram of a PLC power-off retention circuit according to the present invention;
[0019] Figure 2 This is a circuit diagram of a PLC power-off retention circuit according to the present invention. Detailed Implementation
[0020] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0021] like Figure 1 As shown, this solution provides a PLC power-off retention circuit, including a power input port Vin, a power supply circuit, a charging circuit, a discharging circuit and a system power supply Vsys connected in sequence. The charging circuit is also connected to a charging voltage monitoring circuit, a supercapacitor bank and a capacitor voltage monitoring circuit.
[0022] The power supply circuit includes a first diode D1 connected to the power input port Vin, the cathode of the first diode D1 being connected in series with a first energy storage capacitor C1 and a switching power supply chip U1; the switching power supply chip U1 is connected to the charging circuit and the system power supply Vsys.
[0023] When the discharge circuit is turned on, the supercapacitor bank discharges to the power supply circuit, forming a loop.
[0024] Working principle:
[0025] In this embodiment, the power input port Vin is the power input port of the PLC system. The rated input voltage is DC24V. A first diode D1 is used to realize the reverse connection protection of the input voltage, and a first energy storage capacitor C1 is used as the input energy storage.
[0026] The switching power supply chip U1 is used to perform voltage conversion on the input power supply. It can step down the DC24V input power supply commonly used in PLC systems to DC5V, which supplies power to the system power supply Vsys and the charging circuit.
[0027] When the power input port Vin is powered, the DC5V after being stepped down by the switching power supply chip U1 can charge the supercapacitor bank through the charging circuit. The capacitor voltage monitoring circuit is used to detect the voltage of the supercapacitor bank. When the voltage of the supercapacitor bank exceeds the threshold, the external power is cut off.
[0028] When the power input port Vin is de-energized, the supercapacitor bank supplies power to the system power supply Vsys through the discharge circuit, thereby ensuring the completion of the data storage function after power failure.
[0029] When the DC5V voltage rises abnormally, the charging voltage monitoring circuit will cut off the charging circuit to protect the supercapacitor bank.
[0030] It should be noted that the switching power supply chip U1 mentioned in this embodiment is a switching power supply chip from Chipsys Technology Co., Ltd., model SCT2632STER, which is used to step down the received voltage to DC5V, and this DC5V supplies power to the system power supply Vsys and the charging circuit.
[0031] like Figure 2 As shown, the charging circuit in this embodiment includes a first PNP transistor Q1 and a second PMOS transistor Q2. The base of the first PNP transistor Q1 is connected to a second resistor R2, and the other end of the second resistor R2 is connected to the first resistor R1 and the cathode of the Zener diode D2. The emitter of the first PNP transistor Q1 is connected to the cathode of a third reverse polarity protection diode D3, a third resistor R3, a second capacitor C2, and the source of the second PMOS transistor Q2. The anode of the third reverse polarity protection diode D3 and the first resistor R1 are respectively connected to the switching power supply chip U1. The collector of the first PNP transistor Q1 is connected to the third resistor R3, the second capacitor C2, a fourth resistor R4, the gate of the second PMOS transistor Q2, and the charging voltage monitoring circuit.
[0032] The drain of the second PMOS transistor Q2 is connected to fuse FU1, the other end of which is connected to NTC thermistor R7, and the other end of which is connected to the supercapacitor bank. The NTC thermistor R7 is an NTC10D-11 from Fenghua Technology Co., Ltd.; the fuse FU1 is an SMD0805-075-12V from Luhai Technology Co., Ltd.; the second PMOS transistor Q2 and the sixth PMOS transistor Q6 are NCE40P05Y from Wuxi Xinjieneng Technology Co., Ltd.; the first transistor Q1 and the fourth transistor Q4 are MMBT5401 from Jiangsu Changjing Technology Co., Ltd.; and the third transistor Q3 and the fifth transistor Q5 are MMBT5551 from Jiangsu Changjing Technology Co., Ltd.
[0033] like Figure 2 As shown, the charging voltage monitoring circuit in this embodiment includes a third PNP transistor Q3. The collector of the third PNP transistor Q3 is connected to the first IO port 0V-5V of the MCU chip and the sixth resistor R6. The other end of the sixth resistor R6 is connected to the MCU power supply Vmcu.
[0034] The base of the third PNP transistor Q3 is connected to the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the gate of the second PMOS transistor Q2.
[0035] The emitter of the third PNP transistor Q3 is connected to signal ground.
[0036] like Figure 2 As shown, in this embodiment, the supercapacitor bank includes a third supercapacitor C3, a fourth supercapacitor C4, and a fifth supercapacitor C5 that are connected in a smooth manner. The positive terminal of the third supercapacitor C3 is connected to the NTC thermistor R7. The two ends of the third supercapacitor C3 are connected in parallel with the eighth resistor R8. The two ends of the fourth supercapacitor C4 are connected in parallel with the ninth resistor R9. The two ends of the fifth supercapacitor C5 are connected in parallel with the tenth resistor R10 and connected to signal ground.
[0037] like Figure 2 As shown, the capacitor voltage monitoring circuit in this embodiment includes a fourth PNP transistor Q4 and a fifth PNP transistor Q5. The base of the fourth PNP transistor Q4 is connected to the eleventh resistor R11 and the twelfth resistor R12. The other end of the eleventh resistor R11 and the emitter of the fourth PNP transistor Q4 are connected to the NTC thermistor R7. The collector of the fourth PNP transistor Q4 is connected to the thirteenth resistor R13 and the fourteenth resistor R14. The other end of the thirteenth resistor R13 is connected to the base of the fifth PNP transistor Q5, and the other end of the fourteenth resistor R14 is connected to the emitter of the fifth PNP transistor Q5 and connected to signal ground.
[0038] The collector of the fifth PNP transistor Q5 is connected to the second IO port SC-RDY of the MCU chip and the fifteenth resistor R15. The other end of the fifteenth resistor R15 is connected to the MCU power supply Vmcu.
[0039] like Figure 2 As shown, the discharge circuit in this embodiment includes a sixth PMOS transistor Q6. The gate of the sixth PMOS transistor Q6 is connected to the sixth capacitor C6, the sixteenth resistor R16, and the anode of the fourth diode D4. The cathode of the fourth diode D4 is connected to the third IO port Ctrl of the MCU chip.
[0040] The drain of the fifth PNP transistor Q5 is connected to the anode of the fifth transistor D5, and the cathode of the fifth transistor D5 is connected to the system power supply Vsys; the source of the fifth PNP transistor Q5, the sixth capacitor C6, and the sixteenth resistor R16 are also connected to the emitter of the fourth PNP transistor Q4.
[0041] Workflow:
[0042] When DC5V starts charging the supercapacitor bank, NTC thermistor R7 suppresses instantaneous peak current, fuse FU1 prevents excessive charging current, and capacitor C2 reduces the turn-on speed of the second PMOS transistor Q2, achieving soft start. The voltage divider circuit composed of resistor R3 and resistor R4 ensures that the second PMOS transistor Q2 is in the conducting state. At this time, the third NPN transistor Q3 is not conducting, and the first IO port OV-5V of the MCU is at a high level. When the DC5V voltage rises abnormally, Zener diode D2 is in the Zener breakdown state, the first PNP transistor Q1 is conducting, and the second PMOS transistor Q2 is turning off. DC5V stops charging the supercapacitor bank, playing an overvoltage protection role. At this time, the NPN transistor is conducting, the first IO port OV-5V of the MCU is at a low level, and the PLC system issues a warning.
[0043] During the charging process, the voltage across the supercapacitor bank continuously increases. Once it reaches the threshold set by the eleventh resistor R11 and the twelfth resistor R12, the fourth PNP transistor Q4 turns on, the fifth NPN transistor Q5 turns on, and the second IO port SC-RDY of the MCU is at a low level, notifying the PLC that the supercapacitor bank is fully charged.
[0044] When power is lost, the PLC can save data. If the supercapacitor bank is not fully charged, data will not be saved when power is lost. The MCU's third IO port Ctrl controls the switch of the sixth PMOS transistor Q6. When Ctrl is pulled low, the sixth PMOS transistor Q6 is turned on, and the supercapacitor bank supplies power to the system through the sixth PMOS transistor Q6, ensuring that the data storage function is completed after power failure.
[0045] The above description is only for illustrating the embodiments of this utility model and is not intended to limit this utility model. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A PLC power-down retention circuit, characterized in that, It includes a power input port (Vin), a power supply circuit, a charging circuit, a discharging circuit, and a system power supply (Vsys) connected in sequence. The charging circuit is also connected to a charging voltage monitoring circuit, a supercapacitor bank, and a capacitor voltage monitoring circuit. The power supply circuit includes a first diode (D1) connected to the power input port (Vin), the cathode of the first diode (D1) being connected in series with a first energy storage capacitor (C1) and a switching power supply chip (U1); the switching power supply chip (U1) is connected to the charging circuit and the system power supply (Vsys).
2. The PLC power fail hold circuit of claim 1, wherein, The switching power supply chip (U1) is model SCT2632STER.
3. The PLC power fail hold circuit according to claim 1 or 2, wherein, The charging circuit includes a first PNP transistor (Q1) and a second PMOS transistor (Q2). The base of the first PNP transistor (Q1) is connected to a second resistor (R2), and the other end of the second resistor (R2) is connected to the first resistor (R1) and the cathode of a Zener diode (D2). The emitter of the first PNP transistor (Q1) is connected to the cathode of a third reverse polarity protection diode (D3), the third resistor (R3), the second capacitor (C2), and the source of the second PMOS transistor (Q2). The anode of the third reverse polarity protection diode (D3) and the first resistor (R1) are respectively connected to the switching power supply chip (U1). The collector of the first PNP transistor (Q1) is connected to the third resistor (R3), the second capacitor (C2), the fourth resistor (R4), the gate of the second PMOS transistor (Q2), and the charging voltage monitoring circuit. The drain of the second PMOS transistor (Q2) is connected to a fuse (FU1), the other end of which is connected to an NTC thermistor (R7), and the other end of which is connected to the supercapacitor bank.
4. The PLC power fail hold circuit of claim 3, wherein, The charging voltage monitoring circuit includes a third PNP transistor (Q3), the collector of which is connected to the first IO port (0V-5V) of the MCU chip and the sixth resistor (R6), and the other end of the sixth resistor (R6) is connected to the MCU power supply (Vmcu). The base of the third PNP transistor (Q3) is connected to the fifth resistor (R5), and the other end of the fifth resistor (R5) is connected to the gate of the second PMOS transistor (Q2). The emitter of the third PNP transistor (Q3) is connected to signal ground.
5. The PLC power fail holdup circuit of claim 3 or 4, wherein, The supercapacitor bank includes a third supercapacitor (C3), a fourth supercapacitor (C4), and a fifth supercapacitor (C5) that are connected in a straight line. The positive terminal of the third supercapacitor (C3) is connected to the NTC thermistor (R7). The two ends of the third supercapacitor (C3) are connected in parallel with the eighth resistor (R8), the two ends of the fourth supercapacitor (C4) are connected in parallel with the ninth resistor (R9), and the two ends of the fifth supercapacitor (C5) are connected in parallel with the tenth resistor (R10), and are connected to signal ground.
6. The PLC power fail holdup circuit of claim 4, wherein, The capacitor voltage monitoring circuit includes a fourth PNP transistor (Q4) and a fifth PNP transistor (Q5). The base of the fourth PNP transistor (Q4) is connected to the eleventh resistor (R11) and the twelfth resistor (R12). The other end of the eleventh resistor (R11) and the emitter of the fourth PNP transistor (Q4) are connected to the NTC thermistor (R7). The collector of the fourth PNP transistor (Q4) is connected to the thirteenth resistor (R13) and the fourteenth resistor (R14). The other end of the thirteenth resistor (R13) is connected to the base of the fifth PNP transistor (Q5), and the other end of the fourteenth resistor (R14) is connected to the emitter of the fifth PNP transistor (Q5) and connected to signal ground. The collector of the fifth PNP transistor (Q5) is connected to the second IO port (SC-RDY) of the MCU chip and the fifteenth resistor (R15), and the other end of the fifteenth resistor (R15) is connected to the MCU power supply (Vmcu).
7. The PLC power fail holdup circuit of claim 6, wherein, The discharge circuit includes a sixth PMOS transistor (Q6), the gate of which is connected to the sixth capacitor (C6), the sixteenth resistor (R16), and the anode of the fourth diode (D4), and the cathode of the fourth diode (D4) is connected to the third IO port (Ctrl) of the MCU chip. The drain of the fifth PNP transistor (Q5) is connected to the anode of the fifth transistor (D5), and the cathode of the fifth transistor (D5) is connected to the system power supply (Vsys). The source of the fifth PNP transistor (Q5), the sixth capacitor (C6), and the sixteenth resistor (R16) are also connected to the emitter of the fourth PNP transistor (Q4).