DC-DC non-isolated step-down circuit based on integrated inductor step-down chip
By using a DC-DC non-isolated buck circuit based on an integrated inductor buck chip, multiple main control chips and voltage divider circuits are used to achieve multiple outputs, solving the problem of low efficiency of multiple outputs in existing technologies and realizing a high-efficiency, low-power power supply solution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN ZHENHUA MICROELECTRONICS
- Filing Date
- 2025-07-02
- Publication Date
- 2026-04-17
AI Technical Summary
The lack of non-isolated DC-DC buck solutions for multi-output in existing technologies results in low efficiency of power modules and difficulty in meeting the requirements of multi-output.
A non-isolated DC-DC step-down circuit based on an integrated inductor step-down chip is adopted. Non-isolated DC-DC step-down processing is performed through multiple independent main control chips, and the control and filtering of multiple output voltages are realized by using voltage divider circuits and feedback circuits. Voltage regulation and filtering are combined with bootstrap capacitors and output capacitors.
It achieves efficient multi-output with a step-down efficiency of over 89%. The power supply is small in size, simple in structure, has few components, low power consumption, and low output ripple voltage, meeting the needs of actual production.
Smart Images
Figure CN224138897U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit technology, specifically to a DC-DC non-isolated step-down circuit based on an integrated inductor step-down chip. Background Technology
[0002] Currently, power application plays a crucial role in various electronic devices and systems. Through reasonable power application, stable operation of equipment, performance improvement, and effective energy conservation can be achieved.
[0003] As the power requirements of communication equipment power modules become increasingly demanding, power applications can be improved by increasing the switching frequency of the switching transistors in the switching power supply. However, higher switching frequencies indicate greater converter losses and lower power module efficiency. To ensure the stability and reliability of the power module, a DC-DC converter is used. A DC-DC converter is a device that converts DC power from one voltage level to another. These converters play a crucial role in electronic devices and systems, enabling stable operation of devices with varying voltage requirements through their efficient voltage conversion capabilities.
[0004] To reduce the size of power modules, non-isolated DC-DC converters are often used as the last stage of the board-level power supply in communication equipment, resulting in a very compact set of peripheral components. However, when customers require multiple outputs, there is currently a lack of non-isolated DC-DC buck solutions.
[0005] Therefore, how to provide a non-isolated DC-DC step-down solution for multiple outputs is an important issue that urgently needs to be addressed in the industry. Utility Model Content
[0006] In view of this, the present invention provides a non-isolated DC-DC buck circuit based on an integrated inductor buck chip, thereby solving the problem of the lack of non-isolated DC-DC buck solutions when multiple outputs are required in the prior art.
[0007] According to a first aspect, embodiments of the present invention provide a DC-DC non-isolated buck circuit based on an integrated inductor buck chip, comprising:
[0008] Multiple independent master control chips are used. The input pins of each master control chip are connected to the input voltage signal and perform non-isolated DC-DC step-down processing on the input voltage signal to obtain their respective output voltage signals. The EN pin of the master control chip that outputs the highest output voltage signal is connected to the output pin of another master control chip.
[0009] Each main control chip has an input capacitor between the input voltage signal and the input pin. One end of the input capacitor is connected between the input voltage signal of the main control chip and the input pin, and the other end of the input capacitor is grounded.
[0010] Each main control chip has its corresponding voltage divider circuit. The voltage divider circuit includes a first voltage divider resistor connected between the feedback pin and the output pin of the main control chip and a second voltage divider resistor connected between the feedback pin of the main control chip and ground. The first voltage divider resistor and the second voltage divider resistor are connected to each other.
[0011] Each main control chip has its corresponding feedback circuit, which includes a first feedback capacitor connected between the feedback pin and the output pin of the main control chip. The first feedback capacitor is connected in parallel with the first voltage divider resistor of the corresponding main control chip.
[0012] A voltage adjustment pin is connected between the first voltage divider circuit and the second voltage divider resistor of the main control chip, which is not used to output the highest output voltage signal.
[0013] Each main control chip has several output capacitors connected in parallel between its output pin and ground.
[0014] In conjunction with the first aspect, in the first embodiment of the first aspect, the main control chip includes a first main control chip U1, a second main control chip U2 and a third main control chip U3, and the second main control chip U2 and the third main control chip U3 are chips of the same model.
[0015] The first main control chip U1 is used to output the first output voltage signal, the second main control chip U2 is used to output the second output voltage signal, and the third main control chip U3 is used to output the third output voltage signal, and the voltage corresponding to the first output voltage signal is the highest value among all channels.
[0016] In conjunction with the first embodiment of the first aspect, in the second embodiment of the first aspect, a first capacitor C1 is provided between the input voltage signal of the first main control chip U1 and the input pin. One end of the first capacitor C1 is connected between the input voltage signal of the first main control chip U1 and the input pin, and the other end of the first capacitor C1 is grounded.
[0017] A fifteenth capacitor C15 is provided between the input voltage signal of the second main control chip U2 and the input pin. One end of the fifteenth capacitor C15 is connected between the input voltage signal of the second main control chip U2 and the input pin, and the other end of the fifteenth capacitor C15 is grounded.
[0018] A twentieth capacitor C20 is provided between the input voltage signal and the input pin of the third main control chip U3. One end of the twentieth capacitor C20 is connected between the input voltage signal and the input pin of the third main control chip U3, and the other end of the twentieth capacitor C20 is grounded.
[0019] In conjunction with the first embodiment of the first aspect, in the third embodiment of the first aspect, the voltage divider resistor of the first main control chip U1 includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the feedback pin and the output pin of the first main control chip U1, and the second resistor R2 is connected between the feedback pin and ground of the first main control chip U1. The first resistor R1 and the second resistor R2 are connected.
[0020] The voltage divider resistors of the second main control chip U2 include a third resistor R3 and a fourth resistor R4. The third resistor R3 is connected between the feedback pin and the output pin of the second main control chip U2, and the fourth resistor R4 is connected between the feedback pin and ground of the second main control chip U2. The third resistor R3 and the fourth resistor R4 are connected together.
[0021] The voltage divider resistors of the third main control chip U3 include a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is connected between the feedback pin and the output pin of the third main control chip U3, and the sixth resistor R6 is connected between the feedback pin and ground of the third main control chip U3. The fifth resistor R5 and the sixth resistor R6 are connected together.
[0022] In conjunction with the third embodiment of the first aspect, in the fourth embodiment of the first aspect, a second capacitor C2 is provided between the feedback pin and the output pin of the first main control chip U1, and the second capacitor C2 is connected in parallel with the first resistor R1.
[0023] The second main control chip U2 has a fifth capacitor C5 between its feedback pin and output pin, and the fifth capacitor C5 is connected in parallel with the third resistor R3.
[0024] The third main control chip U3 has a seventh capacitor C7 between its feedback pin and output pin, and the seventh capacitor C7 is connected in parallel with the fifth resistor R5.
[0025] In conjunction with the third embodiment of the first aspect, in the fifth embodiment of the first aspect, a voltage adjustment pin is led out between the third resistor R3 and the fourth resistor R4, and a voltage adjustment pin is led out between the fifth resistor R5 and the sixth resistor R6.
[0026] In conjunction with the first embodiment of the first aspect, in the sixth embodiment of the first aspect, a third capacitor C3 and a fourth capacitor C4 are provided between the output pin of the first main control chip U1 and ground, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel.
[0027] The output pin of the second main control chip U2 is connected to ground by a sixth capacitor C6 and a sixteenth capacitor C16, which are connected in parallel.
[0028] The third main control chip U3 has an eighth capacitor C8 and a seventeenth capacitor C17 connected in parallel between its output pin and ground.
[0029] In conjunction with the first embodiment of the first aspect, in the seventh embodiment of the first aspect, a bootstrap capacitor is provided in the peripheral circuit of the first main control chip U1, and the bootstrap capacitor is connected between the BS pin and the LX pin of the first main control chip U1.
[0030] In conjunction with the first embodiment of the first aspect, in the eighth embodiment of the first aspect, the LX pin of the main control chip is connected to the power inductor and the switching transistor inside the main control chip, and each main control chip has two LX pins, and the LX pins in the same main control chip are shorted and connected in parallel.
[0031] In conjunction with the first embodiment of the first aspect, in the ninth embodiment of the first aspect, the SS pin of the first main control chip U1 is externally connected to the twenty-first capacitor C21 and ground.
[0032] This invention relates to a DC-DC non-isolated buck circuit based on an integrated inductor buck chip. The design achieves a buck efficiency of over 89%, meeting the requirements for multiple outputs, high efficiency conversion, and small power supply size. By setting voltage divider circuits (i.e., voltage divider resistors) in each main control chip, the voltage magnitude in the output voltage signal is controlled, meeting actual production requirements. The circuit has a simple structure, is easy to debug, requires few components, occupies little space, has low power consumption, and low output ripple voltage. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] in:
[0035] Figure 1 The diagram shows a schematic of a non-isolated DC-DC step-down circuit based on an integrated inductor step-down chip provided by this invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0037] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0038] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0039] Currently, power application plays a crucial role in various electronic devices and systems. Through reasonable power application, stable operation of equipment, performance improvement, and effective energy conservation can be achieved.
[0040] As the power requirements of communication equipment power modules become increasingly demanding, power applications can be improved by increasing the switching frequency of the switching transistors in the switching power supply. However, higher switching frequencies indicate greater converter losses and lower power module efficiency. To ensure the stability and reliability of the power module, a DC-DC converter is used. A DC-DC converter is a device that converts DC power from one voltage level to another. These converters play a crucial role in electronic devices and systems, enabling stable operation of devices with varying voltage requirements through their efficient voltage conversion capabilities.
[0041] To reduce the size of power modules, non-isolated DC-DC converters are often used as the last stage of the board-level power supply in communication equipment, resulting in a very compact set of peripheral components. However, when customers require multiple outputs, there is currently a lack of non-isolated DC-DC buck solutions.
[0042] Therefore, how to provide a non-isolated DC-DC step-down solution for multiple outputs is an important issue that urgently needs to be addressed in the industry.
[0043] To address the aforementioned problems, this specification provides a non-isolated DC-DC buck converter circuit based on an integrated inductor buck chip. For example... Figure 1 As shown, the circuit includes:
[0044] Multiple independent master control chips are used. Each master control chip is connected to the input voltage signal and performs non-isolated DC-DC step-down processing on the input voltage signal to obtain its own output voltage signal.
[0045] Assuming the input voltage signal range is 4.5-5.5V, and the user requires three output voltage signals, namely 3.3V / 3A, 1.5V / 2A, and 1.2V / 0.6A respectively, then three main control chips will be used: the first main control chip U1, the second main control chip U2, and the third main control chip U3. The input pin (IN pin) of each main control chip will be connected to the input voltage, and corresponding non-isolated DC-DC step-down processing will be performed. Multiple outputs will be achieved through independent control channels inside the chip, resulting in the output voltage signal of each individual channel.
[0046] Each main control chip has an input capacitor between the input voltage signal and the input pin (IN pin). The input capacitors (first capacitor C1, fifteenth capacitor C15, and twentieth capacitor C20) are connected to the input voltage signal of their respective main control chip. Between the input pin and the input pin (IN pin), a filtering network is formed. The input capacitors filter the input voltage signals of their respective main control chips to remove high-frequency noise and instantaneous fluctuations in the input power supply.
[0047] Specifically, one end of the first capacitor C1 is connected between the input voltage signal and the input pin of the first main control chip U1, and the other end of the first capacitor C1 is grounded. One end of the fifteenth capacitor C15 is connected between the input voltage signal and the input pin of the second main control chip U2, and the other end of the fifteenth capacitor C15 is grounded. One end of the twentieth capacitor C20 is connected between the input voltage signal and the input pin of the third main control chip U3, and the other end of the twentieth capacitor C20 is grounded.
[0048] The first main control chip U1 is used to output the first output voltage signal, the second main control chip U2 is used to output the second output voltage signal, and the third main control chip U3 is used to output the third output voltage signal. The voltage corresponding to the first output voltage signal is the highest value among all channels, namely 3.3V / 3A as mentioned above. Simultaneously, the EN pin of the main control chip used to output the highest output voltage signal is connected to the output pin of another main control chip; that is, the EN pin of the first main control chip U1 is connected to the output pin of the second main control chip U2.
[0049] In this embodiment, the second main control chip U2 and the third main control chip U3 can be the same model of chip according to actual needs.
[0050] Thus, these three channels are based on high-efficiency synchronous rectification buck power supply chips with two types of integrated inductors. Both types of chips use ultra-small packages, and the peripheral circuits of the three main control chips are simple in structure, have few components, and are easy to debug.
[0051] Understandably, depending on the number of output channels required by the user in actual application, when the number of output channels exceeds three, each of the excess channels can be connected to these channels using the third main control chip U3 and its corresponding peripheral circuits to convert the input voltage signal into the required output voltage signal.
[0052] In this embodiment, each main control chip has its corresponding voltage divider circuit. The voltage divider circuit includes a first voltage divider resistor connected between the feedback pin (FB pin) and the output pin (OUT pin) of the main control chip, and a second voltage divider resistor connected between the feedback pin (FB pin) of the main control chip and ground. The first voltage divider resistor and the second voltage divider resistor are connected to each other.
[0053] The first resistor R1 is connected between the feedback pin (FB pin) and the output pin (OUT pin) of the first main control chip U1, and the second resistor R2 is connected between the feedback pin (FB pin) of the first main control chip U1 and ground. The first resistor R1 and the second resistor R2 are connected together, and the first resistor R1 and the second resistor R2 constitute the voltage divider resistor of the first main control chip U1 and are used to adjust the magnitude of the output voltage of the first main control chip U1.
[0054] The voltage divider circuits of the second and third main control chips U2 and U3 are similar in structure to those of the first main control chip U1. Specifically, the third resistor R3 is connected between the feedback pin (FB pin) and the output pin (OUT pin) of the second main control chip U2; the fourth resistor R4 is connected between the feedback pin (FB pin) and ground of the second main control chip U2, and the third resistor R3 is connected to the fourth resistor R4; the fifth resistor R5 is connected between the feedback pin (FB pin) and the output pin (OUT pin) of the third main control chip U3; and the sixth resistor R6 is connected between the feedback pin (FB pin) and ground of the third main control chip U3, and the fifth resistor R5 is connected to the sixth resistor R6. The working principle of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 is the same as that of the first resistor R1 and the second resistor R2, all for adjusting the output voltage of the corresponding main control chip.
[0055] Output voltage The formula for calculating the numerical value is:
[0056]
[0057] in, This indicates the voltage value of the feedback pin (FB pin); This indicates the resistance value of the resistor (e.g., first resistor R1, third resistor R3, fifth resistor R5) connected between the feedback pin (FB pin) and the output pin (OUT pin) of the main control chip. This indicates the resistance value of the resistor (e.g., the second resistor R2, the fourth resistor R4, and the sixth resistor R6) connected between the feedback pin (FB pin) of the main control chip and ground.
[0058] That is, output voltage Depend on and The partial pressure is determined.
[0059] In this embodiment, each main control chip has its corresponding feedback circuit. The feedback circuit includes a first feedback capacitor connected between the feedback pin (FB pin) and the output pin (OUT pin) of the main control chip. The first feedback capacitor is connected in parallel with the first voltage divider resistor of the corresponding main control chip.
[0060] Among them, a second capacitor C2 is provided between the feedback pin (FB pin) and the output pin (OUT pin) of the first main control chip U1, and the second capacitor C2 is connected in parallel with the first resistor R1. The feedback signal is sampled and high-frequency noise is filtered out through the second capacitor C2 connected in parallel with the first resistor R1.
[0061] Similarly, the feedback circuits of the second main control chip U2 and the third main control chip U3 have similar circuit structures to those of the first main control chip U1. Specifically, a fifth capacitor C5 is provided between the feedback pin (FB pin) and the output pin (OUT pin) of the second main control chip U2, and the fifth capacitor C5 is connected in parallel with the third resistor R3. A seventh capacitor C7 is provided between the feedback pin (FB pin) and the output pin (OUT pin) of the third main control chip U3, and the seventh capacitor C7 is connected in parallel with the fifth resistor R5. The working principle of the fifth capacitor C5 and the seventh capacitor C7 is the same as that of the second capacitor C2, both of which are connected in parallel with the corresponding resistor to sample the feedback signal and filter out high-frequency noise.
[0062] In this embodiment, a voltage adjustment pin is connected between the first voltage divider circuit and the second voltage divider resistor of the main control chip (not used to output the highest output voltage signal). Specifically, a voltage adjustment pin TRIM1 is led out between the third resistor R3 and the fourth resistor R4, and a voltage adjustment pin TRIM2 is led out between the fifth resistor R5 and the sixth resistor R6. The voltage adjustment pin adjusts the voltage division ratio through an external resistor, thereby achieving fine adjustment of the output voltage (0.6V-). ).
[0063] In this embodiment, several output capacitors are provided between the output pins of the main control chip and ground, and the output capacitors are connected in parallel.
[0064] Among them, the first main control chip U1 has a third capacitor C3 and a fourth capacitor C4 between its output pin (OUT pin) and ground. The third capacitor C3 and the fourth capacitor C4 are connected in parallel, and the output capacitors filter the output voltage signal.
[0065] The output capacitors of the second main control chip U2 and the third main control chip U3 have similar circuit structures to the output capacitor of the first main control chip U1. Specifically, the output pin (OUT pin) of the second main control chip U2 is provided with a sixth capacitor C6 and a sixteenth capacitor C16 between it and ground. The sixth capacitor C6 and the sixteenth capacitor C16 are connected in parallel. The output pin (OUT pin) of the third main control chip U3 is provided with an eighth capacitor C8 and a seventeenth capacitor C17 between it and ground. The eighth capacitor C8 and the seventeenth capacitor C17 are connected in parallel.
[0066] In this embodiment, the peripheral circuit of the first main control chip U1 is provided with a bootstrap capacitor. The bootstrap capacitor (the nineteenth capacitor C19) is connected between the BS pin and the LX pin of the first main control chip U1 to provide a voltage boost for the gate drive of the high-side switching transistor and ensure reliable conduction of the components.
[0067] The mode selection pin (MODE pin) of the first main control chip U1 is set to low level. When this pin is set to low level, the first main control chip U1 operates in Pulse Frequency Modulation (PFM) mode, which is light load and high efficiency. Conversely, when this pin is set to high level or floating, the first main control chip U1 operates in Pulse Width Modulation (PWM) mode, which is fixed frequency.
[0068] In this embodiment, the LX pin of the main control chip is used as a switching node. The LX pin is connected to the power inductor and the switching transistor (integrated inside the chip). The input voltage is converted into a pulse signal through high-frequency switching, and then filtered by the inductor and the output capacitor to obtain smooth DC.
[0069] Meanwhile, all three main control chips have two LX pins. The LX pins of the same main control chip are shorted and connected in parallel, and the traces are kept away from the power loop to reduce interference.
[0070] In this embodiment, the ILMT pin of the first main control chip U1 is the valley peak current limiting setting pin, and the ILMT pin is left floating. The default valley peak current limiting is set to 6A, and overload is prevented by detecting the valley value of the inductor current. The FS pin of the first main control chip U1 is the frequency selection pin. Similarly, the FS pin is left floating, and the operating frequency is set to 500kHz.
[0071] In this embodiment, the PG pin of the first main control chip U1 is the output voltage status indicator pin, and the EN pin is the external enable control pin. The EN pin is connected to the output pin of the second main control chip U2. This connection allows the first main control chip U1 to output power after the second main control chip U2 outputs power, achieving sequential power-on. After the second main control chip is working normally, the EN pin is pulled high, and the first main control chip then starts working.
[0072] It should be noted that the EN pin can also be connected elsewhere to control the output of the first channel. When the EN pin is set to a high level, the first main control chip U1 will work.
[0073] In this embodiment, the SS pin of the first main control chip U1 is a soft-start control pin. The soft-start time can be controlled by connecting the twenty-first capacitor C21 to ground. The voltage slope during startup is controlled by the charging time to avoid surge current.
[0074] This invention relates to a DC-DC non-isolated buck circuit based on an integrated inductor buck chip. The design achieves a buck efficiency of over 89%, meeting the requirements for multiple outputs, high efficiency conversion, and small power supply size. By setting voltage divider circuits (i.e., voltage divider resistors) in each main control chip, the voltage magnitude in the output voltage signal is controlled, meeting actual production requirements. The circuit has a simple structure, is easy to debug, requires few components, occupies little space, has low power consumption, and low output ripple voltage.
[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A DC-DC non-isolated step-down circuit based on an integrated inductive step-down chip, characterized in that, include: Multiple independent master control chips are used. The input pins of each master control chip are connected to the input voltage signal and perform non-isolated DC-DC step-down processing on the input voltage signal to obtain their respective output voltage signals. The EN pin of the master control chip that outputs the highest output voltage signal is connected to the output pin of another master control chip. Each main control chip has an input capacitor between the input voltage signal and the input pin. One end of the input capacitor is connected between the input voltage signal of the main control chip and the input pin, and the other end of the input capacitor is grounded. Each main control chip has its corresponding voltage divider circuit. The voltage divider circuit includes a first voltage divider resistor connected between the feedback pin and the output pin of the main control chip and a second voltage divider resistor connected between the feedback pin of the main control chip and ground. The first voltage divider resistor and the second voltage divider resistor are connected to each other. Each main control chip has its corresponding feedback circuit, which includes a first feedback capacitor connected between the feedback pin and the output pin of the main control chip. The first feedback capacitor is connected in parallel with the first voltage divider resistor of the corresponding main control chip. A voltage adjustment pin is connected between the first voltage divider circuit and the second voltage divider resistor of the main control chip, which is not used to output the highest output voltage signal. Each main control chip has several output capacitors connected in parallel between its output pin and ground.
2. The integrated inductor-based buck chip-based DC-DC non-isolated buck circuit according to claim 1, characterized in that, The main control chip includes a first main control chip U1, a second main control chip U2 and a third main control chip U3, and the second main control chip U2 and the third main control chip U3 are of the same model. The first main control chip U1 is used to output the first output voltage signal, the second main control chip U2 is used to output the second output voltage signal, and the third main control chip U3 is used to output the third output voltage signal, and the voltage corresponding to the first output voltage signal is the highest value among all channels.
3. The integrated inductor-based buck chip-based DC-DC non-isolated buck circuit according to claim 2, characterized in that, A first capacitor C1 is provided between the input voltage signal of the first main control chip U1 and the input pin. One end of the first capacitor C1 is connected between the input voltage signal of the first main control chip U1 and the input pin, and the other end of the first capacitor C1 is grounded. A fifteenth capacitor C15 is provided between the input voltage signal of the second main control chip U2 and the input pin. One end of the fifteenth capacitor C15 is connected between the input voltage signal of the second main control chip U2 and the input pin, and the other end of the fifteenth capacitor C15 is grounded. A twentieth capacitor C20 is provided between the input voltage signal and the input pin of the third main control chip U3. One end of the twentieth capacitor C20 is connected between the input voltage signal and the input pin of the third main control chip U3, and the other end of the twentieth capacitor C20 is grounded.
4. The integrated inductor-based buck chip based DC-DC non-isolated buck circuit of claim 2, wherein, The voltage divider resistors of the first main control chip U1 include a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the feedback pin and the output pin of the first main control chip U1, and the second resistor R2 is connected between the feedback pin and ground of the first main control chip U1. The first resistor R1 and the second resistor R2 are connected. The voltage divider resistors of the second main control chip U2 include a third resistor R3 and a fourth resistor R4. The third resistor R3 is connected between the feedback pin and the output pin of the second main control chip U2, and the fourth resistor R4 is connected between the feedback pin and ground of the second main control chip U2. The third resistor R3 and the fourth resistor R4 are connected together. The voltage divider resistors of the third main control chip U3 include a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is connected between the feedback pin and the output pin of the third main control chip U3, and the sixth resistor R6 is connected between the feedback pin and ground of the third main control chip U3. The fifth resistor R5 and the sixth resistor R6 are connected together.
5. The integrated inductor-based buck chip-based DC-DC non-isolated buck circuit according to claim 4, characterized in that, A second capacitor C2 is provided between the feedback pin and the output pin of the first main control chip U1, and the second capacitor C2 is connected in parallel with the first resistor R1. The second main control chip U2 has a fifth capacitor C5 between its feedback pin and output pin, and the fifth capacitor C5 is connected in parallel with the third resistor R3. The third main control chip U3 has a seventh capacitor C7 between its feedback pin and output pin, and the seventh capacitor C7 is connected in parallel with the fifth resistor R5.
6. The integrated inductor-based buck chip based DC-DC non-isolated buck circuit of claim 4, wherein, A voltage adjustment pin is brought out between the third resistor R3 and the fourth resistor R4, and another voltage adjustment pin is brought out between the fifth resistor R5 and the sixth resistor R6.
7. The DC-DC non-isolated buck circuit based on an integrated inductor buck chip according to claim 2, characterized in that, A third capacitor C3 and a fourth capacitor C4 are provided between the output pin of the first main control chip U1 and ground, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel. The output pin of the second main control chip U2 is connected to ground by a sixth capacitor C6 and a sixteenth capacitor C16, which are connected in parallel. The third main control chip U3 has an eighth capacitor C8 and a seventeenth capacitor C17 connected in parallel between its output pin and ground.
8. The integrated inductor-based buck chip based DC-DC non-isolated buck circuit of claim 2, wherein, The peripheral circuit of the first main control chip U1 is equipped with a bootstrap capacitor, which is connected between the BS pin and the LX pin of the first main control chip U1.
9. The integrated inductor-based buck chip based DC-DC non-isolated buck circuit of claim 2, wherein, The LX pin of the main control chip is integrated with the power inductor and switching transistor inside the main control chip, and each main control chip has two LX pins. The LX pins of the same main control chip are shorted and connected in parallel.
10. The integrated inductor-based buck chip based DC-DC non-isolated buck circuit of claim 2, wherein, The SS pin of the first main control chip U1 is connected to the twenty-first capacitor C21 and grounded.