Clock generation circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a clock generation circuit, a chip and an electronic device. The clock generation circuit comprises a reference module used for generating a reference current according to a reference voltage; the RC oscillation module is connected with the reference module so as to oscillate according to the reference current and output a clock signal; the oscillation-starting acceleration module is connected with the reference module so as to input a first oscillation-starting acceleration signal to the reference module when the clock generation circuit starts oscillation; wherein the first oscillation starting acceleration signal is used for controlling the reference module to accelerate to generate the reference current when the clock generation circuit starts oscillation. The oscillation starting establishment time of the clock generation circuit is shortened, and the purpose of rapidly outputting the clock signal is achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a clock generating circuit, chip, and electronic device. Background Technology

[0002] Currently, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. In on-chip systems where clock source accuracy and frequency requirements are not high, RC oscillators are widely used due to their low cost and ease of on-chip integration. However, current RC oscillators have a relatively long settling time, which leads to the problem that they cannot quickly output a clock signal. Utility Model Content

[0003] In view of the above problems, embodiments of this application provide a clock generating circuit, chip, and electronic device to solve the above technical problems.

[0004] In a first aspect, embodiments of this application provide a clock generation circuit, including:

[0005] A reference module used to generate a reference current based on a reference voltage;

[0006] An RC oscillation module is connected to a reference module to oscillate according to a reference current and output a clock signal.

[0007] An oscillation acceleration module is connected to a reference module to input a first oscillation acceleration signal to the reference module when the clock generation circuit starts oscillating.

[0008] The first oscillation acceleration signal is used to control the reference module to accelerate the generation of reference current when the clock generation circuit starts oscillating.

[0009] Secondly, embodiments of this application also provide a chip including the clock generation circuit described above.

[0010] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or clock generating circuit.

[0011] This application establishes a reference current based on a reference voltage using a reference module, enabling the RC oscillation module to oscillate and output a clock signal based on the reference current. Since the oscillation acceleration module can input a first oscillation acceleration signal to the reference module when the clock generation circuit starts oscillating, the reference module can be controlled to accelerate the generation of the reference current when the clock generation circuit starts oscillating. This helps to shorten the oscillation setup time of the clock generation circuit, thereby achieving the goal of quickly outputting a clock signal.

[0012] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A circuit diagram of an RC oscillator in the related art is shown.

[0015] Figure 2 A schematic diagram of a clock generation circuit in an embodiment of this application is shown.

[0016] Figure 3 A circuit diagram of a reference module in an embodiment of this application is shown.

[0017] Figure 4 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.

[0018] Figure 5 A circuit diagram of an RC oscillation module in an embodiment of this application is shown.

[0019] Figure 6 Another circuit diagram of the RC oscillation module in an embodiment of this application is shown.

[0020] Figure 7 A schematic diagram of a reference module and a vibration acceleration module in an embodiment of this application is shown.

[0021] Figure 8 A circuit diagram of a reference module and an oscillation acceleration module in an embodiment of this application is shown.

[0022] Figure 9 A circuit diagram of a vibration acceleration module in an embodiment of this application is shown.

[0023] Figure 10 Another circuit diagram of the oscillation acceleration module in an embodiment of this application is shown.

[0024] Figure 11 Another circuit diagram of the oscillation acceleration module in an embodiment of this application is shown.

[0025] Figure 12 A circuit diagram of a reference module and an oscillation acceleration module in an embodiment of this application is shown.

[0026] Figure 13 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.

[0027] Figure 14 A circuit diagram of the first comparison unit in an embodiment of this application is shown.

[0028] Figure 15 Another circuit diagram of the reference module and the oscillation acceleration module in an embodiment of this application is shown.

[0029] Figure 16 Another circuit diagram of the oscillation acceleration module in an embodiment of this application is shown.

[0030] Figure 17 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.

[0031] Figure 18 A schematic diagram showing a voltage change of the first capacitor and the second capacitor in an embodiment of this application is shown.

[0032] Figure 19 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.

[0033] Figure 20 A circuit diagram of a charging current control module in an embodiment of this application is shown.

[0034] Figure 21 A timing diagram of the relevant signals in an embodiment of this application is shown.

[0035] Among them, 10 is the reference module, 20 is the RC oscillation module, 21 is the first charging and discharging unit, 22 is the first comparison unit, 23 is the first logic unit, 30 is the oscillation acceleration module, 31 is the clamping unit, 40 is the charging current control module, 41 is the second charging and discharging unit, 42 is the second comparison unit, and 43 is the second logic unit.

[0036] Clock signal CLK, reference voltage Vref, reference current Iref, first oscillation acceleration signal Vcrtl, second oscillation acceleration signal VBN, operational amplifier OP, first transistor M1, first resistor R1, second resistor R2, second transistor M2, third transistor M3, fourth transistor M4, first node m1, first bias current source IN, second bias current source IP, first reference voltage VCH, second reference voltage VCL, power supply terminal VDD, ground terminal GND;

[0037] First sub-inverter INA, second sub-inverter INB, third sub-inverter INC, first sub-PMOS transistor Mp1, second sub-PMOS transistor Mp2, first sub-NMOS transistor Mn1, second sub-NMOS transistor Mn2;

[0038] First inverter IN1, second inverter IN2, third inverter IN3, fourth inverter IN4, fifth inverter IN5, sixth inverter IN6, seventh inverter IN7, eighth inverter IN8, ninth inverter IN9, tenth inverter IN10, eleventh inverter IN11, twelfth inverter IN12, thirteenth inverter IN13, fourteenth inverter IN14, first NAND gate NAND1, second NAND gate NAND2, third NAND gate NAND3, fourth NAND gate NAND4, fifth NAND gate NAND5, sixth NAND gate NAND6;

[0039] First comparator COMP1, second comparator COMP2, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6, first charge / discharge signal VC1, second charge / discharge signal VC2, first comparison signal VP1, second comparison signal VP2, third comparison signal VP3, fourth comparison signal VP4, first control signal Q1, second control signal Q1B, third control signal Q2, fourth control signal Q2B, first switch signal S1, second switch signal S2, switch control signal Sn;

[0040] First PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9, tenth PMOS transistor MP10, eleventh PMOS transistor MP11, twelfth PMOS transistor MP12.

[0041] The first NMOS transistor is MN1, the second NMOS transistor is MN2, the third NMOS transistor is MN3, the fourth NMOS transistor is MN4, the fifth NMOS transistor is MN5, the sixth NMOS transistor is MN6, the seventh NMOS transistor is MN7, the eighth NMOS transistor is MN8, the ninth NMOS transistor is MN9, and the tenth NMOS transistor is MN10. Detailed Implementation

[0042] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0043] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0045] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] In the description of the embodiments in this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0047] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0048] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0049] In the embodiments of this application, the control terminal of each transistor is the gate, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistors in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain.

[0050] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0051] Currently, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. (See also...) Figure 1 , Figure 1 The diagram shows a circuit schematic of an RC oscillator in the related art. The RC oscillator includes comparator COMP1, comparator COMP2, an RS flip-flop composed of two NAND gates, capacitor Cx, capacitor Cy, transistor MN1 for controlling the charging and discharging of capacitor Cx, and transistor MN2 for controlling the charging and discharging of capacitor Cy.

[0052] During the operation of the RC oscillator, the two NAND gates output control signals OUT1 and OUT2 respectively, thereby controlling transistors MN1 and MN2 to alternately charge capacitors Cx and Cy. When the output voltages IN1 and IN2 of capacitors Cx and Cy exceed the reference voltage Vref (based on the current I...), the oscillator continues to operate. ref When the resistor R is generated, one of the capacitors Cx and Cy is charged while the other is discharged, thus realizing the process of alternating charging and discharging of capacitors Cx and Cy.

[0053] In an ideal scenario where loop delays (such as comparator delays) are neglected, the capacitors Cx and Cy charge to the reference voltage Vref for half a cycle of the clock signal, meaning the clock signal period satisfies the following relationship:

[0054]

[0055] Where T is the period of the clock signal, C is the capacitance value of capacitors Cx and Cy, and N is the current mirror factor.

[0056] By transforming the above formula, we can see that the period of the clock signal satisfies the following relationship:

[0057]

[0058] It can be seen that the period of the clock signal is related to the current I. ref Regardless of magnitude, the period of the clock signal depends only on the resistor R, capacitor C, and current mirror factor N.

[0059] However, the operation of an RC oscillator requires a reference current source to establish a reference current. Only after mirroring the reference current through a current mirror can the aforementioned charging current NI for capacitors Cx and Cy be generated. ref And the current I that generates the reference voltage Vref ref Therefore, the RC oscillator's oscillation setup time is affected by the setup time of the reference current source, which leads to the problem that the RC oscillator has a long oscillation setup time and cannot output a clock signal quickly.

[0060] Therefore, this application provides a clock generating circuit, a chip, and an electronic device, which will be described in detail below.

[0061] First, refer to Figure 2 , Figure 2 A schematic diagram of a clock generation circuit in an embodiment of this application is shown, wherein the clock generation circuit includes a reference module 10, an RC oscillation module 20, and an oscillation acceleration module 30.

[0062] Specifically, the reference module 10 can generate a reference current Iref based on the reference voltage Vref, so that the RC oscillation module 20 can oscillate based on the reference current Iref and output a clock signal CLK. Generally, the RC oscillation module 20 can mirror the reference current Iref through a current mirror to output multiple currents, one or two of which are used as charging currents, and the other current generates a reference voltage that is compared with the charging and discharging voltage through a resistor.

[0063] As an exemplary embodiment of reference module 10, see [reference]. Figure 3 , Figure 3 The diagram shows a circuit schematic of a reference module 10 in an embodiment of this application. The reference module 10 includes an operational amplifier OP, a first transistor M1, and a first resistor R1. The first terminal of the first transistor M1 is connected to the power supply terminal VDD, the second terminal of the first transistor M1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the ground terminal GND. The first input terminal of the operational amplifier OP is connected to the reference voltage Vref, the second input terminal of the operational amplifier OP is connected to the first node m1 between the first transistor M1 and the first resistor R1, and the output terminal of the operational amplifier OP is connected to the control terminal of the first transistor M1.

[0064] It should be noted that after the operational amplifier (OP) feedback loop stabilizes, according to the virtual short and virtual open characteristics of the OP, the voltage at the first node m1 is equal to the reference voltage Vref, i.e., VCH = Vref. Therefore, the magnitude of the reference current Iref flowing through the first transistor M1 is:

[0065]

[0066] It can be seen that after the operational amplifier (OP) feedback loop is stabilized, a reference current Iref related to the magnitude of the reference voltage Vref and the magnitude of the first resistor R1 can be generated. The RC oscillation module 20 can be charged by mirroring the reference current Iref of the branch where the first transistor M1 is located through the current mirror.

[0067] The RC oscillation module 20 is connected to the reference module 10. The RC oscillation module 20 can oscillate according to the reference current Iref and output a clock signal CLK. Generally, refer to Figure 4 , Figure 4 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown. The RC oscillation module 20 includes a first charging / discharging unit 21, a first comparison unit 22, and a first logic unit 23. The first charging / discharging unit 21 can charge based on a reference current Iref and output a periodically changing charging / discharging voltage signal. The first comparison unit 22 is connected to the first charging / discharging unit 21 and to a reference module 10. The first comparison unit 22 can compare the charging / discharging voltage signal with the magnitude of a first reference voltage VCH and output a comparison signal. The first logic unit 23 is connected to the first comparison unit 22 and to the first charging / discharging unit 21. The first logic unit 23 can input a control signal to the first charging / discharging unit 21 based on the comparison signal. The control signal can control the first charging / discharging unit 21 to charge and discharge alternately, thereby causing the first charging / discharging unit 21 to output a periodically changing charging / discharging voltage signal.

[0068] As an example, see Figure 5 , Figure 5A circuit diagram of an RC oscillation module 20 in an embodiment of this application is shown. The first charging / discharging unit 21 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first capacitor C1, and a second capacitor C2. The first comparison unit 22 includes a first comparator COMP1 and a second comparator COMP2. The first logic unit 23 includes an RS flip-flop. The charging / discharging signals output by the first charging / discharging unit 21 include a first charging / discharging signal VC1 and a second charging / discharging signal VC2. The first charging / discharging signal VC1 is the voltage of the first capacitor C1, and the second charging / discharging signal VC2 is the voltage of the second capacitor C2. The comparison signals output by the first comparison unit 22 include a first comparison signal VP1 and a second comparison signal VP2. The control signals output by the first logic unit 23 include a first control signal Q1 and a second control signal Q1B.

[0069] Assuming that the first control signal Q1 output by the RS flip-flop is high and the second control signal Q1B is low in the initial state, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, while the second PMOS transistor MP2 and the first NMOS transistor MN1 are turned off. Therefore, the first capacitor C1 is charged and the second capacitor C2 is discharged.

[0070] When the voltage of the first capacitor C1 (i.e. the first charge / discharge signal VC1) reaches the first reference voltage VCH, the first comparison signal VP1 output by the first comparator COMP1 changes to a low level. Therefore, the first control signal Q1 output by the RS flip-flop changes to a low level and the second control signal Q1B changes to a high level. At this time, the first PMOS transistor MP1 and the second NMOS transistor MN2 are cut off, while the second PMOS transistor MP2 and the first NMOS transistor MN1 are turned on. Therefore, the second capacitor C2 is charged and the first capacitor C1 is discharged.

[0071] When the voltage of the second capacitor C2 (i.e., the second charge / discharge signal VC2) reaches the first reference voltage VCH, the second comparison signal VP2 output by the second comparator COMP2 is low, causing the first control signal Q1 output by the RS flip-flop to change to a high level and the second control signal Q1B to a low level. The first capacitor C1 is recharged and the second capacitor C2 is re-discharged. The above process is repeated, and the first control signal Q1 or the second control signal Q1B can be used as the output clock signal CLK.

[0072] It is understood that the above embodiments are merely illustrative examples of the RC oscillation module 20, and those skilled in the art can make equivalent modifications to the RC oscillation module 20, for example, referring to... Figure 6 , Figure 6Another circuit diagram of the RC oscillation module 20 in this embodiment is shown, wherein the first NMOS transistor MN1 is connected in parallel with the first capacitor C1, and the second NMOS transistor MN2 is connected in parallel with the second capacitor C2. The charging and discharging of the first capacitor C1 and the second capacitor C2 can be controlled by the first NMOS transistor MN1 and the second NMOS transistor MN2, respectively. At the same time, the RS flip-flop can also be replaced by a logic circuit composed of a first inverter IN1, a second inverter IN2, a third inverter IN3, a fourth inverter IN4, a fifth inverter IN5, a sixth inverter IN6, a first NAND gate NAND1, and a second NAND gate NAND2.

[0073] The oscillation acceleration module 30 is connected to the reference module 10. The oscillation acceleration module 30 can input a first oscillation acceleration signal Vcrtl to the reference module 10 when the clock generation circuit starts oscillating. The first oscillation acceleration signal Vcrtl can control the reference module 10 to accelerate the generation of the reference current Iref when the clock generation circuit starts oscillating.

[0074] It should be noted that when the clock generation circuit starts oscillating, the reference module 10 cannot instantaneously generate the reference current Iref. Therefore, the start-up time of the clock generation circuit is affected by the time it takes for the reference module 10 to establish the reference current Iref. For example, with... Figure 3 For example, the reference module 10 can only generate a stable reference current Iref when the feedback loop of the operational amplifier OP is stable and the voltage of the first node m1 is clamped to the reference voltage Vref.

[0075] In this embodiment, since the oscillation acceleration module 30 can input a first oscillation acceleration signal Vcrtl to the reference module 10 when the clock generation circuit starts oscillating, the reference module 10 can quickly generate a reference current Iref under the control of the first oscillation acceleration signal Vcrtl. For example, with Figure 3 For example, when the clock generation circuit starts oscillating, the oscillation acceleration module 30 can input a low-level signal to the control terminal of the first transistor M1 as the first oscillation acceleration signal Vcrtl. The first transistor M1 is quickly turned on, and the voltage of the first node m1 rises rapidly, thereby making the feedback loop of the operational amplifier OP quickly stabilize, and finally making the reference module 10 quickly generate the reference current Iref.

[0076] Understandably, the oscillation acceleration module 30 can also input a first oscillation acceleration signal Vcrtl to the internal circuit node of the operational amplifier OP when the clock generation circuit starts oscillating, thereby enabling the feedback loop of the operational amplifier OP to stabilize quickly.

[0077] In this embodiment, the reference module 10 establishes a reference current Iref based on the reference voltage Vref, so that the RC oscillation module 20 can oscillate according to the reference current Iref and output a clock signal CLK. Since the oscillation acceleration module 30 can input a first oscillation acceleration signal Vcrtl to the reference module 10 when the clock generation circuit starts oscillating, the reference module 10 can be controlled to accelerate the generation of the reference current Iref when the clock generation circuit starts oscillating, which helps to shorten the oscillation setup time of the clock generation circuit, thereby achieving the purpose of quickly outputting the clock signal CLK.

[0078] In some embodiments of this application, the oscillation acceleration module 30 can control the output of the first oscillation acceleration signal Vcrtl in response to the magnitude of the reference current Iref. That is, the oscillation acceleration module 30 can perform feedback control on the reference module 10 according to the magnitude of the reference current Iref. For example, when the reference current Iref is less than a preset threshold, the oscillation acceleration module 30 inputs the first oscillation acceleration signal Vcrtl to the reference module 10, so that the reference module 10 quickly generates a reference current Iref of a stable magnitude; while when the reference current Iref is greater than or equal to the preset threshold, the oscillation acceleration module 30 stops inputting the first oscillation acceleration signal Vcrtl to the reference module 10, thereby helping to avoid the phenomenon that the reference module 10 continues to be affected by the first oscillation acceleration signal Vcrtl.

[0079] In some embodiments of this application, such as embodiments of the operational amplifier OP, the first transistor M1, and the first resistor R1 of reference module 10, see [reference]. Figure 7 , Figure 7 The diagram shows a reference module 10 and an oscillation acceleration module 30 in an embodiment of this application. The input terminal of the oscillation acceleration module 30 is connected to the first node m1, and the output terminal of the oscillation acceleration module 30 is connected to the control terminal of the first transistor M1.

[0080] Specifically, when the clock generation circuit starts oscillating and the reference current Iref is less than a preset threshold, the voltage of the first node m1 is low. Therefore, the oscillation acceleration module 30 can respond to the low-level signal of the first node m1 by inputting a first oscillation acceleration signal Vcrtl to the control terminal of the first transistor M1. This first oscillation acceleration signal Vcrtl can pull down the voltage of the control terminal of the first transistor M1 when the clock generation circuit starts oscillating, thereby causing the voltage of the first node m1 and the reference current Iref to increase rapidly. When the magnitude of the reference current Iref reaches the preset threshold, the voltage of the first node m1 is high. Therefore, the oscillation acceleration module 30 can respond to the high-level signal of the first node m1 by stopping the input of the first oscillation acceleration signal Vcrtl to the control terminal of the first transistor M1.

[0081] As an exemplary embodiment of the vibration acceleration module 30, see [reference]. Figure 8 , Figure 8 The diagram shows a circuit diagram of reference module 10 and oscillation acceleration module 30 in an embodiment of this application. The oscillation acceleration module 30 includes a second transistor M2 and a first bias current source IN. The second terminal of the second transistor M2 is connected to the control terminal of the first transistor M1, the first terminal of the second transistor M2 is connected to the first terminal of the first bias current source IN, and the second terminal of the first bias current source IN is connected to the ground terminal GND.

[0082] Specifically, when the reference current Iref is less than the preset threshold, the voltage of the first node m1 is low. After the inverter inverts the control terminal of the second transistor M2, it receives a high-level signal, so the second transistor M2 is in the conducting state. Thus, the first bias current source IN can pull down the voltage of the control terminal of the first transistor M1, so that the first transistor M1 is turned on and quickly establishes the reference current Iref. When the reference current Iref is greater than or equal to the preset threshold, the voltage of the first node m1 is high. After the inverter inverts the control terminal of the second transistor M2, it receives a low-level signal, so the second transistor M2 is in the cut-off state. At this time, the oscillation acceleration module 30 stops inputting the first oscillation acceleration signal Vcrtl to the control terminal of the first transistor M1, thereby avoiding the phenomenon that the reference module 10 continues to be affected by the first oscillation acceleration signal Vcrtl after the clock generation circuit has completed oscillation.

[0083] In some embodiments of this application, see Figure 9 , Figure 9 The diagram shows a circuit diagram of an oscillation acceleration module 30 in an embodiment of this application. The oscillation acceleration module 30 further includes a second bias current source IP, a fourth transistor M4, a first sub-inverter INA, and a second sub-inverter INB. The first terminal of the second bias current source IP is connected to the power supply terminal VDD, the second terminal of the second bias current source IP is connected to the second terminal of the fourth transistor M4, and the first terminal of the fourth transistor M4 is connected to the ground terminal GND. The input terminal of the first sub-inverter INA is connected to the second terminal of the fourth transistor M4, the output terminal of the first sub-inverter INA is connected to the input terminal of the second sub-inverter INB, and the output terminal of the second sub-inverter INB is connected to the control terminal of the second transistor M2.

[0084] Specifically, when the reference current Iref is less than the preset threshold, the voltage (VCH) of the first node m1 is low, and the fourth transistor M4 is in the off state. Due to the presence of the first sub-inverter INA and the second sub-inverter INB, node A is high, node B is low, and node C is high. Therefore, the second transistor M2 is in the on state and outputs the first oscillation acceleration signal Vcrtl, enabling the reference module 10 to quickly establish the reference current Iref. Conversely, when the reference current Iref is greater than or equal to the preset threshold, the voltage (VCH) of the first node m1 is high, and the fourth transistor M4 is in the on state. At this time, node A is low, node B is high, and node C is low. Therefore, the second transistor M2 is in the off state and stops outputting the first oscillation acceleration signal Vcrtl.

[0085] In some embodiments of this application, see Figure 10 , Figure 10 The diagram shows another circuit diagram of the oscillation acceleration module 30 in this embodiment of the present application. The oscillation acceleration module 30 further includes a clamping unit 31. The clamping unit 31 is connected to the input terminal of the first sub-inverter INA, the input terminal of the second sub-inverter INB, and the output terminal of the second sub-inverter INB. The clamping unit 31 clamps the input terminal of the first sub-inverter INA and the output terminal of the first sub-inverter INA to be at opposite levels, and the input terminal of the second sub-inverter INB and the output terminal of the second sub-inverter INB to be at opposite levels.

[0086] It should be noted that during the operation of the oscillation acceleration module 30, since the transistors inside the inverter may be turned on simultaneously, the voltages at the input terminals of the first sub-inverter INA, the input terminals of the second sub-inverter INB, and the output terminals of the second sub-inverter INB may have the same level. This may cause the second transistor M2 to fail to be turned on and output the first oscillation acceleration signal Vcrtl, or the first oscillation acceleration signal Vcrtl to still be output after the clock generation circuit has completed oscillation.

[0087] In the above embodiment, since the clamping unit 31 can clamp the input terminal of the first sub-inverter INA to be opposite to the output terminal of the first sub-inverter INA, and the input terminal of the second sub-inverter INB to be opposite to the output terminal of the second sub-inverter INB, it can be ensured that the levels of node A and node B are opposite, and the levels of node B and node C are opposite. For example, if node A is a low-level signal, the clamping unit 31 can clamp node B to be high and node C to be low; or if node A is a high-level signal, the clamping unit 31 can clamp node B to be low and node C to be high, thereby helping to ensure the reliability of the control of the second transistor M2.

[0088] As an example, see Figure 11 , Figure 11 This illustration shows another circuit diagram of the oscillation acceleration module 30 in an embodiment of this application. The clamping unit 31 includes a first sub-PMOS transistor Mp1, a second sub-PMOS transistor Mp2, a first sub-NMOS transistor Mn1, and a second sub-NMOS transistor Mn2. The first terminal of the first sub-PMOS transistor Mp1 is connected to the power supply terminal VDD, the second terminal of the first sub-PMOS transistor Mp1 is connected to the first terminal of the second sub-PMOS transistor Mp2, and the control terminal of the first sub-PMOS transistor Mp1 is connected to the output terminal of the second sub-inverter INB. The second terminal of the second sub-PMOS transistor Mp2 is connected to the first sub-NMOS transistor Mn2. The second terminal of OS transistor Mn1 is connected to the first sub-inverter INA, and the control terminal of the second sub-PMOS transistor Mp2 is connected to the input terminal of the first sub-inverter INA. The second terminal of the second sub-PMOS transistor Mp2 is connected to the output terminal of the first sub-inverter INA. The first terminal of the first sub-NMOS transistor Mn1 is connected to the second terminal of the second sub-NMOS transistor Mn2, and the control terminal of the first sub-NMOS transistor Mn1 is connected to the input terminal of the first sub-inverter INA. The first terminal of the second sub-NMOS transistor Mn2 is connected to the ground terminal GND, and the control terminal of the second sub-NMOS transistor Mn2 is connected to the output terminal of the second sub-inverter INB.

[0089] Specifically, when node A is a low-level signal and node C is a low-level signal, the first sub-PMOS transistor Mp1 and the second sub-PMOS transistor Mp2 are turned on, and the first sub-NMOS transistor Mn1 and the second sub-NMOS transistor Mn2 are turned off. Therefore, node B is clamped to a high level, making the levels of node A and node B opposite, and the levels of node B and node C opposite. Conversely, when node A is a high-level signal and node C is a high-level signal, the first sub-PMOS transistor Mp1 and the second sub-PMOS transistor Mp2 are turned off, and the first sub-NMOS transistor Mn1 and the second sub-NMOS transistor Mn2 are turned on. Therefore, node B is clamped to a low level, making the levels of node A and node B opposite, and the levels of node B and node C opposite.

[0090] It is understood that the above embodiments are merely exemplary embodiments of the reference module 10 and the vibration acceleration module 30, and those skilled in the art can make equivalent modifications to the reference module 10 and the vibration acceleration module 30, for example, referring to... Figure 12 , Figure 12 The diagram shows a circuit diagram of the reference module 10 and the oscillation acceleration module 30 in an embodiment of this application. In this application, the control terminal of the second transistor M2 can also be directly connected to the second terminal of the fourth transistor M4. Furthermore, the reference module 10 can be further configured with a second resistor R2 to generate a first reference voltage VCH and a second reference voltage VCL across the first resistor R1, respectively.

[0091] In some embodiments of this application, such as the embodiment where the RC oscillation module 20 includes a first charging / discharging unit 21, a first comparison unit 22, and a first logic unit 23, see [reference]. Figure 13 , Figure 13 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the oscillation acceleration module 30 is also connected to the first comparison unit 22 to input a second oscillation acceleration signal VBN to the first comparison unit 22 when the clock generation circuit starts oscillating. The second oscillation acceleration signal VBN is used to control the first comparison unit 22 to accelerate the start-up when the clock generation circuit starts oscillating.

[0092] It should be noted that when the clock generation circuit starts oscillating, the circuit of the first comparison unit 22 cannot start quickly. Therefore, the start-up time of the clock generation circuit is also affected by the start-up time of the first comparison unit 22. In the above embodiment, since the oscillation acceleration module 30 can also input a second oscillation acceleration signal VBN to the first comparison unit 22 when the clock generation circuit starts oscillating, the second oscillation acceleration signal VBN can control the first comparison unit 22 to start up faster when the clock generation circuit starts oscillating, thereby helping to further shorten the start-up time of the clock generation circuit.

[0093] As an example, see Figure 14 , Figure 14 The diagram shows a circuit schematic of the first comparison unit 22 in an embodiment of this application. The first comparison unit 22 includes a bias current source IBN, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8.

[0094] Specifically, the first terminal of the third PMOS transistor MP3 is connected to the power supply terminal VDD, the control terminal of the third PMOS transistor MP3 is connected to the second terminal of the third PMOS transistor MP3, the second terminal of the third PMOS transistor MP3 is connected to the second terminal of the third NMOS transistor MN3; the first terminal of the third NMOS transistor MN3 is connected to the first terminal of the bias current source IBN, the second terminal of the bias current source IBN is connected to the ground terminal GND, and the control terminal of the third NMOS transistor MN3 is connected to the first charge / discharge signal VC1.

[0095] The first terminal of the fourth PMOS transistor MP4 is connected to the power supply terminal VDD, the control terminal of the fourth PMOS transistor MP4 is connected to the second terminal of the fourth PMOS transistor MP4, the second terminal of the fourth PMOS transistor MP4 is connected to the second terminal of the fourth NMOS transistor MN4, the first terminal of the fourth NMOS transistor MN4 is connected to the first terminal of the bias current source IBN, and the control terminal of the fourth NMOS transistor MN4 is connected to the second charge / discharge signal VC2.

[0096] The first terminal of the fifth PMOS transistor MP5 is connected to the power supply terminal VDD, the control terminal of the fifth PMOS transistor MP5 is connected to the second terminal of the fifth PMOS transistor MP5, the second terminal of the fifth PMOS transistor MP5 is connected to the second terminal of the fifth NMOS transistor MN5, the first terminal of the fifth NMOS transistor MN5 is connected to the first terminal of the bias current source IBN, and the control terminal of the fifth NMOS transistor MN5 is connected to the first reference voltage VCH.

[0097] The first terminal of the sixth PMOS transistor MP6 is connected to the power supply terminal VDD. The control terminal of the sixth PMOS transistor MP6 is connected to the control terminal of the fifth PMOS transistor MP5. The second terminal of the sixth PMOS transistor MP6 is connected to the second terminal of the sixth NMOS transistor MN6. The control terminal of the sixth NMOS transistor MN6 is connected to the second terminal of the sixth NMOS transistor MN6. The second terminal of the sixth NMOS transistor MN6 is connected to the ground terminal GND.

[0098] The first terminal of the seventh PMOS transistor MP7 is connected to the power supply terminal VDD; the control terminal of the seventh PMOS transistor MP7 is connected to the control terminal of the third PMOS transistor MP3; the second terminal of the seventh PMOS transistor MP7 is connected to the second terminal of the seventh NMOS transistor MN7; the control terminal of the seventh NMOS transistor MN7 is connected to the control terminal of the sixth NMOS transistor MN6; and the second terminal of the seventh NMOS transistor MN7 is connected to the ground terminal GND.

[0099] The first terminal of the eighth PMOS transistor MP8 is connected to the power supply terminal VDD. The control terminal of the eighth PMOS transistor MP8 is connected to the control terminal of the fourth PMOS transistor MP4. The second terminal of the eighth PMOS transistor MP8 is connected to the second terminal of the eighth NMOS transistor MN8. The control terminal of the eighth NMOS transistor MN8 is connected to the control terminal of the sixth NMOS transistor MN6. The second terminal of the eighth NMOS transistor MN8 is connected to the ground terminal GND.

[0100] It should be noted that the third NMOS transistor MN3 and the fifth NMOS transistor MN5 are a differential input pair. When the first charge / discharge signal VC1 is greater than the first reference voltage VCH, the voltage at the second terminal of the third PMOS transistor MP3 is pulled low. Since the second terminal of the third PMOS transistor MP3, the control terminal of the third PMOS transistor MP3, and the control terminal of the seventh PMOS transistor MP7 are interconnected, the voltage at the control terminal of the seventh PMOS transistor MP7 is pulled low and turned on. At this time, the first comparison signal VP1 output by node m01 is high. Similarly, when the first charge / discharge signal VC1 is less than the first reference voltage VCH, the first comparison signal VP1 output by node m01 is low.

[0101] The fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 form another differential input pair. When the second charge / discharge signal VC2 is greater than the first reference voltage VCH, the voltage at the second terminal of the fourth PMOS transistor MP4 is pulled low. Since the second terminal of the fourth PMOS transistor MP4, the control terminal of the fourth PMOS transistor MP4, and the control terminal of the eighth PMOS transistor MP8 are interconnected, the voltage at the control terminal of the eighth PMOS transistor MP8 is pulled low and turned on. At this time, the second comparison signal VP2 output by node m02 is high. Similarly, when the second charge / discharge signal VC2 is less than the first reference voltage VCH, the second comparison signal VP2 output by node m01 is low.

[0102] It can be seen that, for comparing the first charge / discharge signal VC1 and the second charge / discharge signal VC2, the first comparison unit 22 uses the fifth PMOS transistor MP5, the fifth NMOS transistor MN5, the sixth PMOS transistor MP6, and the sixth NMOS transistor MN6 to compare the magnitudes of the first charge / discharge signal VC1 with the first reference voltage VCH, and the second charge / discharge signal VC2 with the first reference voltage VCH. In contrast, the first comparison unit 22 uses two comparators (such as...). Figure 5 The above embodiments are beneficial for reducing the circuit area and cost of the clock generation circuit.

[0103] Meanwhile, when the clock generation circuit starts oscillating, the oscillation acceleration module 30 can input a high-level signal as the second oscillation acceleration signal VBN to the control terminals of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8, thereby enabling the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 to conduct quickly. Therefore, the second oscillation acceleration signal VBN can control the first comparison unit 22 to accelerate its start-up when the clock generation circuit starts oscillating, thereby further shortening the start-up time of the clock generation circuit.

[0104] As another exemplary embodiment of the vibration acceleration module 30, see [reference]. Figure 15 , Figure 15This paper shows another circuit diagram of reference module 10 and oscillation acceleration module 30 in an embodiment of this application. The oscillation acceleration module 30 includes a third transistor M3 and a second bias current source IP. The first terminal of the second bias current source IP is connected to the power supply terminal VDD, the second terminal of the second bias current source IP is connected to the first terminal of the third transistor M3, and the second terminal of the third transistor M3 is connected to the first comparison unit 22.

[0105] Specifically, when the reference current Iref is less than the preset threshold, the voltage of the first node m1 is low, the fourth transistor M4 is cut off, the inverter input is a high-level signal, and the inverter output is a low-level signal. Therefore, the third transistor M3 is in the conducting state, so that the second bias current source IP can input a high-level signal to the control terminals of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 as the second oscillation acceleration signal VBN, so that the first comparator unit 22 starts up quickly.

[0106] When the reference current Iref is greater than or equal to the preset threshold, the voltage of the first node m1 is high, the fourth transistor M4 is turned on, the inverter input is a low-level signal, and the inverter output is a high-level signal. Therefore, the third transistor M3 is in the off state. At this time, the oscillation acceleration module 30 stops inputting the second oscillation acceleration signal VBN to the control terminals of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8, thereby avoiding the phenomenon that the first comparison unit 22 continues to be affected by the second oscillation acceleration signal VBN after the clock generation circuit has completed oscillation.

[0107] It is understood that the above embodiments are merely exemplary embodiments of the oscillation acceleration module 30 outputting the second oscillation acceleration signal VBN. Those skilled in the art can make equivalent modifications to the oscillation acceleration module 30; for example, the control terminal of the third transistor M3 can be directly connected to the first node m1. For another example, see [reference needed]. Figure 16 , Figure 16 The diagram shows another circuit diagram of the oscillation acceleration module 30 in the embodiment of this application. The oscillation acceleration module 30 may further include a third sub-inverter INC. The input terminal of the third sub-inverter INC is connected to the input terminal of the second sub-inverter INB. The control terminal of the third transistor M3 can be directly connected to the output terminal of the third sub-inverter INC.

[0108] It should be noted that the comparator circuit in current RC oscillators exhibits a delay, therefore the actual period of the clock signal CLK is affected by the delay of the comparator circuit. For example, with... Figure 1For example, considering the actual situation where the comparator delay is taken into account, the sum of the time it takes for capacitor Cx\Cy to charge to the reference voltage Vref and the comparator delay is half a cycle of the clock signal CLK. At this time, the period of the clock signal CLK satisfies the following relationship:

[0109]

[0110] Where td is the comparator delay.

[0111] Therefore, the actual oscillation frequency f of the clock signal CLK is:

[0112]

[0113] As can be seen, the comparator's delay affects the actual oscillation frequency of the clock signal CLK, leading to a decrease in the frequency accuracy of the RC oscillator's output clock signal CLK. To solve this technical problem, please refer to the following:

[0114] Some embodiments of this application are described in the following references. Figure 17 , Figure 17 Another schematic diagram of the clock generation circuit in this application embodiment is shown, wherein the clock generation circuit further includes a charging current control module 40, which is connected to the first charging and discharging unit 21. During a first time period when the first charging and discharging unit 21 is charging, the charging current control module 40 controls the charging current of the first charging and discharging unit 21 to a first preset value; during a second time period when the first charging and discharging unit 21 is charging, the charging current control module 40 controls the charging current of the first charging and discharging unit 21 to a second preset value; wherein the sum of the first time period and the second time period is equal to the charging duration of the first charging and discharging unit 21, the first preset value is equal to twice the second preset value, and the duration corresponding to the first time period is equal to the comparison delay of the first comparison unit 22.

[0115] For example, see Figure 18 , Figure 18 The diagram illustrates a voltage change of the first capacitor C1 and the second capacitor C2 in an embodiment of this application. During the first charging time period, the first capacitor C1 is charged at twice the reference current Iref, and during the second charging time period, the first capacitor C1 is charged at once the reference current Iref. Similarly, during the first charging time period, the second capacitor C2 is charged at twice the reference current Iref, and during the second charging time period, the second capacitor C2 is charged at once the reference current Iref.

[0116] Since the sum of the first time period and the second time period is equal to the charging time of the first charging / discharging unit 21 (e.g., the charging time of the first capacitor C1 or the charging time of the second capacitor C2), and the corresponding duration of the first time period is equal to the comparison delay of the first comparison unit 22, it can be known that the charging of the first capacitor C1 and the second capacitor C2 to the first reference voltage VCH satisfies the following relationship:

[0117]

[0118] Where C is the capacitance value of the first capacitor C1 and the second capacitor C2, td is the comparison delay of the first comparison unit 22 (i.e., the duration corresponding to the first time period), Tch is the charging duration of the first charging and discharging unit 21, and Tch-td is the duration corresponding to the second time period.

[0119] Based on the above relationship, it can be seen that the charging time of the first charging and discharging unit 21 satisfies the following relationship:

[0120] Tch=R1*C-td

[0121] Since the first charging / discharging unit 21 charges once and the first comparison unit 22 compares the voltage once, which is half a cycle of the clock signal CLK, the period of the clock signal CLK satisfies the following relationship:

[0122] T = 2 * Tch + 2 * td

[0123] T = 2 * R1 * C - 2 * td + 2 * td

[0124] T = 2 * R1 * C

[0125] As can be seen, by controlling the charging current of the first capacitor C1 and the second capacitor C2 through the charging current control module 40, the period of the clock signal CLK output by the clock generation circuit can be independent of the delay of the first comparison unit 22, which ultimately helps to solve the problem of the frequency accuracy of the clock signal CLK being reduced due to the delay of the comparator.

[0126] As an exemplary embodiment, see [reference] Figure 19 , Figure 19 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the first terminal of the first PMOS transistor MP1 and the first terminal of the second PMOS transistor MP2 are connected to each other in the first charging and discharging unit 21, and a switch S0 is provided between the second PMOS transistor MP2 and the reference current Iref. The charging current control module 40 can output a switch control signal Sn to control the switch S0, thereby changing the charging current of the first capacitor C1 and the second capacitor C2.

[0127] For example, when the second PMOS transistor MP2 is turned on, the switch S0 is closed, and the first PMOS transistor MP1 is turned off, the second capacitor C2 is charged with twice the reference current Iref; when the second PMOS transistor MP2 is turned on, the first PMOS transistor MP1 is turned off, and the switch S0 is open, the second capacitor C2 is charged with one reference current Iref. When the first PMOS transistor MP1 is turned on, the switch S0 is closed, and the second PMOS transistor MP2 is turned off, the second capacitor C2 is charged with twice the reference current Iref; when the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned off, and the switch S0 is open, the first capacitor C1 is charged with one reference current Iref.

[0128] In some embodiments of this application, see Figure 20 , Figure 20 A circuit diagram of a charging current control module 40 in an embodiment of this application is shown, wherein the charging current control module 40 includes a second charging and discharging unit 41, a second comparison unit 42, and a second logic unit 43.

[0129] The second charging / discharging unit 41 includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 are controlled by a first switching signal S1, the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 are controlled by a second switching signal S2, the eleventh PMOS transistor MP11 is controlled by a second control signal Q1B, and the twelfth PMOS transistor MP12 is controlled by a first control signal Q1.

[0130] The second comparison unit 42 can compare the voltage VC5 of the fifth capacitor C5 with the first reference voltage VCH, and the voltage VC6 of the fifth capacitor C5 with the first reference voltage VCH, and output a third comparison signal VP3 and a fourth comparison signal VP4. Understandably, the second comparison unit 42 can employ methods such as... Figure 5 The two comparators shown are used to compare the voltage VC5 of the fifth capacitor with the first reference voltage VCH, and the voltage VC6 of the fifth capacitor C5 with the first reference voltage VCH, respectively; or, the second comparison unit 42 can also adopt the following... Figure 14 The circuit structure shown is not described in detail here.

[0131] The second logic unit 43 can output a third control signal Q2 and a fourth control signal Q2B according to the third comparison signal VP3 and the fourth comparison signal VP4, and can output a first switch signal S1, a second switch signal S2 and a switch control signal Sn according to the first control signal Q1, the second control signal Q1B, the third control signal Q2 and the fourth control signal Q2B, so as to realize feedback control of the second charging and discharging unit 41 through the first switch signal S1 and the second switch signal S2.

[0132] The second logic unit 43 includes an RS latch circuit composed of a seventh inverter IN7, an eighth inverter IN8, a ninth inverter IN9, a tenth inverter IN10, an eleventh inverter IN11, a twelfth inverter IN12, a third NAND gate NAND3, and a fourth NAND gate NAND4. The RS latch circuit can output a third control signal Q2 and a fourth control signal Q2B with opposite levels. The first control signal Q1 and the second control signal Q1B can output a first switch signal S1 through a fifth NAND gate NAND5. The third control signal Q2 and the fourth control signal Q2B can output a second switch signal S2 through a sixth NAND gate NAND6. The first switch signal S1 and the second switch signal S2 can output a switch control signal Sn through a thirteenth inverter IN13, a fourteenth inverter IN14, and a NOR gate NOR.

[0133] Specifically, see Figure 21 , Figure 21 This application illustrates a timing diagram of a related signal in an embodiment of the present application. Figure 21 In the diagram, VC3 is the voltage of the third capacitor C3, VC4 is the voltage of the fourth capacitor C4, VC5 is the voltage of the fifth capacitor C5, and VC6 is the voltage of the sixth capacitor C6.

[0134] Assuming the initial state is as follows: the first control signal Q1 is low, the second control signal Q1B is high, the third control signal Q2 is low, and the fourth control signal Q2B is high, then the first switch signal S1 is high, the second switch signal S2 is high, the switch control signal Sn is high, the twelfth PMOS transistor MP12 and the tenth NMOS transistor MN10 are turned on, and the voltage VC6 of the sixth capacitor C6 is clamped to the second reference voltage VCL.

[0135] When the first control signal Q1 changes to a high level and the second control signal Q1B changes to a low level, the first switch signal S1 is low, the second switch signal S2 is high, and the switch control signal Sn is low. Therefore... Figure 19 When switch S0 is closed and the first PMOS transistor MP1 is turned on, the first capacitor C1 is charged with twice the reference current Iref; simultaneously... Figure 20The twelfth PMOS transistor MP12 is cut off, the tenth PMOS transistor MP10 is turned on, and the tenth NMOS transistor MN10 is cut off. The fourth capacitor C4 is charged, and the voltage VC4 of the fourth capacitor C4 gradually increases. According to the law of conservation of charge, the voltage VC6 of the sixth capacitor C6 starts to rise from the second reference voltage VCL.

[0136] When the voltage VC6 of the sixth capacitor C6 rises to the first reference voltage VCH, the fourth comparison signal VP4 in the second comparison unit 42 changes to a low level. Therefore, the third control signal Q2 changes to a high level, the fourth control signal Q2B changes to a low level, the first switch signal S1 changes to a high level, the second switch signal S2 changes to a high level, and the switch control signal Sn changes to a high level. Figure 19 When the switch S0 is turned off, the first PMOS transistor MP1 remains on, and the first capacitor C1 is charged with a current equal to the reference current Iref.

[0137] When the voltage of the first capacitor C1 rises to the first reference voltage VCH, the first control signal Q1 changes back to low level, and the second control signal Q1B changes back to high level, completing the charging process of the first capacitor C1 (i.e., half a cycle of the clock signal CLK). The charging process of the second capacitor C2 is similar, and will not be described in detail here.

[0138] It can be seen that during the period when the voltage of the sixth capacitor C6 or the fifth capacitor C5 rises from the second reference voltage VCL to the first reference voltage VCH, the switch control signal Sn is at a low level. Therefore, the switch control signal Sn can control... Figure 19 When the switch S0 is closed, the first capacitor C1 and the second capacitor C2 are charged at twice the reference current Iref.

[0139] This application also provides a chip that includes the clock generation circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the clock generation circuit described in the above embodiments, it has all the beneficial effects of the clock generation circuit in the above embodiments, and will not be repeated here.

[0140] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A clock generation circuit, characterized by comprising: include: A reference module used to generate a reference current based on a reference voltage; An RC oscillation module is connected to the reference module to oscillate according to the reference current and output a clock signal; An oscillation acceleration module is connected to the reference module to input a first oscillation acceleration signal to the reference module when the clock generation circuit starts oscillating. The first oscillation acceleration signal is used to control the reference module to accelerate the generation of the reference current when the clock generation circuit starts oscillating.

2. The clock generation circuit of claim 1, wherein, The vibration acceleration module controls the output of the first vibration acceleration signal in response to the magnitude of the reference current. When the reference current is less than a preset threshold, the oscillation acceleration module inputs a first oscillation acceleration signal to the reference module. When the reference current is greater than or equal to a preset threshold, the oscillation acceleration module stops inputting the first oscillation acceleration signal to the reference module.

3. The clock generation circuit of claim 2, wherein, The reference module includes an operational amplifier, a first transistor, and a first resistor; The first terminal of the first transistor is connected to the power supply terminal, the second terminal of the first transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the ground terminal. The first input terminal of the operational amplifier is connected to the reference voltage, the second input terminal of the operational amplifier is connected to the first node between the first transistor and the first resistor, and the output terminal of the operational amplifier is connected to the control terminal of the first transistor. The input terminal of the oscillation acceleration module is connected to the first node, and the output terminal of the oscillation acceleration module is connected to the control terminal of the first transistor. The first oscillation acceleration signal is used to pull down the control terminal voltage of the first transistor when the clock generation circuit starts oscillating.

4. The clock generating circuit as described in claim 3, characterized in that, The oscillation acceleration module includes a second transistor and a first bias current source; The second terminal of the second transistor is connected to the control terminal of the first transistor, the first terminal of the second transistor is connected to the first terminal of the first bias current source, and the second terminal of the first bias current source is connected to the ground terminal. Specifically, when the reference current is less than a preset threshold, the second transistor is in the on state; when the reference current is greater than or equal to the preset threshold, the second transistor is in the off state.

5. The clock generation circuit of claim 4, wherein, The oscillation acceleration module also includes a second bias current source, a fourth transistor, a first sub-inverter, and a second sub-inverter; The first terminal of the second bias current source is connected to the power supply terminal, the second terminal of the second bias current source is connected to the second terminal of the fourth transistor, and the first terminal of the fourth transistor is connected to the ground terminal. The input terminal of the first sub-inverter is connected to the second terminal of the fourth transistor, the output terminal of the first sub-inverter is connected to the input terminal of the second sub-inverter, and the output terminal of the second sub-inverter is connected to the control terminal of the second transistor.

6. The clock generation circuit of claim 5, wherein, The vibration acceleration module also includes a clamping unit; The clamping unit is connected to the input terminal of the first sub-inverter, the clamping unit is connected to the input terminal of the second sub-inverter, and the clamping unit is connected to the output terminal of the second sub-inverter. Specifically, the clamping unit clamps the input terminal of the first sub-inverter to be at a level opposite to the output terminal of the first sub-inverter, and the input terminal of the second sub-inverter to be at a level opposite to the output terminal of the second sub-inverter.

7. The clock generation circuit of claim 6, wherein, The clamping unit includes a first sub-PMOS transistor, a second sub-PMOS transistor, a first sub-NMOS transistor, and a second sub-NMOS transistor; The first terminal of the first sub-PMOS transistor is connected to the power supply terminal, the second terminal of the first sub-PMOS transistor is connected to the first terminal of the second sub-PMOS transistor, and the control terminal of the first sub-PMOS transistor is connected to the output terminal of the second sub-inverter. The second terminal of the second sub-PMOS transistor is connected to the second terminal of the first sub-NMOS transistor, the control terminal of the second sub-PMOS transistor is connected to the input terminal of the first sub-inverter, and the second terminal of the second sub-PMOS transistor is connected to the output terminal of the first sub-inverter. The first terminal of the first sub-NMOS transistor is connected to the second terminal of the second sub-NMOS transistor, and the control terminal of the first sub-NMOS transistor is connected to the input terminal of the first sub-inverter. The first terminal of the second sub-NMOS transistor is connected to the ground terminal, and the control terminal of the second sub-NMOS transistor is connected to the output terminal of the second sub-inverter.

8. The clock generation circuit of claim 1, wherein, The RC oscillation module includes a first charging and discharging unit, a first comparison unit, and a first logic unit; The first charging and discharging unit charges based on the reference current and outputs a periodically varying charging and discharging voltage signal; The first comparison unit is connected to the first charge / discharge unit and the first comparison unit is connected to the reference module to compare the magnitude of the charge / discharge voltage signal with the first reference voltage and output a comparison signal. The first logic unit is connected to the first comparison unit and the first charging / discharging unit, so as to input a control signal to the first charging / discharging unit according to the comparison signal; The oscillation acceleration module is also connected to the first comparison unit to input a second oscillation acceleration signal to the first comparison unit when the clock generation circuit starts oscillating. The second oscillation acceleration signal is used to control the first comparison unit to accelerate its start-up when the clock generation circuit starts oscillating.

9. The clock generation circuit of claim 8, wherein, The oscillation acceleration module includes a third transistor and a second bias current source; The first terminal of the second bias current source is connected to the power supply terminal, the second terminal of the second bias current source is connected to the first terminal of the third transistor, and the second terminal of the third transistor is connected to the first comparator unit. Specifically, when the reference current is less than a preset threshold, the third transistor is in the on state; when the reference current is greater than or equal to the preset threshold, the third transistor is in the off state.

10. The clock generation circuit of claim 8, wherein, The charge / discharge voltage signal includes a first charge / discharge signal and a second charge / discharge signal; The first comparison unit includes a bias current source, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The first terminal of the third PMOS transistor is connected to the power supply terminal, the control terminal of the third PMOS transistor is connected to the second terminal of the third PMOS transistor, and the second terminal of the third PMOS transistor is connected to the second terminal of the third NMOS transistor. The first terminal of the third NMOS transistor is connected to the first terminal of the bias current source, the second terminal of the bias current source is connected to the ground terminal, and the control terminal of the third NMOS transistor is connected to the first charging and discharging signal. The first terminal of the fourth PMOS transistor is connected to the power supply terminal, the control terminal of the fourth PMOS transistor is connected to the second terminal of the fourth PMOS transistor, and the second terminal of the fourth PMOS transistor is connected to the second terminal of the fourth NMOS transistor. The first terminal of the fourth NMOS transistor is connected to the first terminal of the bias current source, and the control terminal of the fourth NMOS transistor is connected to the second charge / discharge signal. The first terminal of the fifth PMOS transistor is connected to the power supply terminal, the control terminal of the fifth PMOS transistor is connected to the second terminal of the fifth PMOS transistor, and the second terminal of the fifth PMOS transistor is connected to the second terminal of the fifth NMOS transistor. The first terminal of the fifth NMOS transistor is connected to the first terminal of the bias current source, and the control terminal of the fifth NMOS transistor is connected to the first reference voltage. The first terminal of the sixth PMOS transistor is connected to the power supply terminal, the control terminal of the sixth PMOS transistor is connected to the control terminal of the fifth PMOS transistor, and the second terminal of the sixth PMOS transistor is connected to the second terminal of the sixth NMOS transistor. The control terminal of the sixth NMOS transistor is connected to the second terminal of the sixth NMOS transistor, and the second terminal of the sixth NMOS transistor is connected to the ground terminal; The first terminal of the seventh PMOS transistor is connected to the power supply terminal, the control terminal of the seventh PMOS transistor is connected to the control terminal of the third PMOS transistor, and the second terminal of the seventh PMOS transistor is connected to the second terminal of the seventh NMOS transistor. The control terminal of the seventh NMOS transistor is connected to the control terminal of the sixth NMOS transistor, and the second terminal of the seventh NMOS transistor is connected to the ground terminal; The first terminal of the eighth PMOS transistor is connected to the power supply terminal, the control terminal of the eighth PMOS transistor is connected to the control terminal of the fourth PMOS transistor, and the second terminal of the eighth PMOS transistor is connected to the second terminal of the eighth NMOS transistor. The control terminal of the eighth NMOS transistor is connected to the control terminal of the sixth NMOS transistor, and the second terminal of the eighth NMOS transistor is connected to the ground terminal.

11. The clock generation circuit of claim 8, wherein, The clock generation circuit also includes a charging current control module; During a first time period while the first charging and discharging unit is charging, the charging current control module controls the charging current of the first charging and discharging unit to a first preset value. During the second time period when the first charging and discharging unit is charging, the charging current control module controls the charging current of the first charging and discharging unit to a second preset value. Wherein, the sum of the first time period and the second time period is equal to the charging duration of the first charging and discharging unit, the first preset value is equal to twice the second preset value, and the duration corresponding to the first time period is equal to the comparison delay of the first comparison unit.

12. A chip, characterized by Includes the clock generation circuit as described in any one of claims 1 to 11.

13. An electronic device, comprising: It includes a device body and a chip as described in claim 12 disposed on the device body.

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