Semiconductor device

Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes a channel over a substrate; a gate over the channel and interposed between the source / drain regions; an etch stop layer around sidewalls of the gate and over the substrate and the source / drain region; and an interlayer dielectric over the etch stop layer. The interlayer dielectric includes a liner and a primary dielectric over the liner. The primary dielectric includes a carbon-containing lower portion and a carbon-containing upper portion.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] In one or more embodiments disclosed herein, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion.

[0005] In one or more embodiments disclosed herein, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a nitrogen-containing liner.

[0006] In one or more embodiments disclosed herein, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a carbon-containing liner. Attached Figure Description

[0007] The state revealed here is in conjunction with the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 The illustration shows an example of a nanostructure field-effect transistor (nano-FET) in three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B ,and Figure 21C A cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments;

[0010] Figure 22A , Figure 22B ,and Figure 22C This is a cross-sectional view of a nano-FET according to some embodiments.

[0011] [Symbol Explanation]

[0012] 20: Divider

[0013] 50:Substrate

[0014] 50A: Zone 1

[0015] 50B: Second District

[0016] 51A, 51B, 51C: First semiconductor layer

[0017] 52A, 52B, 52C: First Nanostructures

[0018] 53A, 53B, 53C: Second semiconductor layer

[0019] 54A, 54B, 54C: Second nanostructures

[0020] 55: Nanostructures

[0021] 64: Multi-layer stacking

[0022] 66: Fins

[0023] 68: STI Zone

[0024] 70: Dummy Dielectric Layer

[0025] 71: Dummy gate dielectric

[0026] 72: Dummy gate layer

[0027] 74: Masking layer

[0028] 76: Dummy gate

[0029] 76A: First Dummy Gate / Dummy Gate

[0030] 76B: Second Dummy Gate / Dummy Gate

[0031] 78: Mask

[0032] 80: First Spacing Layer

[0033] 81: First spacer

[0034] 82: Second spacer layer

[0035] 83: Second spacer

[0036] 86: First Groove

[0037] 88: Sidewall Groove

[0038] 90: First internal spacer

[0039] 92: Epitaxial Source / Drain Region

[0040] 92A: First epitaxial source / drain region

[0041] 92B: Second epitaxial source / drain region

[0042] 931: First semiconductor material layer

[0043] 932: Second semiconductor material layer

[0044] 933: Third semiconductor material layer

[0045] 94:CESL

[0046] 96: First ILD

[0047] 98: Lining

[0048] 100: Main dielectric

[0049] 100A: Primary Dielectric

[0050] 100B: Second main dielectric

[0051] 102: Second groove

[0052] 104: Gate dielectric layer

[0053] 106: Gate electrode

[0054] 108: Gate Mask

[0055] 110: Second ILD

[0056] 112: Third groove

[0057] 114: Silicide Region

[0058] 116: Contact / Source / Drain Contact

[0059] 118: Contact / Gate Contact

[0060] T: Thickness

[0061] P1: First pitch

[0062] P2: Second pitch

[0063] P3: Third pitch

[0064] P4: Fourth pitch Detailed Implementation

[0065] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0066] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0067] As discussed in more detail below, the embodiments disclosed herein describe transistors having an interlayer dielectric around the gate electrode, wherein the interlayer dielectric exhibits good film quality despite being cured by a low-temperature annealing process. The techniques described herein involve forming a carbon-containing liner prior to the main dielectric to form the interlayer dielectric layer, allowing carbon in the liner to diffuse into the main dielectric, thereby improving the film quality of the interlayer dielectric. Embodiments are described below in a specific context, namely, a die incorporating a nano-FET. However, various embodiments can be applied to dies incorporating other types of transistors, such as FinFETs, planar transistors, or the like, instead of or in combination with nano-FETs.

[0068] Figure 1The illustration shows an example of a nano-FET in a three-dimensional view according to some embodiments. The nano-FET includes a nanostructure 55 (e.g., a nanosheet or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region for the nano-FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent isolation regions 68. Although the isolation regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of the fins 66 is illustrated as a single continuous material with respect to the substrate 50, the bottom portion of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fins 66 refer to the portion extending between adjacent isolation regions 68.

[0069] The gate dielectric layer 104 is above the top surface of the fin 66 and extends along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 106 is above the gate dielectric layer 104. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite sides of the gate dielectric layer 104 and the gate electrode 106.

[0070] Figure 1 Further illustrations are provided for the reference cross sections used in the following figures. Cross section A-A' is along the longitudinal axis of the gate electrode 106 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nano-FET, and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nano-FET. For clarity, the following figures refer to these reference cross sections.

[0071] Some embodiments described herein are discussed in the context of nano-FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Additionally, some embodiments are envisioned for use in planar devices such as planar FETs or in fin field-effect transistors (FinFETs).

[0072] Figures 2 to 22C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A ,and Figure 22A Illustration Figure 1 The reference cross section A-A' is shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B ,and Figure 22B Illustration Figure 1 The reference cross section B-B' is shown in the figure. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 19C , Figure 20C , Figure 21C ,and Figure 22C Illustration Figure 1 The reference cross section C-C' shown is illustrated.

[0073] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphate, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof.

[0074] The substrate 50 has a first region 50A and a second region 50B. The first region 50A may be a region for forming a plurality of transistors having a first density. The second region 50B may be a region for forming a plurality of transistors having a second density less than the first density. For example, the first region 50A may be a region for forming a static random array memory (SRAM) device or a logic device. The second region 50B may be a region for forming a logic device or an input / output (I / O) device. In some embodiments, the first region 50A and the second region 50B are regions for forming NMOS transistors (e.g., n-type nano-FETs). Alternatively, the first region 50A and the second region 50B are regions for forming PMOS transistors (e.g., p-type nano-FETs). The first region 50A may be physically separated from the second region 50B (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the first regions 50A and 50B. Although the illustration shows one first zone 50A and one second zone 50B, any number of first zones 50A and second zones 50B can be provided and can be configured in any manner.

[0075] Further in Figure 2 In this process, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form channel regions for nano-FETs in both the first region 50A and the second region 50B. In some embodiments, such as in Figure 22A , Figure 22B ,and Figure 22C In the illustrated embodiment, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form channel regions for a nano-FET in both the first region 50A and the second region 50B. In such embodiments described above, the channel regions in the first region 50A and the second region 50B may have the same material composition (e.g., silicon, silicon-carbon, silicon-germanium, or another semiconductor material) and may be formed simultaneously.

[0076] In other embodiments (not shown in the figures), the second semiconductor layer 53 in the second region 50B can be removed, and the first semiconductor layer 51 in the second region 50B can be patterned to form a channel region for a nano-FET in the second region 50B. Alternatively, the first semiconductor layer 51 in the first region 50A can be removed, and the second semiconductor layer 53 can be patterned to form a channel region for a nano-FET in the first region 50A. However, still in other embodiments (not shown in the figures), the first semiconductor layer 51 in the second region 50B can be removed, and the second semiconductor layer 53 in the second region 50B can be patterned to form a channel region for a nano-FET in the second region 50B; the second semiconductor layer 53 in the first region 50A can be removed, and the first semiconductor layer 51 in the first region 50A can be patterned to form a channel region for a nano-FET in the first region 50A.

[0077] For illustrative purposes, the multilayer stack 64 is illustrated as three layers including each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods.

[0078] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. Thus, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nano-FET. Alternatively, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nano-FET. In various embodiments, the first semiconductor layer 51 or the second semiconductor layer 53 used to form the channel region can be formed from a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, or the like. Alternatively, the first semiconductor layer 51 or the second semiconductor layer 53 forming the channel region can be formed from a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbide, or the like.

[0079] Now for reference Figure 3According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. Nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0080] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0081] For illustrative purposes, Figure 3 The fins 66 in the first region 50A and the second region 50B are illustrated as having substantially equal widths. In some embodiments, the width of the fins 66 in the first region 50A is greater than or less than the width of the fins 66 in the second region 50B. Furthermore, although the fins 66 and the nanostructures 55 are illustrated as always having a consistent width, in other embodiments, the fins 66 or nanostructures 55 may have tapered sidewalls, such that the width of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, the nanostructures 55 may have different widths and be trapezoidal in shape.

[0082] exist Figure 4In the substrate 50, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, nitride, or similar compound of silicon oxide, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one or more embodiments, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a substrate (not shown separately) may first be formed along the surfaces of the substrate 50, fin 66, and nanostructure 55. Subsequently, a filler material, such as the filler material described above, can be formed on top of the lining.

[0083] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, or similar methods may be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the nanostructure 55 is flush with the top surface of the insulating material.

[0084] Next, the insulating material is recessed to form STI regions 68. The recessed insulating material causes the upper portions of the fins 66 in the first region 50A and the second region 50B to protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes, such as those selective for the insulating material (e.g., etching the insulating material at a faster rate than etching the material of the fins 66 and the nanostructure 55), can be used to recess the STI region 68. For example, an oxide of dilute hydrofluoric acid (dHF) can be used for removal.

[0085] The above is about Figures 2 to 4The described process is only one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may comprise the aforementioned alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structures, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0086] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are illustrated and discussed herein as containing the same material in the second region 50B and the first region 50A. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials, or may be formed in different orders in the second region 50B and the first region 50A.

[0087] Further in Figure 4 Suitable wells (not shown separately) can be formed in the fin 66, nanostructure 55, and / or STI region 68. For example, when the first region 50A and the second region 50B are regions for forming an n-type nano-FET, the wells in the first region 50A and the second region 50B may include p-type wells. Alternatively, when the first region 50A and the second region 50B are regions for forming a p-type nano-FET, the wells in the first region 50A and the second region 50B may include n-type wells. The p-type wells may be implanted with p-type impurities, such as boron, boron fluoride, indium, or the like, at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. Type n wells can be implanted with type n impurities, such as phosphorus, arsenic, antimony, or similar substances, at concentrations of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range.

[0088] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The masking layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the first region 50A and the second region 50B. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, thereby extending the dummy dielectric layer 70 between the dummy gate layer 72 and the STI region 68.

[0089] Figures 6A to 21C The illustration shows various additional steps in the manufacturing process of the embodiment. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13A , Figure 13C , Figure 14A , Figure 14C , Figure 14D , Figure 15A , Figure 16A , Figure 19C , Figure 20C ,and Figure 21C The illustration shows the features in either zone 50A or zone 50B. Figure 6A (along such as) Figure 1 The cross section A-A' shown in the figure and Figure 6B In this process, acceptable lithography and etching techniques can be used to treat the mask layer 74 (see...). Figure 5The pattern is then patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers individual channel regions of the fin 66. The first and second dummy gates 76A and 76B may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the individual fin 66. The first dummy gate 76A and the second dummy gate 76B may be along... Figure 1 The sections shown are separated in the direction of A-A', or they can be solidly connected in this direction. Therefore, Figure 6A Or display with Figure 6A The dummy gate 76 shown in the figures of the same orientation can be a first dummy gate 76A, a second dummy gate 76B, or a combination of the first dummy gate 76A and the second dummy gate 76B. For example... Figure 6B As shown, two adjacent first dummy gates 76A in the first region 50A may have a first pitch P1, and two adjacent second dummy gates 76B in the second region 50B may have a second pitch P2 smaller than the first pitch P1. In some embodiments, the first pitch P1 is approximately 47 nm to 53 nm. The second pitch P2 is approximately 188 nm to 195 nm. The first dummy gates 76A in the first region 50A may have substantially the same length and / or width as the second dummy gates 76B in the second region 50B.

[0090] exist Figure 7A (along) Figure 1 The cross section C-C' shown in the figure and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and can be deposited by CVD, ALD, or the like.

[0091] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. An appropriate type (e.g., p-type or n-type) of impurity can be implanted into the exposed fins 66 and nanostructures 55 in the first region 50A and the second region 50B. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. The lightly doped source / drain region can have a depth of approximately 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 Impurity concentration within a specified range. Annealing can be used to repair implant damage and revitalize implanted impurities.

[0092] exist Figure 8A and Figure 8B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or the like. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 acts as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as... Figure 8A As shown in the diagram. Subsequently, the second spacer 83 acts as a mask during the etching of the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown. Figure 8A As shown in the image.

[0093] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, the first and second dummy gates 76A and 76B, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the first and second dummy gates 76A and 76B, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, the first and second dummy gates 76A and 76B, and the dummy gate dielectric 71.

[0094] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0095] exist Figure 9A and Figure 9B In some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions are then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed below the top surface of the STI region 68; and so on. The first groove 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50 during the etching process for forming the first groove 86. A single etching process or multiple etching processes may be used to etch each layer of the nanostructure 55 and / or the fin 66. A timed etching process may be used to terminate the etching of the first groove 86 after the first groove 86 has reached the desired depth.

[0096] exist Figure 10A and Figure 10B In this process, a portion of the sidewall of a layer (e.g., a first nanostructure 52) in a multilayer stack 64 formed from a first semiconductor material exposed by the first groove 86 is etched to form a sidewall groove 88. Although in Figure 10BIn the illustration, the sidewalls of the first nanostructure 52 in the groove 88 are shown as straight, but the sidewalls can be concave or convex. The sidewalls can be etched using isotropic etching processes such as wet etching or similar methods. When the first nanostructure 52 is etched using an etchant selective for the first semiconductor material, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, when the second nanostructure 54 is etched using an etchant selective for the second semiconductor material, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 or the second nanostructure 54 comprises, for example, SiGe, the sidewalls of the first nanostructure 52 or the second nanostructure 54 can be etched using a dry etching process having tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In embodiments where the first nanostructure 52 or the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 or the second nanostructure 54 can be etched using a wet or dry etching process having hydrogen fluoride, another fluorine-based etchant, or the like.

[0097] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in the sidewall groove 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited over the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in a first recess 86, and the first nanostructure 52 will be replaced by the corresponding gate structure.

[0098] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, or similar methods. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as low-k materials having a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer wall of the first internal spacer 90 is illustrated to be flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54.

[0099] Furthermore, despite Figure 11B The outer wall of the first internal spacer 90 is shown as straight, but the outer wall of the first internal spacer 90 can also be concave or convex. As an example, Figure 11CThe illustration shows an embodiment where the sidewalls of the first nanostructure 52 are concave, and the outer sidewalls of the first internal spacer 90 are also concave. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, or similar methods. The first internal spacer 90 can be used to prevent subsequent etching processes, such as those used to form the gate structure, from affecting the subsequently formed source / drain regions (such as those described below). Figures 12A to 12C Damage to the epitaxial source / channel region 92.

[0100] exist Figures 12A to 12C In the first groove 86, a first epitaxial source / drain region 92A and a second epitaxial source / drain region 92B (collectively referred to as epitaxial source / drain region 92) are formed. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving the performance of the nano-FET. Figure 12B As shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76A or 76B is inserted between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76A or 76B, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nano-FET.

[0101] The epitaxial source / drain region 92 may include any acceptable material suitable for use in an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile stress to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface protruding from an individual upper surface in the nanostructure 55 and may have a facet. Alternatively, the epitaxial source / drain region 92 may also include any acceptable material suitable for use in a p-type nano-FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 may include a material that applies compressive stress to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 may also have a surface protruding from an individual surface in the multilayer stack 64 and may have a facet.

[0102] Epitaxial source / drain regions 92, first nanostructures 52, second nanostructures 54, and / or substrate 50 may be implanted with dopants to form source / drain regions, similar to the previously described process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density of approximately 1 x 10⁻⁶. 19 atoms / cm 3 With approximately 1x1021 atoms / cm 3 The impurity concentrations between [specific parameters]. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0103] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the first region 50A and the second region 50B, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 in the same nano-FET to merge, such as... Figure 12A As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 12C As shown. In Figure 12A and Figure 12C In the illustrated embodiment, a first spacer 81 may be formed to the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0104] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 931, a second semiconductor material layer 932, and a third semiconductor material layer 933. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 931, the second semiconductor material layer 932, and the third semiconductor material layer 933 may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 931 may have a doping concentration lower than that of the second semiconductor material layer 932 and higher than that of the third semiconductor material layer 933. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 931 may be deposited, the second semiconductor material layer 932 may be deposited over the first semiconductor material layer 931, and the third semiconductor material layer 933 may be deposited over the second semiconductor material layer 932.

[0105] Figure 12D The illustration shows an embodiment where the sidewalls of the first nanostructure 52 in the first region 50A and the second nanostructure 54 in the second region 50B are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the first nanostructure 52. Figure 12DAs shown, the epitaxial source / drain region 92 can be formed in contact with the first internal spacer 90 and can extend through the sidewall of the second nanostructure 54.

[0106] exist Figures 13A to 13C In, respectively in Figure 6A , Figure 12B ,and Figure 12C Commonly deposited contact etch stop layer (CESL) 94 ( Figures 7A to 12D The process will not change. Figure 6A (See the cross-section shown). In some embodiments, according to some examples, a CESL 94 is disposed along the surface of the STI region 68, the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The CESL 94 may be a layer with sufficient thickness to prevent or reduce oxygen diffusion into the channel regions (e.g., nanostructures 54A-C). For example, the CESL 94 may block carbon or oxygen from spreading from the first ILD 96 (see the cross-section shown). Figures 14A to 14C Diffusion. CESL 94 may include a dielectric nitride layer, such as silicon nitride or the like. In some embodiments, CESL 94 has a thickness of about 2 nm to about 5 nm.

[0107] exist Figures 14A to 14C In this process, a first interlayer dielectric (ILD) 96 is formed over a CESL 94. The first ILD 96 includes a liner 98 and a main dielectric 100 above the liner 98. The liner 98 of the first ILD 96 is a thin layer conformally deposited over the CESL 94 prior to the deposition of the main dielectric 100. The liner 98 of the first ILD 96 may be a material including carbon, such as SiC, SiCN, SiOCN, SiOC, or the like. As will be discussed in more detail later, the carbon in the liner 98 may diffuse into the main dielectric 100 and improve the film quality of the main dielectric 100. In some embodiments, the liner 98 of the first ILD 96 also includes at least one element contained in the main dielectric 100 and at least one element contained in the CESL 94. In an illustrative embodiment, the liner 98 may be SiOCN, which includes oxygen contained in the main dielectric 100 and nitrogen contained in the CESL 94. Therefore, the liner 98 of the first ILD 96 has similar characteristics to the main dielectric 100 and CESL 94, thus providing a good interface with the main dielectric 100 and CESL 94, offering fewer dislocations, and increasing adhesion to the main dielectric 100 and CESL 94. In embodiments where the liner 98 is a SiOCN layer, the liner 98 may have suitable thickness and rigidity to facilitate subsequent planarization processes to expose the dummy gate 76 (see...). Figure 15BFor example, liner 98 may have a thickness less than that of CESL 94, such as about 1 nm to about 3 nm. By increasing the oxygen content in liner 98, the stiffness of liner 98 can be reduced.

[0108] Liner 98 can be deposited by suitable methods, such as CVD, ALD, or the like. In some embodiments, ALD includes depositing a silicon-containing precursor and a nitrogen- and carbon-containing precursor. The silicon-containing precursor may include silanes, organosilanes, siloxanes, organosiloxanes, combinations thereof, or the like. The nitrogen- and carbon-containing precursor may include NH2(CH3), NH2(C2H5), NH2(C3H7), NH(CH3)2, NH(C2H5)2, N(C2H5)3, N(CH3)3, combinations thereof, or the like. Subsequently, the deposited precursor may be oxidized by H2O, O2, or other suitable oxidants.

[0109] According to some embodiments, the main dielectric 100 includes a first main dielectric 100A in a first region 50A and a second main dielectric 100B in a second region 50B. The main dielectric 100 may include a silicon oxide material deposited by flowable CVD (FCVD) or the like, although other suitable materials may also be used for the main dielectric 100. For example, a flowable dielectric may be deposited over a liner 98, including in high aspect ratio trenches between adjacent first dummy gates 76A and adjacent second dummy gates 76B. The flowable dielectric may be carbon-free silicon oxide. In illustrative embodiments, the process for forming the flowable dielectric may include reacting a silicon-containing precursor with an oxygen-containing precursor to form a flowable silicon oxide film at low temperatures (e.g., below about 100 degrees Celsius). Suitable silicon-containing precursors for forming a flowable dielectric may include carbon-free silanes, including aminosilanes such as trisilanes, heteroazosilanes, combinations thereof, or the like; or halogenated silanes (such as tetrachlorosilanes, tetrabromosilanes), combinations thereof, or the like. Suitable oxygen-containing precursors for forming a flowable dielectric may include O2, O3, NO, NO2, N2O, H2O, H2O2, combinations thereof, or the like.

[0110] Next, an annealing process can be performed to solidify the flowable dielectric and form the main dielectric 100 as it is deposited and flows into a high aspect ratio trench. The annealing process may include at least two stages. For example, the first stage of the annealing process may introduce H2O vapor or other oxygen-containing gas to oxidize residual Si dangling bonds, and when the main dielectric 100 is formed from a precursor such as an aminosilane, Si-N-Si bonds may be replaced with Si-O-Si bonds. The second stage of annealing may include introducing N2 or other nitrogen-containing gas to convert the Si-OH bonds of the main dielectric 100 to Si-O-Si bonds by dry annealing. The first and second stages of the annealing process can be performed at temperatures between approximately 400°C and approximately 500°C. Experiments have shown that when the annealing temperature of the annealing process is below approximately 500°C, it effectively reduces the deactivation of active dopants in the epitaxial source / drain regions 92. Such dopant deactivation can impair the electrical performance of the nano-FET.

[0111] During the annealing process, carbon in the liner 98 diffuses into the main dielectric 100. Effective carbon diffusion from the liner 98 to the main dielectric 100 can occur when the annealing temperature is above approximately 400 degrees Celsius. Carbon diffusion into the main dielectric 100 can improve the film quality of the main dielectric 100, such as enhancing its performance in subsequent processes (e.g., ...). Figures 15A to 18B Resistance to cleaning agents or etchants in the gate replacement process described herein. Thus, in some embodiments where the main dielectric 100 has degraded film quality due to insufficient curing in a low-temperature annealing process (e.g., below about 500 degrees Celsius), carbon diffusion into the main dielectric 100 can improve the film quality of the main dielectric 100, thereby solving the film quality degradation problem caused by the low-temperature annealing process.

[0112] In some embodiments, the first carbon concentration of the first main dielectric 100A gradually decreases from the bottom of the first main dielectric 100A toward the top of the first main dielectric 100A, and the second carbon concentration of the second main dielectric 100B gradually decreases from the bottom of the second main dielectric 100B toward the top of the second main dielectric 100B. For example, the peak carbon concentration in the first main dielectric 100A or the peak carbon concentration in the second main dielectric 100B is at a depth near the liner 98, or at the bottom of the first main dielectric 100A or the second main dielectric 100B.

[0113] In some embodiments where the liner 98 is a SiOCN layer, after the annealing process, the atomic ratio of carbon to silicon in the liner 98 may decrease from between about 1 and about 12 to between about 0.1 and about 0.2, while the atomic ratio of oxygen to silicon in the liner 98 may remain between about 2 and about 2.6, and the atomic ratio of nitrogen to silicon in the liner may remain between about 0.23 and about 0.36. In some embodiments, the average atomic ratio of carbon to silicon in the primary dielectric 100 in the first region 50A or the second region 50B is less than about 0.1. The primary dielectric 100 may also include nitrogen, which may be derived from nitrogen-containing gas from the annealing process, or residues of precursors, such as an average atomic ratio of nitrogen to silicon of less than about 0.1. In some embodiments, the atomic ratio of oxygen to silicon in the primary dielectric 100 is between about 1.85 and about 2.1. In some embodiments, the liner 98 has a nitrogen concentration greater than the nitrogen concentration of the primary dielectric 100. In some embodiments, the lining 98 has an oxygen concentration greater than that of the main dielectric 100.

[0114] In some embodiments, the annealing process provides the same thermal budget for the first region 50A and the second region 50B, but it has been found that the film quality in the first main dielectric 100A in the first region 50A can degrade more than the film quality in the second main dielectric 100B in the second region 50B. This may be due to the high transistor density in the first region 50A. This film degradation problem in the nano-FET in the first region 50A may be more severe than in the nano-FET in the second region 50B. This is because the adjacent gate contact pitch in the first region 50A (see...) Figure 18A The carbon content is very small, so even minor damage or loss to the first main dielectric 100A can lead to leakage or short circuits between adjacent gate contacts in the first region 50A. As carbon diffuses from the liner 98 into the first main dielectric 100A, the film quality of the first main dielectric 100A can be improved, and film degradation problems can be mitigated or resolved.

[0115] In some embodiments, the annealing process provides different thermal budgets for the first region 50A and the second region 50B. For example, the annealing process provides a lower thermal budget for the first region 50A than for the second region 50B. The first epitaxial source / drain region 92A may be more thermally sensitive than the second epitaxial source / drain region 92B, such as being more susceptible to dopant deactivation, because the volume of the first epitaxial source / drain region 92A between the dummy gates 76A with a close pitch P1 may be smaller than the volume of the second epitaxial source / drain region 92B. A wafer scaffold that provides regional thermal conduction can be used to achieve different thermal budgets for the first region 50A and the second region 50B. The wafer scaffold may include a first region for providing a first temperature to the first region 50A and a second region for providing a second temperature to the second region 50B. In some embodiments, providing a low thermal budget only for the first region 50A can lead to thin-film degradation issues in the first primary dielectric 100A, and due to the pitch of adjacent gate contacts in the first region 50A (see... Figure 18A The problem is very small, and it may be particularly severe for nano-FETs in the first region 50A. As carbon diffuses from the liner 98 into the first main dielectric 100A, the film quality of the first main dielectric 100A can be improved, and the film degradation problem can be mitigated or resolved.

[0116] Figure 14D The illustration shows a comparison of the first carbon concentration of the first main dielectric 100A and the second carbon concentration of the second main dielectric 100B along the thickness T of the main dielectric 100, according to some embodiments, when different thermal budgets are given for the first region 50A and the second region 50B. Figure 14D As shown, compared to the first main dielectric 100A, more carbon can travel a longer distance in the second main dielectric 100B due to the higher thermal budget provided to the liner 98 and the second main dielectric 100B in the second region 50B. In such embodiments, the second main dielectric 100B is at a depth level flush with the top of the second dummy gate 76B (or with...). Figure 18B The second carbon concentration at a depth level flush with the top of the gate electrode 106 in the resulting structure shown can be greater than that at a depth level flush with the top of the first main dielectric 100A (or with the top of the first dummy gate 76A). Figure 18B The first carbon concentration at the depth level flush with the top of the gate electrode 106 in the resulting structure shown.

[0117] Carbon diffusion into the primary dielectric 100 can improve the film quality of the primary dielectric 100 annealed only at low temperatures (e.g., below about 500 degrees Celsius), particularly for the first primary dielectric 100A. In some embodiments, by adding a liner 98 prior to the formation of the primary dielectric 100, the etching rate of the first primary dielectric 100A relative to dilute hydrofluoric acid is improved from 6.5 times faster to 4.8 times faster than the etching rate of the etch-thermal oxide. In some embodiments, by adding a liner 98 prior to the formation of the primary dielectric 100, the etching rate of the second primary dielectric 100B relative to dilute hydrofluoric acid is improved from 5 times faster to 4.2 times faster than the etching rate of the etch-thermal oxide.

[0118] exist Figures 15A to 15B In some embodiments, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the dummy gate 76, the first spacer 81, and the top surface of the first ILD 96 are flush within a range of process variations. Therefore, the top surface of the dummy gate 76 is exposed via the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0119] exist Figure 16A and Figure 16B In one or more etching steps, the dummy gate 76 and the masking layer 74 (if present) are removed to form the second recess 102. A portion of the dummy gate dielectric 71 in the second recess 102 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases to selectively etch the dummy gate 76 at a faster rate than etching the main dielectric 100 or the first spacer 81 of the first ILD 96. Because the film quality of the main dielectric 100 has been improved, the main dielectric 100 may have sufficient resistance to the etching process. Each second recess 102 exposes and / or covers a portion of a nanostructure 55, which serves as a channel region in the subsequently completed nano-FET. The portions of the nanostructure 55 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer when etching the dummy gate 76. Then, after removing the dummy gate 76, the dummy gate dielectric 71 can be removed.

[0120] exist Figure 17A and Figure 17BIn the process, the first nanostructure 52 in the first region 50A and the second region 50B is removed, thereby extending the second groove 102. The first nanostructure 52 can be removed by an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the first nanostructure 52. Compared to the first nanostructure 52, the first nanostructure 54, the substrate 50, the first ILD 96, and the STI region 68 remain relatively unetched. In embodiments where the first nanostructure 52 comprises, for example, SiGe, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 52. In embodiments where the first nanostructure 52 comprises silicon, hydrogen fluoride, another fluorine-based etchant, or the like can be used to remove the first nanostructure 52.

[0121] exist Figure 18A and Figure 18B In the second groove 102, a gate dielectric layer 104 and a gate electrode 106 are formed to replace the gate. The gate dielectric layer 104 is conformally deposited in the second groove 102. The gate dielectric layer 104 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 104 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0122] According to some embodiments, the gate dielectric layer 104 comprises one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may comprise a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 104 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 104 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 104 may be the same or different in the first region 50A and the second region 50B. Methods for forming the gate dielectric layer 104 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0123] Gate electrodes 106 are deposited over the gate dielectric layer 104 and fill the remaining portion of the second groove 102. Gate electrodes 106 may comprise metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although in Figure 18A and Figure 18BThe diagram shows a single-layer gate electrode 106, but the gate electrode 106 may include any number of liner layers, any number of work function tuning layers, and filler material. Any combination of layers constituting the gate electrode 106 may be deposited between adjacent layers in the second nanostructure 54.

[0124] The formation of the gate dielectric layer 104 in the first region 50A and the second region 50B can occur simultaneously, such that the gate dielectric layer 104 in each region is formed of the same material, and the formation of the gate electrode 106 can occur simultaneously, such that the gate electrode 106 in each region is formed of the same material. In some embodiments, the gate dielectric layer 104 in each region can be formed by different processes, such that the gate dielectric layer 104 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 106 in each region can be formed by different processes, such that the gate electrode 106 can be made of different materials and / or have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0125] After filling the second recess 102, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 104 and the gate electrode 106 above the top surface of the first ILD 96. The excess material from the gate electrode 106 and the gate dielectric layer 104 thus forms the replacement gate structure of the resulting nano-FET. The gate electrode 106 and the gate dielectric layer 104 can be collectively referred to as the “gate structure”. In some embodiments, after the planarization process, one or more cleaning processes are performed on the gate electrode 106 and the first ILD 96. Because the film quality of the main dielectric 100 has been improved, the main dielectric 100 can have sufficient resistance to cleaning agents during the cleaning process. In some embodiments, adjacent gate structures in the first region 50A have a first pitch P1, and adjacent gate electrodes 106 in the first region 50A have a third pitch P3 substantially equal to the first pitch P1. In some embodiments, adjacent gate structures in the second region 50B have a second pitch P2, and adjacent gate electrodes 106 in the second region 50B have a fourth pitch P4 that is substantially equal to the second pitch P2.

[0126] exist Figures 19A to 19C In this process, the gate structure (including the gate dielectric layer 104 and the corresponding overlying gate electrode 106) is recessed, thereby forming a groove between the gate structure directly above and the opposing portion of the first spacer 81. A gate mask 108 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled into the groove, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The gate contacts (such as contact 118, hereinafter referred to) are then formed. Figure 21A and Figure 21B(To be discussed) Penetrate the gate shield 108 to contact the top surface of the recessed gate electrode 106.

[0127] like Figures 19A to 19C As further shown, the second ILD 110 is deposited over the first ILD 96 and over the gate mask 108. In some embodiments, the second ILD 110 is a flowable dielectric formed by FCVD. In some embodiments, the second ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0128] exist Figures 20A to 20C In this process, the second ILD 110, the first ILD 96, CESL 94, and the gate mask 108 are etched to form a third recess 112, exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 112 can be formed by etching using anisotropic etching processes such as RIE, NBE, or similar methods. In some embodiments, the third recess 112 can be etched through the second ILD 110 and the first ILD 96 using a first etching process; it can be etched through the gate mask 108 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A mask such as a photoresist can be formed and patterned over the second ILD 110 to shield portions of the second ILD 110 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch, so that the third groove 112 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 112 may be flush with (e.g., at the same level, or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 20BThe third recess 112 is illustrated to expose the epitaxial source / drain region 92 and the gate structure in the same cross-section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently formed contacts. After forming the third recess 112, a silicide region 114 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 114 is formed by first depositing a metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 114. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 114 is referred to as a silicide region, it may also be a germanide region or a silicon germanide region (e.g., a region containing both silicide and germanide). In one or more embodiments, the silicide region 114 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0129] Next, in Figures 21A to 21C In the third recess 112, contacts 118 and 116 (also referred to as contact plugs) are formed. Contacts 118 and 116 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 118 and 116 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate electrode 106 and / or silicide region 114 in the illustrated embodiment). Contact 118 is electrically coupled to the gate electrode 106 and may be referred to as a gate contact, and contact 116 is electrically coupled to the silicide region 114 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 110. Because the film quality of the first ILD 96 has been improved and can be maintained after various cleaning and etching processes, leakage or short circuits between adjacent gate contacts 118 can be reduced or prevented.

[0130] Figures 22A to 22C The figure shows a cross-sectional view of an apparatus according to some alternative embodiments. Figure 22A Illustration Figure 1 The reference cross section A-A' is shown in the figure. Figure 22B Illustration Figure 1 The reference cross section B-B' is shown in the figure. Figure 22C Illustration Figure 1 The reference cross section C-C' is shown in the diagram. Figures 22A to 22CIn the text, similar reference figures indicate that they are formed by... Figures 21A to 21C Similar components are formed using processes with similar structures. However, in Figures 22A to 22C In the first region 50A and the second region 50B, the channel region includes a first nanostructure 52, and the bottom of the first nanostructure 52 is in contact with the fin 66. For example, this can be formed by simultaneously removing a second nanostructure 54 from both the first region 50A and the second region 50B. Figures 22A to 22C The structure is such that a gate dielectric layer 104 and a gate electrode 106 are deposited around the first nanostructure 52.

[0131] As described above, although the interlayer dielectric is cured only by a low-temperature annealing process to reduce or avoid dopant deactivation in the source / drain regions, the embodiments disclosed herein provide ILDs with good thin-film quality to various cleaning and etching processes. In some embodiments, such ILDs can be formed by simply forming a carbon-containing liner prior to forming the main dielectric of the ILD. ILDs and their fabrication processes can be beneficial for transistors with high density, such as SRAM devices or logic devices.

[0132] In one or more embodiments, a method of manufacturing a semiconductor device is provided. The method includes forming a dummy gate inserted between source / drain regions; forming an etch stop layer over the dummy gate and the source / drain regions, wherein the etch stop layer comprises a nitride layer; forming an interlayer dielectric over the etch stop layer, wherein the interlayer dielectric comprises a liner and a main dielectric over the liner, wherein the liner comprises carbon; wherein forming the main dielectric includes: forming a flowable dielectric around the dummy gate and over the source / drain regions; and curing the flowable dielectric, wherein carbon in the liner diffuses into the flowable dielectric while curing the flowable dielectric; removing the etch stop layer, liner, and main dielectric over the dummy gate by a planarization process to expose the dummy gate; and replacing the dummy gate with a gate. In one or more embodiments, curing the flowable dielectric includes performing an annealing process at a temperature between 400°C and 500°C. In one or more embodiments, the annealing process includes a first stage and a second stage, wherein the interlayer dielectric is exposed to an oxygen-containing gas in the first stage and to a nitrogen-containing gas in the second stage. In one or more embodiments, the primary dielectric includes a gradually decreasing carbon concentration from the lower portion of the primary dielectric to the upper portion of the primary dielectric. In one or more embodiments, the liner is a SiOCN layer. In one or more embodiments, the etch-stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness. In one or more embodiments, after curing the flowable dielectric, the carbon-to-silicon atomic ratio of the liner decreases from between 1 and 12 to between 0.1 and 0.2.

[0133] A method for manufacturing a semiconductor device is provided. The method includes forming a first channel, a second channel, a third channel, and a fourth channel over a substrate; forming a first dummy gate, a second dummy gate, a third dummy gate, and a fourth dummy gate over the first channel, the second channel, the third channel, and the fourth channel, respectively, wherein a first pitch between the first dummy gate and the second dummy gate is smaller than a second pitch between the third dummy gate and the fourth dummy gate; forming an etch stop layer over the substrate, the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate; forming an interlayer dielectric over the etch stop layer, wherein the interlayer dielectric includes a liner over the etch stop layer and a main dielectric over the liner, wherein the liner includes carbon, and forming the main dielectric includes forming a flowable dielectric over the liner, between the first dummy gate and the second dummy gate, and between the third dummy gate and the fourth dummy gate; and forming an etch stop layer over the first dummy gate and the second dummy gate. A first thermal budget is provided for a first portion of the flowable dielectric between the dummy gate and the second dummy gate, and a second thermal budget is provided for a second portion of the flowable dielectric between the third dummy gate and the fourth dummy gate to solidify the first and second portions of the flowable dielectric, wherein the first thermal budget is smaller than the second thermal budget, and carbon in the liner diffuses into the first and second portions of the flowable dielectric while the first and second thermal budgets are provided; an etch stop layer, liner, and main dielectric above the first, second, third, and fourth dummy gates are removed by a planarization process to expose the first, second, third, and fourth dummy gates; and the first, second, third, and fourth dummy gates are replaced with the first, second, third, and fourth gates, respectively. In one or more embodiments, the carbon concentration of the first portion of the main dielectric gradually decreases from a first depth of the first portion of the first main dielectric to a second depth of the second portion of the first main dielectric, wherein the first depth is lower than the second depth. In one or more embodiments, the first carbon concentration of a first portion of the main dielectric at a first depth level flush with the top of the first dummy gate is greater than the second carbon concentration of a second portion of the main dielectric at a second depth level flush with the top of the third dummy gate. In one or more embodiments, the first and second thermal budgets are provided by an annealing process at a temperature not exceeding 500 degrees Celsius. In one or more embodiments, both the liner and the etch-stop layer comprise nitrogen, and both the liner and the main dielectric comprise oxygen. In one or more embodiments, the flowable dielectric is carbon-free prior to curing, and the liner is a SiOCN layer. In one or more embodiments, the etch-stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

[0134] In one or more embodiments, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein both the liner and the main dielectric include at least silicon, oxygen, and carbon, wherein the main dielectric includes a lower portion and an upper portion, wherein a first carbon concentration of the main dielectric at the lower portion is greater than a second carbon concentration of the main dielectric at the upper portion. In one or more embodiments, the carbon concentration in the main dielectric gradually decreases from the second carbon concentration to the first carbon concentration along the thickness direction of the main dielectric. In one or more embodiments, the liner is a SiOCN layer. In one or more embodiments, both the main dielectric and the liner further include nitrogen. In one or more embodiments, the nitrogen concentration of the liner is greater than the nitrogen concentration of the main dielectric. In one or more embodiments, the etch stop layer has a first thickness and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

[0135] In one or more embodiments, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch-stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch-stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion. In one or more embodiments, the liner is a nitrogen-containing liner. In one or more embodiments, the etch-stop layer is a nitrogen-containing etch-stop layer. In one or more embodiments, the etch-stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

[0136] In one or more embodiments, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch-stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch-stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a nitrogen-containing liner. In one or more embodiments, the etch-stop layer is a nitrogen-containing etch-stop layer. In one or more embodiments, the etch-stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

[0137] In one or more embodiments, the semiconductor device includes a channel above a substrate; a gate above the channel and inserted between source / drain regions; an etch-stop layer around the sidewalls of the gate and above the substrate and source / drain regions; and an interlayer dielectric above the etch-stop layer, wherein the interlayer dielectric includes a liner and a main dielectric above the liner, wherein the main dielectric includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a carbon-containing liner. In one or more embodiments, the etch-stop layer is a nitrogen-containing etch-stop layer. In one or more embodiments, the etch-stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

[0138] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Include: A channel above a substrate; A gate is inserted above this channel between multiple source / drain regions; An etch stop layer is formed around the multiple sidewalls of the gate and above the substrate and the multiple source / drain regions. and An interlayer dielectric layer above the etch stop layer, wherein the interlayer dielectric layer includes a liner and a main dielectric layer above the liner, wherein the main dielectric layer includes a carbon-containing lower portion and a carbon-containing upper portion.

2. The semiconductor device according to claim 1, wherein The lining is a nitrogen-containing lining.

3. The semiconductor device according to claim 1, wherein The etching stop layer is a nitrogen-containing etching stop layer.

4. The semiconductor device according to claim 1, wherein The etch stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

5. A semiconductor device, characterized in that, Include: A channel above a substrate; A gate is inserted above this channel between multiple source / drain regions; An etch stop layer is formed around the multiple sidewalls of the gate and above the substrate and the multiple source / drain regions. and An interlayer dielectric layer above the etch stop layer, wherein the interlayer dielectric layer includes a liner and a main dielectric layer above the liner, wherein the main dielectric layer includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a nitrogen-containing liner.

6. The semiconductor device according to claim 5, wherein The etching stop layer is a nitrogen-containing etching stop layer.

7. The semiconductor device according to claim 5, wherein The etch stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

8. A semiconductor device, characterized by comprising: Include: A channel above a substrate; A gate is inserted above this channel between multiple source / drain regions; An etch stop layer is formed around the multiple sidewalls of the gate and above the substrate and the multiple source / drain regions. and An interlayer dielectric layer above the etch stop layer, wherein the interlayer dielectric layer includes a liner and a main dielectric layer above the liner, wherein the main dielectric layer includes a carbon-containing lower portion and a carbon-containing upper portion, and the liner is a carbon-containing liner.

9. The semiconductor device according to claim 8, wherein The etching stop layer is a nitrogen-containing etching stop layer.

10. The semiconductor device according to claim 8, wherein The etch stop layer has a first thickness, and the liner has a second thickness, wherein the first thickness is greater than the second thickness.

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