Display device and electronic device

Abstract

The utility model relates to a display device and an electronic device. The display device includes: a display element layer including a light emitting element; an encapsulation layer on the display element layer, the encapsulation layer being formed as a single layer; and a light control layer overlapping the encapsulation layer, the light control layer including a light control pattern layer including a first wavelength conversion layer, a second wavelength conversion layer, and a light transmitting layer, in which the light emitting element includes a first electrode, an organic light emitting portion on the first electrode, and a second electrode on the organic light emitting portion, and in which the first wavelength conversion layer and the second wavelength conversion layer overlap each other. A distance between a top surface of the second electrode and a bottom surface of the light control pattern layer is in a range of 10 nanometers (nm) to 2000 nanometers.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0050924, filed on April 16, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure generally relate to display devices, electronic devices, and methods of manufacturing display devices. Background Technology

[0004] With the development of information technology, the importance of display devices, which provide a connection medium between users and information, has increased. Accordingly, research and development of display devices has been ongoing.

[0005] A display device may include a plurality of pixels for displaying an image, and each of the pixels may include a light-emitting element for emitting light and a driving element connected to the light-emitting element. When the light-emitting element emits light toward the display surface of the display device, light loss may occur, and therefore a structure for reducing or preventing this problem may be desirable.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0007] Some aspects of embodiments of this disclosure include a display device and a method of manufacturing a display device, wherein the light output efficiency of the display device is relatively improved and the thickness of the display device is relatively reduced.

[0008] According to some embodiments of this disclosure, a display device includes: a display element layer including a light-emitting element; an encapsulation layer formed as a single layer on the display element layer; and a light control layer overlapping the encapsulation layer, wherein the light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion, wherein the light control layer includes a light control pattern layer, the light control pattern layer including a first wavelength conversion layer, a second wavelength conversion layer, and a light-transmitting layer, and wherein the distance between the top surface of the second electrode and the bottom surface of the light control pattern layer is 10 nm to 2000 nm.

[0009] According to some embodiments, the encapsulation layer can be deposited using atomic layer deposition (ALD) (e.g., plasma-enhanced atomic layer deposition (PEALD)).

[0010] According to some embodiments, the encapsulation layer can have a thickness of 10 nm to 1000 nm.

[0011] According to some embodiments, the bottom surface of the encapsulation layer can contact the second electrode, and the top surface of the encapsulation layer can contact the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer.

[0012] According to some embodiments, the encapsulation layer may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and titanium dioxide (TiO) x At least one of the following.

[0013] According to some embodiments, the light control layer may further include a first capping layer on top of the light control pattern layer. According to some embodiments, the first capping layer may include an inorganic material and have a thickness of 100 nm to 1000 nm.

[0014] According to some embodiments, the light control layer may further include a low-refractive-index layer on the first capping layer. According to some embodiments, the low-refractive-index layer may have a lower refractive index than the light control patterning layer. According to some embodiments, the low-refractive-index layer may have a refractive index of 1.1 to 1.4.

[0015] According to some embodiments, the display device may further include a color filter layer on the light control layer. According to some embodiments, the color filter layer may include a first color filter, a second color filter, and a third color filter, as well as a planarization layer over the first, second, and third color filters. According to some embodiments, the first color filter may allow red light to be selectively transmitted through it, the second color filter may allow green light to be selectively transmitted through it, and the third color filter may allow blue light to be selectively transmitted through it.

[0016] According to some embodiments, the planarization layer may include an organic material and have a thickness in the range of 1,000 nm to 10,000 nm.

[0017] According to some embodiments, the display device may further include: a first sub-pixel region emitting light of a first color; a second sub-pixel region emitting light of a second color; a third sub-pixel region emitting light of a third color; and a dam between the first sub-pixel region and the third sub-pixel region. According to some embodiments, a first wavelength conversion layer may be located in the first sub-pixel region, a second wavelength conversion layer may be located in the second sub-pixel region, and a light-transmitting layer may be located in the third sub-pixel region.

[0018] According to some embodiments, the display device may further include an anti-reflective film on the planarization layer.

[0019] According to some embodiments of this disclosure, a display device includes: a display area having pixels, the display area including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area; a display element layer including a light-emitting element forming a pixel; an encapsulation layer on the display element layer; and a light control layer overlapping the display element layer, wherein the light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion, wherein the light control layer includes a light control pattern layer, the light control pattern layer including a first wavelength conversion layer in the first sub-pixel area, a second wavelength conversion layer in the second sub-pixel area, and a light-transmitting layer in the third sub-pixel area, and wherein the distance between the top surface of the second electrode and the bottom surface of the light control pattern layer is 10 nm to 1000 nm.

[0020] According to some embodiments, the encapsulation layer can be formed as a single layer. According to some embodiments, the bottom surface of the encapsulation layer can contact the second electrode, and the top surface of the encapsulation layer can contact the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer. According to some embodiments, the encapsulation layer may include an inorganic material.

[0021] According to some embodiments, the light control layer may further include: a first capping layer on the light control pattern layer; and a low-refractive-index layer on the first capping layer. According to some embodiments, the low-refractive-index layer may have a refractive index lower than that of the light control pattern layer. According to some embodiments, the first capping layer may be in contact with the light control pattern layer. According to some embodiments, the first capping layer may include an inorganic material and have a thickness of 100 nm to 1000 nm. The low-refractive-index layer may have a refractive index of 1.1 to 1.4.

[0022] According to some embodiments, the display device may further include a color filter layer on the light control layer. According to some embodiments, the color filter layer may include a first color filter, a second color filter, and a third color filter, and a planarization layer above the first, second, and third color filters. According to some embodiments, the first color filter may overlap with a first sub-pixel region, the second color filter may overlap with a second sub-pixel region, and the third color filter may overlap with a third sub-pixel region. According to some embodiments, the planarization layer may include an organic material and have a thickness of 1500 nm to 10000 nm.

[0023] According to some embodiments, the display device may include a dam on an encapsulation layer. According to some embodiments, the dam may include an opening. According to some embodiments, the opening may overlap with a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region.

[0024] According to some embodiments, the first wavelength conversion layer and the second wavelength conversion layer may include quantum dots. According to some embodiments, the light-transmitting layer may include a scatterer.

[0025] According to some embodiments, the display device may further include an anti-reflective film on the planarization layer.

[0026] According to some embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming a display element layer including a light-emitting element; forming an encapsulation layer on the display element layer; and forming a light control layer overlapping the encapsulation layer, wherein the light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion, wherein the light control layer includes a light control pattern layer, the light control pattern layer including a first wavelength conversion layer, a second wavelength conversion layer, and a light-transmitting layer, wherein the distance between the second electrode and the light control pattern layer is 10 nm to 2000 nm, and wherein the formation of the encapsulation layer includes depositing the encapsulation layer by using atomic layer deposition (ALD) (e.g., plasma-enhanced atomic layer deposition (PEALD)).

[0027] According to some embodiments, the encapsulation layer can be formed as a single layer.

[0028] The electronic device includes: a processor for providing input image data; and a display device for displaying images based on the input image data. The display device includes: a display element layer including a light-emitting element; an encapsulation layer formed as a single layer on the display element layer; and a light control layer overlapping the encapsulation layer, the light control layer including a light control pattern layer comprising a first wavelength conversion layer, a second wavelength conversion layer, and a light-transmitting layer. The light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion. The distance between the top surface of the second electrode and the bottom surface of the light control pattern layer is in the range of 10 nanometers (nm) to 2000 nm. Attached Figure Description

[0029] Some aspects of the embodiments will now be described more fully below with reference to the accompanying drawings; however, some aspects of the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0030] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, it may be the only element between those two elements, or there may be one or more intervening elements. The same reference numerals refer to the same elements throughout.

[0031] Figure 1 This is a schematic plan view illustrating a display device according to some embodiments of the present disclosure.

[0032] Figure 2 , Figure 3 and Figure 4 It is a diagram. Figure 1 The diagram shows a schematic plan view of the pixels.

[0033] Figure 5 It is a diagram. Figure 1 A schematic cross-sectional view of the display panel is shown in the figure.

[0034] Figure 6 The illustration includes Figures 2 to 4 The circuit diagram for each of the sub-pixels in the pixel is shown.

[0035] Figure 7 It is a diagram. Figure 6 The diagram shows a schematic cross-sectional view of the light-emitting element.

[0036] Figure 8 It is a diagram. Figure 6 The diagram shows a schematic cross-sectional view of the light-emitting element.

[0037] Figure 9 The illustration includes Figure 7 or Figure 8 The diagram shows a schematic cross-sectional view of a pixel in the light-emitting element.

[0038] Figure 10 This is a flowchart illustrating aspects of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0039] Figure 11 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0040] Figure 12 It is a diagram. Figure 11 The electronic device shown is a schematic diagram of an example of a smartphone.

[0041] Figure 13 It is a diagram. Figure 11 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0042] Aspects of some embodiments of this disclosure can be applied in various variations and different forms, and are therefore described in detail by specific examples only. However, these examples are not limited to a particular form, but are applicable to all variations and equivalent materials and substitutions. The included figures are illustrated in a manner that expands upon multiple figures for better understanding.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the “first” element discussed below may also be referred to as the “second” element without departing from the teachings of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0044] It will be further understood that, when used in this specification, the terms "comprising" and / or "including" indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence and / or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the expression that an element, such as a layer, region, substrate, or plate, is placed "on" or "above" another element indicates not only that the element is placed "directly" on or "straight above" the other element, but also that another element is inserted between the element and the other element. Conversely, the expression that an element, such as a layer, region, substrate, or plate, is placed "below" or "under" another element indicates not only that the element is placed "directly" below or "straight below" the other element, but also that another element is inserted between the element and the other element.

[0045] Some aspects of embodiments of this disclosure relate to display devices. Hereinafter, display devices according to some embodiments of this disclosure will be described with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic plan view illustrating a display device according to some embodiments of the present disclosure.

[0047] refer to Figure 1 A display panel (DP) (or display device DD) can display images. The display panel (DP) may include a light-emitting element (LD) (see...). Figure 9 Self-emissive display panels, such as organic light-emitting display panels (OLED panels) using organic light-emitting diodes as light-emitting elements, micron-LED or nano-LED display panels using micron-LEDs or nano-LEDs as light-emitting elements, and quantum dot organic light-emitting display panels (QD OLED panels) using quantum dots and organic light-emitting diodes, can be used as display panel DPs. Additionally, non-emissive display panels, such as liquid crystal display panels (LCD panels), electrophoretic display panels (EPD panels), and electrowetting display panels (EWD panels), can be used as display panel DPs. When a non-emissive display panel is used as a display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP. However, embodiments according to this disclosure are not limited to specific examples. Hereinafter, embodiments in this disclosure will be described in which a quantum dot organic light-emitting display panel (QD OLED panel) is used as a display panel DP.

[0048] The display panel DP may include a substrate SUB and pixels PXL provided on the substrate SUB.

[0049] The substrate SUB may include a transparent insulating material to allow light to be transmitted through it. The substrate SUB may be a rigid substrate or a flexible substrate. A rigid substrate may be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, or a crystalline glass substrate.

[0050] The flexible substrate can be one of a membrane substrate comprising a polymeric organic material and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0051] The display device DD (or display panel DP) can have various shapes. According to some embodiments, the display device DD can be provided in a rectangular shape, but embodiments according to this disclosure are not limited thereto. For example, the display device DD can have a circular or elliptical shape. Furthermore, the display device DD may include corners and / or curved corners. For convenience, in Figure 1 The illustration shows that the display device DD has a rectangular plate shape. Furthermore, in... Figure 1 In this design, the extension direction of the short side of the display device DD (e.g., the horizontal direction) (or the horizontal direction as the "row" direction of the pixel PXL) is indicated as the first direction DR1, and the extension direction of the long side of the display device DD (e.g., the vertical direction) (or the "column" direction of the pixel PXL) is indicated as the second direction DR2. Additionally, the normal to the display direction of the display device DD or the plane on which the substrate SUB is located is indicated as the third direction DR3.

[0052] The substrate SUB (and the display device DD) may include a display area DA for displaying an image and a peripheral area PA (or a non-display area) surrounding the display area DA (or other than the display area DA). The substrate SUB may include the display area DA and the peripheral area PA, the display area DA including the pixel area in which each pixel PXL is located, and the peripheral area PA located outside the display area DA (e.g., surrounding the display area DA or outside the coverage area of ​​the display area DA) (or adjacent to the display area DA).

[0053] The peripheral region PA may be disposed adjacent to the display region DA. The peripheral region PA may be provided on at least one side of the display region DA. According to some embodiments, the peripheral region PA may surround the periphery (or edge) of the display region DA. According to some embodiments, the peripheral region PA may be the bezel area of ​​the display device DD.

[0054] Pixel PXL can be located in the display area DA, on the substrate SUB. The peripheral area PA can be located around the display area DA. The peripheral area PA can have a structure for protecting components included in the pixel PXL located in the display area DA, but embodiments according to this disclosure are not limited thereto. For example, line units connected to the pixel PXL and driving units connected to the line units to drive the pixel PXL can be provided in the peripheral area PA.

[0055] Pixel PXL may include a plurality of sub-pixels SPX1, SPX2, and SPX3. According to some embodiments, pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged on a first direction DR1. However, embodiments according to this disclosure are not limited thereto, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged on a second direction DR2 intersecting the first direction DR1.

[0056] The first to third sub-pixels SPX1, SPX2, and SPX3 can emit light of different colors. According to some embodiments, the first sub-pixel SPX1 can emit a first light, the second sub-pixel SPX2 can emit a second light, and the third sub-pixel SPX3 can emit a third light. The first light can be light in the red band, the second light can be light in the green band, and the third light can be light in the blue band. The red band can be from approximately 600 nm to approximately 750 nm, the green band can be from approximately 480 nm to approximately 560 nm, and the blue band can be from approximately 370 nm to approximately 460 nm. However, embodiments according to this disclosure are not limited thereto. The color, type, and / or number of pixels constituting pixel PXL are not particularly limited. According to some embodiments, the color of the light emitted by each of the first to third sub-pixels SPX1, SPX2, and SPX3 can be varied. In the following text, when the first to third sub-pixels SPX1, SPX2 and SPX3 are included in the inner-matrix designation, the first to third sub-pixels SPX1, SPX2 and SPX3 can be designated as pixel PXL.

[0057] Figure 2 , Figure 3 and Figure 4 It is a diagram. Figure 1 A schematic plan view of an embodiment of the pixels shown.

[0058] Figures 2 to 4Each of the first sub-pixels SPX1, SPX2, and SPX3 in the diagram can be connected to any one of the data lines and at least one of the scan lines.

[0059] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can have a planar shape of rectangle, square, or other polygon.

[0060] refer to Figure 2 Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. However, embodiments according to this disclosure are not limited thereto. According to some embodiments, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a square or rhomboid planar shape including sides of equal length in the first direction DR1 and the second direction DR2. According to some embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be arranged in the first direction DR1. According to some embodiments, the areas of the first to third sub-pixels SPX1, SPX2, and SPX3 may be the same (or substantially the same), but embodiments according to this disclosure are not limited thereto. For example, at least one of the areas of the first to third sub-pixels SPX1, SPX2, and SPX3 may be different from the other of the areas of the first to third sub-pixels SPX1, SPX2, and SPX3. Alternatively, any two of the areas of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be substantially the same, and the third sub-pixel SPX3 can be different from said two of the areas of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Alternatively, the areas of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be different from each other.

[0061] refer to Figure 3The first sub-pixel SPX1 can be arranged on a first direction DR1 with either the second sub-pixel SPX2 or the third sub-pixel SPX3, and on a second direction DR2 with the other of the second sub-pixel SPX2 and the third sub-pixel SPX3. For example, the first sub-pixel SPX1 can be arranged side-by-side with the second sub-pixel SPX2 on the first direction DR1, and with the third sub-pixel SPX3 on the second direction DR2. According to some embodiments, the third sub-pixel SPX3 can be adjacent to the first sub-pixel SPX1 and the second sub-pixel SPX2 along the second direction DR2. According to some embodiments, the third sub-pixel SPX3 can be arranged on the second direction DR2 with the first sub-pixel SPX1 and the second sub-pixel SPX2. According to some embodiments, the areas of the first sub-pixel SPX1 and the second sub-pixel SPX2 can be the same (or substantially the same), and the area of ​​the third sub-pixel SPX3 can be different from the areas of each of the first sub-pixel SPX1 and the second sub-pixel SPX2. For example, the area of ​​the third sub-pixel SPX3 can be larger than the area of ​​each of the first sub-pixel SPX1 and the second sub-pixel SPX2.

[0062] refer to Figure 4 Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a hexagonal (e.g., regular hexagonal) planar shape. According to some embodiments, two adjacent surfaces of the six surfaces of each of the first to third sub-pixels SPX1 to SPX3 may face adjacent sub-pixels SPX (see [link to embodiment]). Figure 6 (a surface of)

[0063] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light-emitting element (e.g., Figure 7 or Figure 8 The light-emitting element (LD) shown in the figure may include an organic light-emitting element having an organic layer.

[0064] Figure 5 It is a diagram. Figure 1 A schematic cross-sectional view of the display panel is shown in the figure.

[0065] refer to Figure 5 The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a packaging layer TFE, a light control layer LCL, and a color filter layer CFL. According to some embodiments, the substrate SUB, pixel circuit layer PCL, display element layer DPL, packaging layer TFE, light control layer LCL, and color filter layer CFL may be sequentially stacked on a third-direction DR3.

[0066] A pixel circuit layer (PCL) can be provided on a substrate SUB and includes a plurality of transistors and signal lines connected to the transistors. For example, each transistor can be provided in a configuration where a semiconductor layer, a gate electrode, a source electrode, and a drain electrode are sequentially stacked with an insulating layer interposed therebetween. The semiconductor layer can include at least one of amorphous silicon, monocrystalline silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon), organic semiconductors, and oxide semiconductors. The gate electrode, source electrode, and drain electrode can include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but embodiments according to this disclosure are not limited thereto. Furthermore, the pixel circuit layer (PCL) can include at least one insulating layer.

[0067] The display element layer (DPL) can be located on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements (e.g., Figure 7 or Figure 8 The light-emitting element (LD) shown in the figure may be, for example, an organic light-emitting diode, but is not limited thereto according to embodiments of this disclosure.

[0068] The encapsulation layer TFE can be located on the display element layer DPL. The encapsulation layer TFE can be an encapsulation substrate or provided in the form of an encapsulation film formed as a single layer. However, embodiments according to this disclosure are not limited thereto, and the encapsulation layer TFE can have a multilayer structure.

[0069] When the encapsulation layer TFE is provided as a single-layer encapsulation film, the encapsulation layer TFE may include an inorganic layer. According to some embodiments, when the encapsulation layer TFE is formed as a single layer, it may be formed from a single material. According to some embodiments, when the encapsulation layer TFE is formed as a single layer, it may be a layer in which the interface between two or more layers is not observed.

[0070] When the encapsulation layer TFE is provided in the form of a multilayer encapsulation film, the encapsulation layer TFE may include organic layers and inorganic layers. For example, the multilayer encapsulation layer TFE may be provided in which inorganic layers, organic layers, and inorganic layers are stacked in sequence.

[0071] The encapsulation layer TFE can prevent or reduce the penetration of contaminants such as external air and moisture into the display element layer DPL and pixel circuit layer PCL. The encapsulation layer TFE according to this disclosure is characterized by a relatively reduced thickness of the display device DD and a relatively improved light output efficiency of the display device DD. Reference will be made later. Figure 9 This will be described.

[0072] The light control layer LCL may be located on the encapsulation layer TFE. The light control layer LCL may include elements for converting at least a portion of the light emitted from the display element layer DPL into light of a specific color and relatively improving light output efficiency. According to some embodiments, the light control layer LCL may include a light control pattern layer CCL (see...). Figure 9 ) and low-refractive layer LRL (see Figure 9 However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the low-refractive-index layer (LRL) may be omitted.

[0073] exist Figure 5 The diagram illustrates a light control layer (LCL) and a packaging layer (TFE) sequentially stacked on a display element layer (DPL). However, embodiments according to this disclosure are not limited to this. The light control layer (LCL) may be located below the display element layer (DPL). For example, the light control layer (LCL) may be located below the display element layer (DPL) in the direction opposite to the third direction (DR3). The light control layer (LCL) may overlap with the display element layer (DPL), and the display element layer (DPL) may be located above or below the light control layer (LCL).

[0074] A color filter layer (CFL) can be located on the light control layer (LCL). The color filter layer (CFL) allows light passing through the light control layer (LCL) (or the display element layer (DPL)) to be selectively transmitted through the color filter layer (CFL). The color filter layer (CFL) can include first to third color filters CF1, CF2, and CF3 (see...). Figure 9 ).

[0075] Figure 6 The illustration includes, according to some embodiments Figures 2 to 4 The circuit diagram for each of the sub-pixels in the pixel shown is a circuit diagram. Although Figure 6 Various components in a subpixel are illustrated according to some embodiments, but the embodiments of this disclosure are not limited thereto, and according to some embodiments, a subpixel may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0076] Figure 6 The sub-pixel SPX shown in the image can be Figure 1 Any one of the sub-pixels SPX1, SPX2 and SPX3 shown in the figure, and the sub-pixels SPX1, SPX2 and SPX3 arranged in the display area of ​​each display device DD can be configured to be substantially the same or similar to each other.

[0077] exist Figure 6 For convenience, the sub-pixel SPX located in the i-th pixel row (or i-th horizontal row) and j-th pixel column is illustrated (i and j are natural numbers greater than 0).

[0078] refer to Figure 6The sub-pixel SPX may include a light-emitting unit (EMU) that generates light with a brightness corresponding to the data signal. Furthermore, the sub-pixel SPX may further include a pixel circuit (PXC) for driving the light-emitting unit (EMU).

[0079] The light-emitting unit (EMU) may include a light-emitting element (LD) connected between a first power line PL1 supplied with voltage from a first driving power source VDD (or a first power supply) and a second power line PL2 supplied with voltage from a second driving power source VSS (or a second power supply). According to some embodiments, the EMU may include a light-emitting element LD comprising a first electrode AE ​​connected to the first driving power source VDD via a pixel circuit PXC and the first power line PL1, and a second electrode CE connected to the second driving power source VSS via the second power line PL2. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The first driving power source VDD and the second driving power source VSS may have different potentials. The potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light-emitting element LD or higher during the emission period.

[0080] When sub-pixel SPX is located in the i-th pixel row and j-th pixel column of display area DA, the pixel circuit PXC of sub-pixel SPX (or sub-pixel) can be electrically connected to the i-th scan line Si and the j-th data line Dj. Furthermore, the pixel circuit PXC can be electrically connected to the i-th control line CLI and the j-th sensing line SENj.

[0081] The aforementioned pixel circuit PXC may include first transistors to third transistors T1, T2 and T3, and storage capacitor Cst.

[0082] The first transistor T1 can be a driving transistor for controlling the driving current applied to the light-emitting element LD, and is electrically connected between the first driving power supply VDD and the light-emitting element LD. Specifically, the first terminal of the first transistor T1 can be electrically connected to the first driving power supply VDD through the first power line PL1, the second terminal of the first transistor T1 can be electrically connected to the second node N2, and the gate electrode of the first transistor T1 can be electrically connected to the first node N1. The first transistor T1 can control the amount of driving current applied from the first driving power supply VDD to the light-emitting element LD through the second node N2 according to the voltage applied to the first node N1. According to some embodiments, the first terminal of the first transistor T1 can be the drain electrode, and the second terminal of the first transistor T1 can be the source electrode. However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the first terminal can be the source electrode, and the second terminal can be the drain electrode.

[0083] The second transistor T2 can be a switching transistor for selecting and activating sub-pixels SPX in response to a scan signal, and is electrically connected between data line Dj (e.g., the j-th data line) and the first node N1. The first terminal of the second transistor T2 can be electrically connected to data line Dj, the second terminal of the second transistor T2 can be electrically connected to the first node N1 (or the gate electrode of the first transistor T1), and the gate electrode of the second transistor T2 can be electrically connected to scan line Si (e.g., the i-th scan line). The first and second terminals of the second transistor T2 are different terminals. For example, when the first terminal is the drain electrode, the second terminal can be the source electrode.

[0084] When a scan signal with a gate on-state voltage (e.g., a high-level voltage) is supplied from scan line Si, the second transistor T2 can be turned on to electrically connect data line Dj and the first node N1 to each other. The first node N1 can be the point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 can transmit the data signal to the gate electrode of the first transistor T1.

[0085] The third transistor T3 can electrically connect the first transistor T1 to the sensing line SENj (e.g., the j-th sensing line), thereby acquiring a sensing signal through the sensing line SENj and detecting characteristics of the sub-pixel SPX, including the threshold voltage of the first transistor T1. Information about the characteristics of the sub-pixel SPX can be used to transform image data, allowing for compensation of characteristic deviations between sub-pixels SPX. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sensing line SENj, and the gate electrode of the third transistor T3 can be electrically connected to the control line CLI (e.g., the i-th control line). The first terminal can be the drain electrode, and the second terminal can be the source electrode.

[0086] The third transistor T3 can be an initialization transistor used to initialize the second node N2, and is turned on when a sensing control signal is supplied from the control line CLI to transmit the voltage of the initialization power supply to the second node N2. Accordingly, the storage capacitor Cst electrically connected to the second node N2 can be initialized.

[0087] The storage capacitor Cst may include a lower electrode LE (or a first storage electrode) and an upper electrode UE (or a second storage electrode). The lower electrode LE may be electrically connected to a first node N1, and the upper electrode UE may be electrically connected to a second node N2. The storage capacitor Cst may be charged with a data voltage corresponding to the data signal supplied to the first node N1 during a frame period. Accordingly, the storage capacitor Cst may store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0088] although Figure 6 The diagram illustrates an embodiment where all three transistors T1, T2, and T3 are N-type transistors; however, embodiments according to this disclosure are not limited thereto. For example, at least one of the aforementioned three transistors T1, T2, and T3 can be replaced with a P-type transistor. The structure of the pixel circuit PXC can be modified and implemented in various ways.

[0089] Figure 7 The illustrations are based on some embodiments. Figure 6 The diagram shows a schematic cross-sectional view of the light-emitting element. Figure 8 The illustrations are based on some embodiments. Figure 6 A schematic cross-sectional view showing further details of the light-emitting element.

[0090] refer to Figure 7 The light-emitting element (LD) may include a first electrode AE, an organic light-emitting portion EL, and a second electrode CE. According to some embodiments, the first electrode AE, the organic light-emitting portion EL, and the second electrode CE may be stacked sequentially.

[0091] According to some embodiments, the first electrode AE ​​can be patterned to correspond to the first to third sub-pixels SPX1, SPX2 and SPX3.

[0092] According to some embodiments, the organic light-emitting portion (EL) can be provided on a first electrode AE. The organic light-emitting portion (EL) can be in contact with the first electrode AE. The organic light-emitting portion (EL) can have a multilayer thin film structure including multiple light-generating layers. The organic light-emitting portion (EL) can include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) stacked in sequence.

[0093] The hole injection layer HIL can be an organic layer located between the first electrode AE ​​and the hole transport layer HTL to allow holes to be smoothly injected from the first electrode AE ​​into the light-emitting layer EML. The hole transport layer HTL can be located between the hole injection layer HIL and the light-emitting layer EML to receive holes provided from the first electrode AE ​​and transport the holes to the light-emitting layer EML.

[0094] The electron injection layer (EIL) can be located between the electron transport layer (ETL) and the second electrode (CE). The electron transport layer (ETL) can be located on the light-emitting layer (EML) to receive electrons supplied from the second electrode (CE) and transport the electrons to the light-emitting layer (EML).

[0095] The light-emitting layer (EML) can be a region in which light is generated by the recombination of holes supplied from the first electrode AE ​​and electrons supplied from the second electrode CE. The EML can comprise an organic light-emitting material, such as a high-molecular-weight organic material or a low-molecular-weight organic material, that emits light of any color (e.g., a set or predetermined color). For example, the EML can be made of an organic material that emits blue light. However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the EML can be made of an organic material that emits red or green light, or of inorganic materials or quantum dots.

[0096] According to some embodiments, the second electrode CE can be provided integrally. The second electrode CE can be located on the organic light-emitting portion EL. The second electrode CE can be integrally formed in the light-emitting element LD.

[0097] refer to Figure 8 According to some embodiments, the organic light-emitting portion (EL) may include multiple light-generating layers. According to some embodiments, the organic light-emitting portion (EL) may include a first organic light-emitting portion (ELa), a charge-generating layer (CGL), and a second organic light-emitting portion (ELb). According to some embodiments, the first electrode (AE), the first organic light-emitting portion (ELa), the charge-generating layer (CGL), the second organic light-emitting portion (ELb), and the second electrode (CE) may be stacked sequentially.

[0098] The first organic light-emitting portion ELa can be provided in a structure in which a hole injection layer HIL, a first hole transport layer HTLa, a first organic light-emitting layer EMLa, and a first electron transport layer ETLa are stacked in sequence. The second organic light-emitting portion ELb can be provided in a structure in which a second hole transport layer HTLb, a second organic light-emitting layer EMLb, a second electron transport layer ETLb, and an electron injection layer EIL are stacked in sequence.

[0099] According to some embodiments, the buffer layer may be located on the first organic light-emitting layer EMLa and the second organic light-emitting layer EMLb. The buffer layer may include an electron transport compound.

[0100] The charge generation layer CGL can be used to supply charge to the first organic light-emitting part ELa and the second organic light-emitting part ELb. The charge generation layer CGL may include an n-type charge generation layer n-CGL for supplying electrons to the first organic light-emitting part ELa and a p-type charge generation layer p-CGL for supplying holes to the second organic light-emitting part ELb. The n-type charge generation layer n-CGL may include a metallic material as a dopant.

[0101] exist Figure 8The illustration shows two organic light-emitting portions, ELa and ELb, of a light-emitting element (LD) stacked together. However, embodiments according to this disclosure are not limited to this. For example, three, four, or more organic light-emitting portions may be stacked in the light-emitting element (LD).

[0102] Figure 9 The illustration includes, according to some embodiments Figure 7 or Figure 8 The diagram shows a schematic cross-sectional view of a pixel in the light-emitting element.

[0103] refer to Figure 1 and Figure 9 The display device DD may include a display area DA, and the display area DA may include first sub-pixel areas to third sub-pixel areas SPA1, SPA2, and SPA3, and a non-emitting area NEA. According to some embodiments, the first sub-pixel area SPA1 may be the area that emits light of a first color from the first sub-pixel SPX1. The second sub-pixel area SPA2 may be the area that emits light of a second color from the second sub-pixel SPX2. The third sub-pixel area SPA3 may be the area that emits light of a third color from the third sub-pixel SPX3. For example, the first sub-pixel area SPA1 may emit light in the red band, the second sub-pixel area SPA2 may emit light in the green band, and the third sub-pixel area SPA3 may emit light in the blue band.

[0104] According to some embodiments, the emission region of the display region DA may correspond to the first sub-pixel regions to the third sub-pixel regions SPA1, SPA2, and SPA3. The first sub-pixel regions to the third sub-pixel regions SPA1, SPA2, and SPA3, as well as the non-emission region NEA, may be defined by the embankment BNK of the light control layer LCL.

[0105] refer to Figure 9 Although the illustration shows an embodiment in which the first to third sub-pixel regions SPA1, SPA2 and SPA3 are adjacent to each other in a direction intersecting with the third direction DR3, the embodiments according to this disclosure are not necessarily limited thereto.

[0106] According to some embodiments, the pixel PXL may include a pixel circuit layer PCL, a display element layer DPL, an encapsulation layer TFE, a light control layer LCL, and a color filter layer CFL, which are sequentially disposed on the substrate SUB on the third-party DR3.

[0107] Circuit elements (e.g., Figure 6The first to third transistors (T1, T2, and T3) shown in the diagram, and the signal lines electrically connected to the circuit elements, can be located in the pixel circuit layer (PCL). The pixel circuit layer (PCL) can be located on the substrate (SUB). The pixel circuit layer (PCL) may include the first transistor T1, a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (ILD), a passivation layer (PVX), and a via layer (VIA). Although a first transistor T1 is illustrated as an example, the sub-pixel (SPX) may include at least one capacitor and multiple transistors for driving the light-emitting element (LD).

[0108] A buffer layer BFL can be located on the substrate SUB. The buffer layer BFL prevents or reduces the diffusion of contaminants or impurities from the outside. The buffer layer BFL also prevents or reduces the diffusion of contaminants or impurities into the first transistor T1 provided on the substrate SUB, thereby relatively improving the flatness of the substrate SUB. The buffer layer BFL can be provided as a single layer, but it can also be provided as multiple layers. The buffer layer BFL can be an inorganic insulating layer comprising inorganic materials. The inorganic insulating layer can include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x At least one of the metal oxides of (). When the buffer layer BFL is provided as a multilayer, the layers constituting the multilayer can be formed of the same material or of different materials. In some cases, the buffer layer BFL may be omitted.

[0109] The first transistor T1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal TE1, and a second terminal TE2. The first terminal TE1 may be either a source electrode or a drain electrode, and the second terminal TE2 may be the other of the source electrode and drain electrode. According to some embodiments, when the first terminal TE1 is a drain electrode, the second terminal TE2 may be a source electrode.

[0110] A semiconductor pattern SCP can be provided and / or formed on a buffer layer BFL. The semiconductor pattern SCP may include a first region contacting a first terminal TE1, a second region contacting a second terminal TE2, and a channel region between the first and second regions. The channel region may overlap with the gate electrode GE of the first transistor T1. The semiconductor pattern SCP can be a semiconductor pattern made of amorphous silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon), oxide semiconductor, or organic semiconductor. The channel region is, for example, an undoped semiconductor pattern and may be intrinsic semiconductor. The first and second regions may correspond to doped semiconductor patterns. According to some embodiments, the first terminal TE1 can be electrically connected to the light-emitting element LD via connecting electrodes CNE1 and CNE2.

[0111] A gate insulating layer GI may be provided (or formed) on a semiconductor pattern SCP. The gate insulating layer GI may be an inorganic insulating layer comprising inorganic materials. The gate insulating layer GI may comprise the same material as the buffer layer BFL, or may comprise at least one material selected from the materials described as constituting the buffer layer BFL. According to some embodiments, the gate insulating layer GI may be provided as an organic insulating layer comprising organic materials. The gate insulating layer GI may be provided as a single layer, but may be provided as a multilayer comprising at least two layers.

[0112] A gate electrode GE can be provided (or formed) on a gate insulating layer GI to correspond to the channel region of a semiconductor pattern SCP. The gate electrode GE can be provided on the gate insulating layer GI to overlap with the channel region of the semiconductor pattern SCP. The gate electrode GE can be formed as a single layer using one of the materials selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and mixtures thereof, or formed as a double-layer or multi-layer structure comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials, to reduce wiring resistance.

[0113] An interlayer insulating layer (ILD) may be provided (or formed) on the gate electrode GE. A first connection electrode CNE1 may be located on the interlayer insulating layer (ILD). The first connection electrode CNE1 may be electrically connected to the first terminal TE1 through contact holes penetrating the gate insulating layer GI and the interlayer insulating layer (ILD).

[0114] A passivation layer PVX may be provided (or formed) on the first connection electrode CNE1. A second connection electrode CNE2 may be located on the passivation layer PVX. The second connection electrode CNE2 may be electrically connected to the first connection electrode CNE1 through contact holes penetrating the passivation layer PVX.

[0115] The passivation layer PVX can be provided in the form of an inorganic insulating layer situated on an organic insulating layer or an organic insulating layer situated on an inorganic insulating layer. The inorganic insulating layer may include, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x The organic insulating layer may include at least one of the following: acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0116] The via layer (VIA) can be completely provided (or formed) on the passivation layer (PVX). The via layer (VIA) can be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials.

[0117] The display element layer (DPL) may be located on the via layer (VIA). The display element layer (DPL) may include a light-emitting element (LD) and a pixel defining layer (PDL). The light-emitting element (LD) and the pixel defining layer (PDL) may be provided (or formed) on the via layer (VIA). The light-emitting element (LD) may include a first light-emitting element (LD1) located in a first sub-pixel region (SPA1), a second light-emitting element (LD2) located in a second sub-pixel region (SPA2), and a third light-emitting element (LD3) located in a third sub-pixel region (SPA3).

[0118] Each of the light-emitting elements (LDs) may include a first electrode AE, an organic light-emitting portion EL, and a second electrode CE. The LDs can be electrically connected to the pixel circuitry of the corresponding pixel (e.g., ...). Figure 6 The pixel circuit PXC is shown in the figure.

[0119] The first electrode AE ​​can be provided (or formed) on the via layer VIA of the corresponding pixel. The first electrode AE ​​can be the anode electrode of the light-emitting element LD. The first electrode AE ​​can be electrically connected to the first terminal TE1 through a contact portion corresponding to the first electrode AE. According to some embodiments, the first electrode AE ​​can include an anode electrode corresponding to the first sub-pixel region to the third sub-pixel region SPA1, SPA2 and SPA3. The first electrode AE ​​can be patterned to correspond to the first sub-pixel region to the third sub-pixel region SPA1, SPA2 and SPA3.

[0120] The first electrode AE ​​can be made of a conductive material (or substance). The conductive material can include opaque metals. Opaque metals can include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), and their alloys. However, the material of the first electrode AE ​​can also include a transparent conductive material (or substance). Transparent conductive materials (or substances) can include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x Conductive oxides such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO), and conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT), etc., can be added to the display device (e.g., Figure 1 The display device shown in the figure (DD) is a separate conductive layer made of opaque metal that reflects light emitted from the light-emitting layer EML in the image display direction (or encapsulation layer TFE).

[0121] The pixel-defining layer (PDL) can define (or separate) the area where the organic light-emitting portion (EL) is located. The PDL can expose at least one area of ​​the first electrode (AE). The PDL can be an organic insulating layer made of organic material. According to some embodiments, the PDL can include a light-absorbing material or have a light absorber coated thereon to absorb light introduced from the outside. For example, the PDL can include a carbon-based black pigment. However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the PDL can be an inorganic insulating layer made of inorganic material.

[0122] The pixel defining layer (PDL) can be partially opened to include an opening exposing a region of the first electrode AE, and protrudes from the via layer (VIA) along the periphery of the emission region on the third-direction DR3. The pixel defining layer (PDL) can be located on the via layer (VIA) to define a region in which the organic light-emitting portion (EL) is housed while located on the first electrode AE. The organic light-emitting portion (EL) can be located on the first electrode AE ​​exposed by the opening in the pixel defining layer (PDL).

[0123] The organic light-emitting element (EL) can have a multilayer thin-film structure including a light-generating layer. The EL can emit one of red, green, and blue light, but embodiments according to this disclosure are not limited thereto. For example, the EL may include a white light-emitting layer that emits white light. The internal design of the EL can be varied depending on the color of the light to be emitted.

[0124] The second electrode CE can be located on the organic light-emitting portion EL and the pixel-defining layer PDL. The second electrode CE can be provided in a plate shape throughout the entire display area DA. The second electrode CE can be located on the outermost (or uppermost) part of the light-emitting element LD.

[0125] The second electrode CE can be a thin-film metal layer of a thickness sufficient to allow light emitted from the organic light-emitting portion EL to be transmitted through it. The second electrode CE can be formed of a metallic material to have a relatively thin thickness, or of a transparent conductive material. The second electrode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and is made transparent or translucent (or substantially transparent or translucent) to meet a transmittance value or threshold (e.g., a set or predetermined transmittance value or threshold). Accordingly, light emitted from the organic light-emitting portion EL located at the bottom of the second electrode CE can be emitted in the upper direction of the encapsulation layer TFE while passing through the second electrode CE.

[0126] The encapsulation layer TFE can be completely provided (or formed) over the second electrode CE. The encapsulation layer TFE can be in contact with the second electrode CE. Figure 9 The illustration shows an embodiment in which the encapsulation layer TFE is formed as a single layer on the second electrode CE. However, embodiments according to this disclosure are not limited thereto.

[0127] According to some embodiments, the encapsulation layer TFE can be formed as a single layer. The encapsulation layer TFE can have an encapsulation layer thickness TFE_T.

[0128] The encapsulation layer TFE according to this disclosure can be deposited using atomic layer deposition (ALD) (e.g., plasma-enhanced atomic layer deposition (PEALD)). The encapsulation layer TFE can have a thickness of 2000 nm or less (or, according to some embodiments, a thickness of 1000 nm or less).

[0129] According to some embodiments, the encapsulation layer thickness TFE_T can be from 10 nm to 2000 nm. According to some embodiments, the encapsulation layer thickness TFE_T can be from 10 nm to 1000 nm. According to some embodiments, the encapsulation layer thickness TFE_T can be from 100 nm to 2000 nm. According to some embodiments, the encapsulation layer thickness TFE_T can be from 100 nm to 1000 nm. According to some embodiments, the encapsulation layer thickness TFE_T can be from 150 nm to 1000 nm. When the encapsulation layer thickness TFE_T is greater than 2000 nm, there is a risk of reducing the light output efficiency of the display device DD. When the encapsulation layer thickness TFE_T is less than 10 nm, the light-emitting element LD may not be properly encapsulated. According to some embodiments, when the encapsulation layer thickness TFE_T is 1000 nm or less, the light output efficiency of the display device DD can be improved by 10% to 15% compared to display devices where the encapsulation layer thickness TFE_T is greater than 1000 nm.

[0130] The encapsulation layer thickness TFE_T can be the average thickness from the bottom surface to the top surface of the encapsulation layer TFE. The bottom surface of the encapsulation layer TFE can be the surface that contacts the display element layer DPL, and the top surface of the encapsulation layer TFE can be the surface that contacts the light control layer LCL.

[0131] The encapsulation layer TFE can be an inorganic layer comprising inorganic materials. The encapsulation layer TFE can protect the sub-pixels (SPX) from foreign matter such as dust particles. The encapsulation layer TFE may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO)x ), Hafnium oxide (HfO) x ) and titanium dioxide (TiO) x At least one of the following.

[0132] The light control layer LCL can be located on the encapsulation layer TFE. According to some embodiments, the bottom surface of the light control layer LCL can contact the top surface of the encapsulation layer TFE. The light control layer LCL may include a dam BNK, a first capping layer CAP1, a light control patterning layer CCL, and a low-refractive-index layer LRL.

[0133] The BNK layer can be located on the TFE layer. The BNK layer can be located in the first sub-pixel region to the third sub-pixel regions SPA1, SPA2, and SPA3 (or...). Figure 1 The first to third sub-pixels (SPX1, SPX2, and SPX3) shown are located between or within the boundaries between the first and third sub-pixel regions (SPA1, SPA2, and SPA3), and include openings that overlap with the first to third sub-pixel regions (SPA1, SPA2, and SPA3), respectively. For example, a desired type and desired number of light control pattern layers (CCLs) can be supplied to the space separated by the openings formed by the embankment (BNK).

[0134] The embankment BNK can define a first sub-pixel region to a third sub-pixel region SPA1, SPA2, and SPA3, and a non-emitting region NEA. The first sub-pixel region to the third sub-pixel region SPA1, SPA2, and SPA3 can be regions corresponding to an opening in the embankment BNK, and the non-emitting region NEA can be a region corresponding to the embankment BNK. For example, when viewed in a plane, the first sub-pixel region to the third sub-pixel region SPA1, SPA2, and SPA3 can be regions overlapping with an opening in the embankment BNK, and when viewed in a plane, the non-emitting region NEA can be a region overlapping with the embankment BNK. When viewed in a plane, the embankment BNK can surround the first sub-pixel region to the third sub-pixel region SPA1, SPA2, and SPA3.

[0135] The BNK can include organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB) resins. However, this disclosure is not necessarily limited thereto, and the BNK can include materials containing silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO)x ) and titanium dioxide (TiO) x Various inorganic materials.

[0136] The dammed BNK may include at least one light-shielding and reflective material. Accordingly, it can prevent or reduce light leakage between adjacent sub-pixels. For example, the dammed BNK may include black pigment, but this disclosure is not necessarily limited thereto.

[0137] The light control pattern layer CCL can be housed within the opening of the embankment BNK and located in the region overlapping with the first to third sub-pixel regions SPA1, SPA2, and SPA3. The light control pattern layer CCL may include a first wavelength conversion layer CCL1, a second wavelength conversion layer CCL2, and a light-transmitting layer TL, corresponding to the first to third sub-pixel regions SPA1, SPA2, and SPA3, respectively. The first wavelength conversion layer CCL1 may be located in the first sub-pixel region SPA1, the second wavelength conversion layer CCL2 may be located in the second sub-pixel region SPA2, and the light-transmitting layer TL may be located in the third sub-pixel region SPA3. The first wavelength conversion layer CCL1, the second wavelength conversion layer CCL2, and the light-transmitting layer TL may be in contact with the top surface of the encapsulation layer TFE.

[0138] According to some embodiments, the first to third sub-pixel regions SPA1, SPA2, and SPA3 may include first to third light-emitting elements LD1, LD2, and LD3 that emit light of the same color. For example, the first to third light-emitting elements LD1, LD2, and LD3 may emit light of a third color (or blue). A first wavelength conversion layer CCL1 and a second wavelength conversion layer CCL2, including color conversion particles QD (or quantum dot particles), are located in the first sub-pixel region SPA1 and the second sub-pixel region SPA2, respectively, and a light-transmitting layer TL is located in the third sub-pixel region SPA3, enabling the display of a full-color image.

[0139] The first wavelength conversion layer CCL1 and the second wavelength conversion layer CCL2 may include color conversion particles QD (or wavelength conversion particles). According to some embodiments, the first wavelength conversion layer CCL1 and the second wavelength conversion layer CCL2 may include color conversion particles QD for converting light of a third color (or in a third wavelength band) incident from the light-emitting element LD into light of a first color (or a specific color) (or in a first wavelength band) or a second color (or a specific color) (or in a second wavelength band) and emitting the converted light.

[0140] The first wavelength conversion layer CCL1 may include first color conversion particles for converting light of a third color emitted from the first light-emitting element LD1 into light of a first color (or red light). For example, the first wavelength conversion layer CCL1 may include a plurality of quantum dot particles QD dispersed in a matrix material (e.g., a predetermined matrix material) such as a base resin. The first quantum dot particles QD of the first wavelength conversion layer CCL1 may absorb blue light and emit red light by shifting the wavelength of the blue light according to energy conversion.

[0141] The second wavelength conversion layer CCL2 may include second color conversion particles for converting light of a third color emitted from the second light-emitting element LD2 into light of a second color (or green light). For example, the second wavelength conversion layer CCL2 may include a plurality of quantum dot particles QD dispersed in a matrix material such as a base resin (e.g., a set or predetermined matrix material). The second quantum dot particles QD of the second wavelength conversion layer CCL2 may absorb blue light and emit green light by shifting the wavelength of the blue light according to energy conversion.

[0142] A light-transmitting layer TL may be provided to effectively utilize the third color (or blue) light emitted from the third light-emitting element LD3. According to some embodiments, when the third light-emitting element LD3 is a blue light-emitting element that emits blue light and the third sub-pixel region SPA3 is a blue sub-pixel region, the light-transmitting layer TL may include at least one scatterer SCT to effectively utilize the light emitted from the third light-emitting element LD3.

[0143] In this disclosure, the distance between the second electrode CE and the light control pattern layer CCL can be from 10 nm to 2000 nm. According to some embodiments, the distance between the second electrode CE and the light control pattern layer CCL can be from 10 nm to 1000 nm. According to some embodiments, the distance between the second electrode CE and the light control pattern layer CCL can be from 100 nm to 2000 nm. According to some embodiments, the distance between the second electrode CE and the light control pattern layer CCL can be from 100 nm to 1000 nm. According to some embodiments, the distance between the second electrode CE and the light control pattern layer CCL can be from 150 nm to 1000 nm. The distance between the second electrode CE and the light control pattern layer CCL can be defined as the average distance between the top surface of the second electrode CE and the bottom surface of at least one of the first wavelength conversion layer CCL1, the second wavelength conversion layer CCL2, and the light-transmitting layer TL in a third-direction DR3.

[0144] The first capping layer CAP1 can be completely disposed above the embankment BNK and the light control patterning layer CCL. The first capping layer CAP1 can be in contact with the embankment BNK and the light control patterning layer CCL. The first capping layer CAP1 can prevent or reduce the penetration of contaminants such as moisture or foreign matter into the light control patterning layer CCL. The first capping layer CAP1 can include inorganic materials. For example, the first capping layer CAP1 can include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and titanium dioxide (TiO) x At least one of the following.

[0145] The first capping layer CAP1 can have a thickness of 100 nm to 1000 nm. When the thickness of the first capping layer CAP1 is less than 100 nm, it may increase the risk that moisture or foreign matter will penetrate into the diaphragm BNK and the light control pattern layer CCL. When the thickness of the first capping layer CAP1 is greater than 1000 nm, it excessively increases the thickness of the display device DD, and therefore may reduce the light output efficiency of the display device DD.

[0146] According to some embodiments, the display device DD may further include a protective layer separate from the encapsulation layer TFE for protecting the bottom of the light control pattern layer CCL. The protective layer for protecting the bottom of the light control pattern layer CCL may have the same thickness range as the first capping layer CAP1. For example, the protective layer for protecting the bottom of the light control pattern layer CCL may have a thickness of 100 nm to 1000 nm. The protective layer for protecting the bottom of the light control pattern layer CCL may include inorganic materials.

[0147] According to some embodiments, the low-refractive-index layer (LRL) may be located on the first capping layer CAP1. According to some embodiments, the LRL may have a refractive index of 1.1 to 1.4. According to some embodiments, the LRL may have a refractive index difference of 0.5 or greater with the layer below the LRL. The LRL may have a lower refractive index than the light control patterning layer CCL below the LRL. The LRL may have a higher refractive index than the color filter CF above the LRL. The LRL may adjust the path of light emitted from the light control patterning layer CCL (or the display element layer DPL). For example, the LRL may change the path of obliquely incident light to a direction perpendicular to the planarization layer OC. The LRL may comprise polymer materials and silicon-based materials.

[0148] According to some embodiments, the second capping layer CAP2 may be located on the low-refractive layer LRL. The second capping layer CAP2 can prevent or reduce the penetration of contaminants such as moisture or foreign matter into the low-refractive layer LRL. The second capping layer CAP2 may include inorganic materials.

[0149] According to this disclosure, the distance between the display element layer DPL and the light control layer LCL can be from 10 nm to 2000 nm. The distance between the display element layer DPL and the light control layer LCL can be defined as the distance from the top surface of the second electrode CE to the bottom surface of the light control pattern layer CCL. For example, the distance between the display element layer DPL and the light control layer LCL can be the distance between the second electrode CE and the light control pattern layer CCL (e.g., the average distance). According to some embodiments, the distance between the display element layer DPL and the light control layer LCL can be from 10 nm to 1000 nm. According to some embodiments, the distance between the display element layer DPL and the light control layer LCL can be from 100 nm to 2000 nm. According to some embodiments, the distance between the display element layer DPL and the light control layer LCL can be from 100 nm to 1000 nm. According to some embodiments, the distance between the display element layer DPL and the light control layer LCL can be from 150 nm to 1000 nm. According to some embodiments, when the distance between the display element layer DPL and the light control layer LCL is 1000nm, the light output efficiency of the display device DD can be improved by 10% to 15% compared with that of a display device DD in which the distance between the display element layer DPL and the light control layer LCL is greater than 1000nm.

[0150] According to some embodiments, the color filter layer CFL may be located on the light control layer LCL. According to some embodiments, the color filter layer CFL may be located on the second capping layer CAP2. The color filter layer CFL may include a color filter CF and a planarization layer OC. The color filter CF may include first color filters to third color filters CF1, CF2, and CF3 corresponding to the first to third sub-pixel regions SPA1, SPA2, and SPA3, respectively.

[0151] According to some embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be a red color filter, a green color filter, and a blue color filter, respectively, but this disclosure is not necessarily limited thereto.

[0152] According to some embodiments, a first color filter CF1 may be located on a second capping layer CAP2, corresponding to a first sub-pixel region SPA1, and allowing light emitted from a first light-emitting element LD1 and a first wavelength conversion layer CCL1 to be selectively transmitted via the first color filter CF1. For example, when viewed in a plane, the first color filter CF1 may overlap with the first sub-pixel region SPA1. According to some embodiments, the first color filter CF1 may overlap with the first wavelength conversion layer CCL1 on a third-direction DR3. The first color filter CF1 may include a color material for allowing light of a first color (or red) to be selectively transmitted via the first color filter CF1. For example, when the first sub-pixel region SPA1 is a red sub-pixel region, the first color filter CF1 may include a red color filter material.

[0153] According to some embodiments, a second color filter CF2 may be located on the second capping layer CAP2, corresponding to the second sub-pixel region SPA2, and allowing light emitted from the second light-emitting element LD2 and the second wavelength conversion layer CCL2 to be selectively transmitted via the second color filter CF2. For example, when viewed in a plane, the second color filter CF2 may overlap with the second sub-pixel region SPA2. According to some embodiments, the second color filter CF2 may overlap with the second wavelength conversion layer CCL2 on a third-direction DR3. The second color filter CF2 may include a color material for allowing light of a second color (or green) to be selectively transmitted via the second color filter CF2. For example, when the second sub-pixel region SPA2 is a green sub-pixel region, the second color filter CF2 may include a green color filter material.

[0154] According to some embodiments, a third color filter CF3 may be located on the second capping layer CAP2, corresponding to the third sub-pixel region SPA3, and allowing light emitted from the third light-emitting element LD3 and the light-transmitting layer TL to be selectively transmitted through the third color filter CF3. For example, when viewed in a plane, the third color filter CF3 may overlap with the third sub-pixel region SPA3. According to some embodiments, the third color filter CF3 may overlap with the light-transmitting layer TL on the third-direction DR3. The third color filter CF3 may include a color material for allowing light of a third color (or blue) to be selectively transmitted through the third color filter CF3. For example, when the third sub-pixel region SPA3 is a blue sub-pixel region, the third color filter CF3 may include a blue color filter material.

[0155] According to some embodiments, the second color filter CF2, the first color filter CF1, and the third color filter CF3 can be sequentially stacked on the third-direction DR3. For example, after the second color filter CF2 is set, the first color filter CF1 can be arranged to cover the second color filter CF2 in the non-emission region NEA. In addition, the third color filter CF3 can be set or formed after the first color filter CF1 is set or formed.

[0156] According to some embodiments, the planarization layer OC can be disposed above the first to third color filters CF1, CF2, and CF3. The planarization layer OC can cover the first to third color filters CF1, CF2, and CF3. The planarization layer OC is not particularly limited as long as it comprises a material with excellent planarization properties and excellent light transmittance. The planarization layer OC can comprise organic or inorganic materials. According to some embodiments, when the planarization layer OC comprises an organic material, it can comprise at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0157] According to some embodiments, the planarization layer OC can have a thickness of 1000 nm to 10000 nm. According to some embodiments, the planarization layer OC can have a thickness of 1500 nm to 10000 nm. When the planarization layer OC has a thickness of less than 1000 nm, the planarization characteristics may be relatively reduced. When the planarization layer OC has a thickness of more than 10000 nm, the thickness of the display device DD may be excessively increased, and the light output efficiency of the display device DD may be relatively reduced.

[0158] According to some embodiments, the display device DD may further include an anti-reflective (AR) film located on the planarization layer OC. The AR film may be located on the outermost portion of the display device DD. According to some embodiments, the display device DD may further include a stacked structure for reducing external light reflection from the display device DD on its outermost portion.

[0159] In the following text, reference will be made to Figure 10 The method of manufacturing the display device DD is described in more detail. Some descriptions that are repeated in the above sections may be omitted. Figure 10 This is a flowchart illustrating aspects of a method for manufacturing a display device according to some embodiments of the present disclosure. Although Figure 10 Various operations in a method of manufacturing a display device are illustrated, but the embodiments of this disclosure are not limited thereto, and according to some embodiments, the method of manufacturing a display device may include additional operations or fewer operations, or the order of operations may be changed without departing from the spirit and scope of the embodiments of this disclosure unless otherwise stated or implied.

[0160] refer to Figure 10 The method for manufacturing a display device DD may include operations S100 of forming a pixel circuit layer, S200 of forming a display element layer, S300 of forming an encapsulation layer, S400 of forming a light control layer, and S500 of forming a color filter layer.

[0161] In operation S100, which forms the pixel circuit layer, a pixel circuit layer comprising pixel circuitry for driving the light-emitting element LD can be formed (e.g., patterned) on the substrate SUB. The pixel circuit layer PCL can be formed (e.g., patterned) to include conductive layers and insulating layers located between the conductive layers.

[0162] According to some embodiments, components located on the substrate SUB can be formed (e.g., patterned) by using a common patterning process (e.g., photolithography, etc.) with a mask.

[0163] The operation S200 of forming the display element layer may include the operation of forming a pixel defining layer PDL and a light-emitting element LD. The operation of forming each of the light-emitting elements LD may include the operation of forming a first electrode AE, an organic light-emitting portion EL, and a second electrode CE.

[0164] A first electrode AE ​​can be formed (e.g., patterned) on the pixel circuit layer PCL. According to some embodiments, the first electrode AE ​​can be deposited on the pixel circuit layer PCL for etching, such that at least a portion of the pixel circuit layer PCL is exposed.

[0165] In this disclosure, unless a deposition process for forming (e.g., patterning) the components of the display device DD is described separately, at least one of sputtering, chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes can be used as processes for depositing the components of the display device DD. Similarly, unless a separate etching process for forming (e.g., patterning) the components of the display device DD is described separately, at least one of wet etching and dry etching processes can be used as processes for etching the components of the display device DD. However, embodiments according to this disclosure are not limited to specific examples.

[0166] A pixel defining layer (PDL) can be formed on a pixel circuit layer (PCL). The PDL can be deposited on the PCL and a first electrode (AE). The PDL can be etched to expose at least a portion of the first electrode (AE). The PDL can be etched to overlap with other portions of the first electrode (AE).

[0167] The organic light-emitting portion (EL) can be formed on the first electrode (AE). The organic light-emitting portion (EL) can be formed as a multilayer thin film structure having multiple light-generating layers.

[0168] The second electrode CE can be formed on the organic light-emitting portion EL. Alternatively, the second electrode CE can be integrally formed on the organic light-emitting portion EL. Or, the second electrode CE can be integrally formed in the light-emitting element LD.

[0169] The operation S300 of forming the encapsulation layer may include the operation of forming the encapsulation layer TFE on the display element layer DPL. The encapsulation layer TFE may be formed on the second electrode CE.

[0170] The operation S300 of forming the encapsulation layer may include the operation of depositing the encapsulation layer TFE using atomic layer deposition (ALD) (e.g., plasma enhanced atomic layer deposition (PEALD)), and the encapsulation layer TFE may have a thickness of 2000 nm or less (or, according to some embodiments, a thickness of 1000 nm or less).

[0171] The operation S400 of forming the light control layer may include the operation of forming the light control layer LCL on the encapsulation layer TFE. The operation S400 of forming the light control layer may include the operation of forming the dam BNK, the first capping layer CAP1, the light control patterning layer CCL, the low refractive index layer LRL, and the second capping layer CAP2.

[0172] The operation S500 of forming the color filter layer may include forming a color filter CF and a planarization layer OC on the light control layer LCL. In the operation S500 of forming the color filter layer, the color filter layer CFL may be formed on the second capping layer CAP2. The color filter CF may be formed on the second capping layer CAP2. The planarization layer OC may be formed on the color filter CF.

[0173] Figure 11 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment. Figure 12 It is a diagram. Figure 11 The electronic device shown is a schematic diagram of an example of a smartphone. Figure 13 It is a diagram. Figure 11 The electronic device is a schematic diagram of an example of a tablet computer.

[0174] refer to Figures 11 to 13 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device DD. The electronic device 1000 may further include various ports for communicating with a video card, sound card, memory card, USB device, or other systems. In embodiments, such as Figure 12 As shown, the electronic device 1000 may be a smartphone 2000. In an embodiment, as... Figure 13 As shown, electronic device 1000 may be tablet computer 3000. However, the foregoing example is illustrative, and electronic device 1000 is not necessarily limited to the foregoing example. For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, vehicle navigation device, computer monitor, laptop computer, or head-mounted display device, etc.

[0175] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. Processor 1010 can be connected to other components via address buses, control buses, and data buses. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0176] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can function as the working memory and / or buffer memory of the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0177] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include a solid-state drive (SSD), hard disk drive (HDD), or CD-ROM, etc.

[0178] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0179] The power supply 1050 can supply the power required to operate the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, the power supply 1050 can supply power to the display device 1060.

[0180] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0181] According to some embodiments of this disclosure, a display device and a method of manufacturing the display device can be provided, wherein the light output efficiency of the display device is relatively improved and the thickness of the display device is relatively reduced.

[0182] Some aspects of embodiments have been disclosed herein, and although specific terminology has been used, it is used in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art upon filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the claims and their equivalents.

Claims

1. A display device, comprising: Display element layer, including light-emitting elements; An encapsulation layer is formed as a single layer on the display element layer; as well as A light control layer, overlapping the encapsulation layer, is included. The light control layer comprises a light control pattern layer, which further comprises a first wavelength conversion layer, a second wavelength conversion layer, and a light-transmitting layer. The light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion. The distance between the top surface of the second electrode and the bottom surface of the light control pattern layer is in the range of 10 nm to 2000 nm.

2. The display device according to claim 1, wherein, The encapsulation layer has a thickness ranging from 10 nm to 1000 nm.

3. The display device according to claim 1, wherein The bottom surface of the encapsulation layer is in contact with the second electrode, and The top surface of the encapsulation layer is in contact with the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer.

4. The display device according to claim 1, wherein The optical control layer further includes: A first capping layer on the light control pattern layer and a low-refractive layer on the first capping layer. The first capping layer has a thickness in the range of 100 nm to 1000 nm, and The low-refractive-index layer has a refractive index in the range of 1.1 to 1.4, which is less than that of the light control pattern layer.

5. The display device according to claim 1, further comprising: A color filter layer is located on the light control layer; as well as An anti-reflective film is placed on the color filter layer. The color filter layer includes a first color filter, a second color filter, and a third color filter, as well as a planarization layer above the first color filter, the second color filter, and the third color filter. The first color filter allows red light to be selectively transmitted through it. The second color filter allows green light to be selectively transmitted through it. The third color filter allows blue light to be selectively transmitted through it. The planarization layer has a thickness in the range of 1000 nm to 10000 nm.

6. The display device according to claim 1, further comprising: The first sub-pixel region is configured to emit light of the first color; The second sub-pixel region is configured to emit light of the second color; The third sub-pixel region is configured to emit light of the third color; as well as The embankment is located between the first sub-pixel region and the third sub-pixel region. The first wavelength conversion layer is located in the first sub-pixel region. The second wavelength conversion layer is located in the second sub-pixel region, and The light-transmitting layer is located in the third sub-pixel region.

7. A display device, comprising: A display area having pixels, the display area including a first sub-pixel area, a second sub-pixel area and a third sub-pixel area; The display element layer includes light-emitting elements that form the pixels; Encapsulation layer, on the display element layer; as well as The light control layer overlaps with the display element layer. The light-emitting element includes a first electrode, an organic light-emitting portion on the first electrode, and a second electrode on the organic light-emitting portion. The light control layer includes a light control pattern layer, which comprises a first wavelength conversion layer in the first sub-pixel region, a second wavelength conversion layer in the second sub-pixel region, and a light-transmitting layer in the third sub-pixel region. The distance between the top surface of the second electrode and the bottom surface of the light control pattern layer is in the range of 10 nm to 1000 nm.

8. The display device of claim 7, wherein, The encapsulation layer is formed as a single layer. The bottom surface of the encapsulation layer is in contact with the second electrode, and The top surface of the encapsulation layer is in contact with the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer.

9. The display device according to claim 7, wherein The optical control layer further includes: A first capping layer is placed on the light control pattern layer; and A low-refractive layer is placed on the first capping layer, and The display device further includes: Color filter layer, on the light control layer, The color filter layer includes a first color filter, a second color filter, and a third color filter, as well as a planarization layer above the first color filter, the second color filter, and the third color filter. The first color filter overlaps with the first sub-pixel region. The second color filter overlaps with the second sub-pixel region, and The third color filter overlaps with the third sub-pixel region, and The planarization layer has a thickness in the range of 1500 nm to 10000 nm. The low-refractive-index layer has a refractive index in the range of 1.1 to 1.4, which is lower than that of the light control pattern layer. The first capping layer is in contact with the light control pattern layer. The first capping layer has a thickness in the range of 100 nm to 1000 nm.

10. An electronic device comprising: A processor used to provide input image data; as well as The display device according to any one of claims 1-9 is used to display an image based on the input image.

Images