Electronic package

Abstract

An electronic package is mainly characterized in that one side of a circuit structure is provided with an electrical bridging element with a wiring part, the other side of the circuit structure is provided with a plurality of electronic elements, the wiring part comprises at least one magnetic layer and a coil type inductor formed on the magnetic layer, and the coil type inductor is arranged on the magnetic layer. The electrical bridging element is integrated in the electronic package as a power management chip, so that the distance of power supplied to the electronic element can be shortened, and the efficiency of the electronic package can be effectively improved.

Description

Technical Field

[0001] This application relates to a semiconductor packaging process, and more particularly to an electronic package that integrates multiple chips. Background Technology

[0002] With the evolution of semiconductor packaging technology, different packaging technologies have been developed to improve electrical performance and save packaging space. For example, in conjunction with the significantly increased number of input / output ports on various chips, integrated circuits with different functions can be integrated into a single package structure. This packaging method can leverage the heterogeneous integration characteristics of System-in-Package (SiP) to integrate electronic components with different functions, such as memory, central processing unit, graphics processor, and image application processor, through stacking design. It is suitable for use in various thin and light electronic products.

[0003] Figure 1 This is a three-dimensional schematic diagram of an existing semiconductor package 1 applied to a circuit board 6. (Example) Figure 1 As shown, the circuit board 6 is equipped with at least one power management IC 60, a capacitor 61 and an inductor 62 to serve as a voltage regulator module (VRM) 6a.

[0004] However, in the existing semiconductor package 1, its power supply comes from the voltage regulation module 6a, which keeps a certain distance from the power management chip 60. This results in the power management chip 60 supplying power (such as circuit 63) to the semiconductor package 1 at too long a distance, causing the delay time to be too long. Therefore, it is difficult to improve the performance of the semiconductor package 1.

[0005] Furthermore, individual components of the voltage regulation module 6a, such as the power management chip 60, capacitor 61, and inductor 62, are respectively located on the circuit board 6, thus occupying a certain area of ​​the circuit board 6. This makes it difficult to reduce the size of the circuit board 6, making it difficult for the final product to meet the miniaturization requirements.

[0006] Therefore, how to overcome the various shortcomings of existing technologies is a technical problem that all sectors urgently need to solve. Utility Model Content

[0007] In view of the various deficiencies of the prior art, this application provides an electronic package, including: a circuit structure; an electrical bridging element having a wiring portion, which is attached to one side of the circuit structure and electrically connected to the circuit structure, wherein the wiring portion includes at least one magnetic layer and a coil inductor formed on the magnetic layer; and a plurality of electronic components, which are attached to the other side of the circuit structure and electrically connected to the circuit structure, such that the plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

[0008] This application also provides a method for manufacturing an electronic package, comprising: providing an electrical bridging element having a wiring portion, wherein the wiring portion includes at least one magnetic layer and a coil inductor formed on the magnetic layer; attaching the electrical bridging element to one side of a circuit structure and electrically connecting the circuit structure; and attaching a plurality of electronic components to the other side of the circuit structure and electrically connecting the circuit structure, such that the plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

[0009] In the aforementioned electronic package and its manufacturing method, an intermediary element is further provided on one side of the circuit structure, allowing the multiple electronic components to be electrically connected to the intermediary element through the circuit structure. For example, the intermediary element has multiple through conductive vias.

[0010] In the aforementioned electronic package and its manufacturing method, the coil inductor has a first inductor segment and a second inductor segment respectively disposed on opposite sides of the magnetic layer, such that the first inductor segment and the second inductor segment are interconnected by a plurality of inductor pillars to form the coil inductor around the magnetic layer.

[0011] In the aforementioned electronic package and its manufacturing method, the electrical bridging element further includes a semiconductor substrate having a plurality of conductive vias, so that the wiring portion is formed on the semiconductor substrate and electrically connected to the plurality of conductive vias.

[0012] As can be seen from the above, the electronic package of this application mainly forms a magnetic layer in the electrical bridging element, and forms a coil-type inductor around the magnetic layer, so that the electrical bridging element is integrated into the electronic package as a power management chip or integrated voltage regulator. Therefore, the distance of power supply to the electronic component can be shortened. Thus, compared with the prior art, the electronic package of this application requires a shorter power supply distance, thereby shortening the delay time and effectively improving the performance of the electronic package.

[0013] Furthermore, by integrating the electrical bridging element as a power management chip or integrated voltage regulator into the electronic package, the area occupied on the wiring board can be reduced, thereby reducing the size of the wiring board. Therefore, compared with the prior art, the electronic package of this application can reduce the size of the circuit board, so that the final product meets the miniaturization requirements. Attached Figure Description

[0014] Figure 1 This is a three-dimensional schematic diagram of an existing semiconductor package being applied to a circuit board.

[0015] Figures 2A to 2D This is a cross-sectional schematic diagram illustrating the manufacturing method of the electrical bridging element of this application.

[0016] Figure 2Efor Figure 2D A partial top view diagram.

[0017] Figures 3A to 3F This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.

[0018] Figure 4 for Figure 3F A cross-sectional view of the application.

[0019] Explanation of reference numerals in the attached figures

[0020] 1 Semiconductor package

[0021] 2 Electrical bridging elements

[0022] 2a Wiring section

[0023] 20 Semiconductor substrates

[0024] 20a First side

[0025] 20b Second side

[0026] 200, 310 conductive vias

[0027] 21 First wiring structure

[0028] 210, 300 insulation layers

[0029] 22 Second wiring structure

[0030] 220 magnetic layer

[0031] 23 Protective Layer

[0032] 24-coil inductor

[0033] 25 First conductive layer

[0034] 250 First Line Section

[0035] 251 First Inductor Section

[0036] 26 Second conductive layer

[0037] 260 Second Line Section

[0038] 261 Second Inductor Section

[0039] 262 Inductor Posts

[0040] 27, 29, 340 conductive bumps

[0041] 270 Undermount metal layer

[0042] 28 Protective Layer

[0043] 3 Electronic Packages

[0044] 3a Intermediate Component

[0045] 30 Load-bearing structure

[0046] 301 Wiring Layer

[0047] 31 Intermediary Board

[0048] 311 First Conductor

[0049] 312 Second conductor

[0050] 313 Protective Film

[0051] 314 Solder Material

[0052] 32 Line Department

[0053] 320 passivation layer

[0054] 321 Conductive trace

[0055] 33 Conductive pillars

[0056] 34 Electronic Components

[0057] 341,43 base rubber

[0058] 35 coating layers

[0059] 35a First Surface

[0060] 35b Second Surface

[0061] 36. Circuit Structure

[0062] 360 dielectric layer

[0063] 361 Line Layer

[0064] 37 Conductive Components

[0065] 370 Insulation Protection Layer

[0066] 38 encapsulation layer

[0067] 39 Auxiliary Components

[0068] 4. Wiring Carrier Board

[0069] 40 welding balls

[0070] 400 electrical contacts

[0071] 41 Heat sink

[0072] 42 Electrical functional components

[0073] 6a Voltage Regulation Module

[0074] 6 Circuit Boards

[0075] 60 power management chips

[0076] 61 capacitors

[0077] 62 Inductors

[0078] 63 Circuit

[0079] 9. Support plate

[0080] 90 release layer

[0081] 91 Adhesive layer

[0082] S-shaped cutting path. Detailed Implementation

[0083] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0084] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0085] Figures 2A to 2D This is a cross-sectional schematic diagram illustrating the fabrication method of the electrical bridging element in the semiconductor package of this application. In this embodiment, the electrical bridging element (bridge die) 2 serves as a power management IC or an integrated voltage regulator (IVR).

[0086] like Figure 2AAs shown, a semiconductor substrate 20 is provided, having a first side 20a and a second side 20b opposite to each other, and the semiconductor substrate 20 has a plurality of conductive vias 200, such as through silicon vias (TSVs), connecting the first side 20a and the second side 20b, so that one end face of the conductive via 200 is exposed on the first side 20a, while the other end face is coupled with a conductive bump 27.

[0087] In this embodiment, the conductive bump 27 includes copper pillars and / or solder balls, which are connected to the conductive via 200 via an underbump metallurgy (UBM) 270. For example, a protective layer 28 exposing the conductive via 200 can be formed on the second side 20b of the semiconductor substrate 20 first, and then the underbump metallurgy 270 can be formed on the end face of the conductive via 200 to form the conductive bump 27 on the underbump metallurgy 270, so that the conductive bump 27 protrudes from the second side 20b of the semiconductor substrate 20.

[0088] like Figure 2B As shown, a first wiring structure 21 electrically connecting the conductive vias 200 is formed on the first side 20a of the semiconductor substrate 20.

[0089] In this embodiment, the first wiring structure 21 includes an insulating layer 210 and a first conductive layer 25 disposed on the insulating layer 210 and electrically connected to the conductive vias 200, such as a redistribution layer (RDL). For example, the first conductive layer 25 is formed of copper, and the insulating layer 210 is formed of materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0090] Furthermore, the first conductive layer 25 has a first line segment 250 and a first inductor segment 251.

[0091] like Figure 2C As shown, a second wiring structure 22 electrically connected to the first wiring structure 21 is formed on the first wiring structure 21.

[0092] In this embodiment, the second wiring structure 22 includes a magnetic layer 220 and a second conductive layer 26 disposed on the magnetic layer 220 and electrically connected to the first conductive layer 25. For example, the material forming the second conductive layer 26 is copper, and the material forming the magnetic layer 220 is such as a magnetic epoxy molding compound (EMC), a magnetic polyimide (PI), or other magnetic dielectric materials.

[0093] Furthermore, the second conductive layer 26 has a second line segment 260 electrically connected to the first line segment 250, and a second inductor segment 261 corresponding to the first inductor segment 251. For example, the first inductor segment 251 and the second inductor segment 261 are interconnected through multiple inductor posts 262 to form a coil, thereby cooperating with the magnetic layer 220 to form a coil-type inductor 24, such as... Figure 2E As shown.

[0094] like Figure 2D As shown, a protective layer 23 is formed on the second wiring structure 22 so that the second line segment 260 of the second conductive layer 26 is exposed on the protective layer 23 for bonding with the conductive bump 29. The first wiring structure 21 and the second wiring structure 22 can be regarded as a wiring part 2a.

[0095] In this embodiment, the conductive bump 29 includes copper pillars and / or solder balls, and it should be understood that the number of layers of the wiring portion 2a can be designed as needed and is not limited to the above.

[0096] Figures 3A to 3F This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.

[0097] like Figure 3A As shown, at least one intermediate element 3a and at least one such intermediate element are provided. Figure 2D The electrical bridging element 2 shown is a bearing structure 30 disposed on a bearing plate 9, and a plurality of conductive pillars 33 are formed on the bearing structure 30.

[0098] In this embodiment, the intermediate element 3a includes an intermediate plate 31, a circuit portion 32, a plurality of first conductors 311 formed on the intermediate plate 31, and a plurality of second conductors 312 formed on the circuit portion 32 and electrically connected to the circuit portion 32, and the plurality of first conductors 311 are covered by a protective film 313.

[0099] The intermediate plate 31 is a silicon substrate and has a plurality of conductive through holes 310, such as through-silicon vias (TSVs), through the intermediate plate 31 to electrically connect the circuit section 32 to the plurality of first conductors 311.

[0100] The circuit portion 32 includes at least one passivation layer 320 and a conductive trace 321 bonded to the passivation layer 320, so that the conductive trace 321 electrically connects the conductive via 310 and the plurality of second conductors 312. It should be understood that there are many types of intermediate elements 3a and there is no particular limitation.

[0101] The first conductor 311 and the second conductor 312 are metal pillars such as copper pillars, and the protective film 313 is an insulating film or polyimide (PI) material, which does not expose the first conductor 311.

[0102] Furthermore, the carrier structure 30 includes at least one insulating layer 300 and at least one wiring layer 301 disposed on the insulating layer 300. For example, the wiring layer 301 is made of copper, and the insulating layer 300 is made of dielectric materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others.

[0103] Furthermore, the carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 are sequentially formed by coating, so that the carrier structure 30 is disposed on the adhesive layer 91.

[0104] In addition, the conductive post 33 is disposed on the wiring layer 301 and electrically connected to the wiring layer 301, and the material forming the conductive post 33 is a metal material such as copper or solder material.

[0105] like Figure 3B As shown, the electrical bridging element 2 and the intermediate element 3a are disposed on the supporting structure 30.

[0106] In this embodiment, the electrical bridging element 2 is disposed on the carrier structure 30 through its wiring portion 2a, so that the conductive bump 29 is electrically connected to the wiring layer 301, and the intermediary element 3a is bonded to the carrier structure 30 with its second conductor 312 through solder material 314, so that the second conductor 312 is electrically connected to the wiring layer 301.

[0107] like Figure 3CAs shown, a covering layer 35 is formed on the support structure 30 to cover the electrical bridging element 2, the intermediate element 3a, and the conductive pillars 33. The covering layer 35 has opposing first surfaces 35a and second surfaces 35b, and it is bonded to the support structure 30 with the first surface 35a. Next, a circuit structure 36 is formed on the second surface 35b of the covering layer 35 to electrically connect the conductive pillars 33, the electrical bridging element 2, and the intermediate element 3a.

[0108] In this embodiment, the covering layer 35 is an insulating material, such as an epoxy resin encapsulant, which can be formed on the support structure 30 by lamination or molding.

[0109] Furthermore, a leveling process can be used to make the second surface 35b of the coating layer 35 flush with the end face of the conductive post 33, the surface of the conductive bump 27, the surface of the protective film 313, and the surface of the first conductor 311, so that the conductive post 33, the conductive bump 27, the protective film 313, and the first conductor 311 are exposed on the second surface 35b of the coating layer 35. For example, a grinding process can be used to remove part of the material of the conductive post 33, the conductive bump 27, the protective film 313, the first conductor 311, and the coating layer 35 to perform the leveling process.

[0110] Furthermore, the circuit structure 36 includes multiple dielectric layers 360 and multiple circuit layers 361 disposed on the dielectric layers 360, such as redistribution layers (RDLs). The outermost dielectric layer 360 can serve as a solder resist layer, allowing the outermost circuit layer 361 to be exposed to the solder resist layer. Alternatively, the circuit structure 36 may also include only a single dielectric layer 360 and a single circuit layer 361.

[0111] In addition, the material forming the circuit layer 361 is copper, and the material forming the dielectric layer 360 is a dielectric material such as poly(p-diazole)benzene (PBO), polyimide (PI), prepreg (PP) or others.

[0112] like Figure 3D As shown, multiple electronic components 34 are connected on the outermost circuit layer 361 of the circuit structure 36. These electronic components 34 can be electrically connected to each other through the circuit structure 36 and the electrical bridging element 2, and then the electronic components 34 are covered by an encapsulation layer 38.

[0113] The electronic component 34 can be an active component, a passive component, or a combination of both. The active component can be, for example, a semiconductor wafer, and the passive component can be, for example, a resistor, a capacitor, or an inductor. For example, the intermediary element 3a can also serve as an electrical bridging element, allowing the electronic components 34 to be electrically connected to each other through the intermediary element 3a.

[0114] In this embodiment, the electronic component 34 is a semiconductor wafer, which is disposed on the circuit layer 361 and electrically connected to the circuit layer 361 by means of multiple conductive bumps 340 made of materials such as solder, and the conductive bumps 340 are covered with a primer 341; or, the electronic component 34 can be electrically connected to the circuit layer 361 by means of multiple bonding wires (not shown); or it can be electrically connected to the circuit layer 361 by means of conductive materials such as conductive adhesive or solder (not shown). However, the method of electrically connecting the electronic component 34 to the circuit layer 361 is not limited to the above.

[0115] Furthermore, the encapsulation layer 38 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin, which can be formed on the circuit structure 36 by lamination or molding. It should be understood that the material forming the encapsulation layer 38 may be the same as or different from the material of the covering layer 35.

[0116] Alternatively, the encapsulation layer 38 may cover the base adhesive 341, but the base adhesive 341 may not be formed, and the conductive bump 340 may be directly covered by the encapsulation layer 38.

[0117] like Figure 3E As shown, the support plate 9 and its release layer 90 and adhesive layer 91 are removed to expose the support structure 30.

[0118] In this embodiment, a plurality of conductive elements 37, such as solder balls, are formed on the support structure 30, and the conductive elements 37 are electrically connected to the wiring layer 301. For example, an insulating protective layer 370, such as a solder resist layer, can be formed on the support structure 30 first, and the insulating protective layer 370 has a plurality of openings so that the wiring layer 301 is exposed through the openings for bonding C4 bump-sized conductive elements 37.

[0119] Furthermore, at least one auxiliary element 39 may be provided on a portion of the conductive element 37 on the support structure 30, so that the auxiliary element 39 is electrically connected to the wiring layer 301 through the conductive element 37. For example, the auxiliary element 39 may be an active element, a passive element, or a combination of both, wherein the active element is, for example, a semiconductor wafer, and the passive element is, for example, a resistor, a capacitor, and an inductor.

[0120] Alternatively, a leveling process, such as grinding, can be used to remove part of the material of the encapsulation layer 38, so that the upper surface of the encapsulation layer 38 is flush with the upper surface of the electronic component 34, thereby exposing the electronic component 34 to the encapsulation layer 38.

[0121] like Figure 3F As shown, along as Figure 3E The cutting path S shown is used for a single-piece cutting process to obtain the electronic package 3.

[0122] In this embodiment, the electronic package 3 can be connected to the upper side of a wiring carrier 4 via the conductive elements 37, such as... Figure 4 As shown, the conductive components 37 are then covered with a base adhesive 43. For example, the wiring carrier 4 is an organic material substrate (such as a packaging substrate with a core layer and circuitry or a coreless packaging substrate with circuitry) or an inorganic material substrate (such as a silicon substrate).

[0123] Furthermore, at least one heat sink 41 and / or an electrical functional component 42 can be configured on the upper side of the wiring carrier 4 as needed, and the lower side of the wiring carrier 4 can be connected to an electronic device (not shown) such as a circuit board through multiple solder balls 40, so that the wiring carrier 4 is electrically connected to the electronic device.

[0124] Furthermore, the electrical functional element 42 is an active element, a passive element, or a combination thereof, and is electrically connected to the electrical contact 400 of the wiring carrier board 4. The active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor.

[0125] Therefore, this application mainly forms the magnetic layer 220 in the electrical bridging element 2, so that the first inductor segment 251 and the second inductor segment 261 form a coil inductor 24 around the magnetic layer 220. This allows the electrical bridging element 2 to be integrated into the electronic package 3 as a power management chip (Power Management IC) or an integrated voltage regulator (IVR). This shortens the distance of power supply to the electronic component 34. Therefore, compared with the prior art, the electronic package 3 of this application requires a shorter power supply distance, thus shortening the delay time and effectively improving the performance of the electronic package 3.

[0126] Furthermore, by integrating the electrical bridging element 2 as a power management IC or an integrated voltage regulator (IVR) into the electronic package 3, the area occupied by the wiring carrier 4 is reduced, thereby reducing the size of the wiring carrier 4. Therefore, compared with the prior art, the electronic package 3 of this application can reduce the size of the circuit board, so that the final product meets the miniaturization requirements.

[0127] This application provides an electronic package 3, which includes: a circuit structure 36 having opposite sides, an electrical bridging element 2 having a wiring portion 2a, and a plurality of electronic components 34.

[0128] The electrical bridging element 2 is attached to one side of the circuit structure 36 and electrically connected to the circuit structure 36. The wiring portion 2a includes at least one magnetic layer 220 and a coil inductor 24 formed on the magnetic layer 220.

[0129] The electronic component 34 is attached to the other side of the circuit structure 36 and electrically connected to the circuit structure 36, so that the multiple electronic components 34 are electrically connected to each other through the circuit structure 36 and the electrical bridging element 2.

[0130] In one embodiment, an intermediary element 3a is further provided on one side of the circuit structure 36, so that the plurality of electronic components 34 are electrically connected to the intermediary element 3a through the circuit structure 36. For example, the intermediary element 3a has a through conductive via 310.

[0131] In one embodiment, the coil inductor 24 has a first inductor segment 251 and a second inductor segment 261 respectively disposed on opposite sides of the magnetic layer 220, such that the first inductor segment 251 and the second inductor segment 261 are interconnected by a plurality of inductor posts 262, so as to form the coil inductor 24 around the magnetic layer 220.

[0132] In one embodiment, the electrical bridging element 2 further includes a semiconductor substrate 20 having a plurality of conductive vias 200, so that the wiring portion 2a is formed on the semiconductor substrate 20 and electrically connected to the conductive vias 200.

[0133] In summary, the electronic package of this application, by forming the magnetic layer in the electrical bridging element and having the first inductor segment and the second inductor segment surround the magnetic layer to form a coil-type inductor, integrates the electrical bridging element as a power management chip or integrated voltage regulator into the electronic package. This shortens the distance of power supply to the electronic component, thus requiring a shorter power supply distance and reducing latency, thereby effectively improving the performance of the electronic package.

[0134] Furthermore, by integrating the electrical bridging element as a power management chip or integrated voltage regulator into the electronic package, the area occupied on the wiring board is reduced, thereby reducing the size of the wiring board. Therefore, the electronic package of this application can reduce the size of the circuit board, enabling the final product to meet the miniaturization requirements.

[0135] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.

Claims

1. An electronic package, characterized by include: Line structure; An electrical bridging element having a wiring portion is attached to one side of the circuit structure and electrically connected to the circuit structure, wherein the wiring portion includes a magnetic layer and a coil inductor formed on the magnetic layer; as well as Multiple electronic components are combined to the other side of the circuit structure and electrically connected to the circuit structure, so that the multiple electronic components are electrically connected to the electrical bridging element through the circuit structure.

2. The electronic package of claim 1, wherein, An intermediary element is also provided on one side of the circuit structure, allowing the multiple electronic components to be electrically connected to the intermediary element through the circuit structure.

3. The electronic package of claim 2, wherein, The interposer has multiple through-hole conductive vias.

4. The electronic package of claim 1, wherein, The coil inductor has a first inductor segment and a second inductor segment respectively disposed on opposite sides of the magnetic layer, such that the first inductor segment and the second inductor segment are interconnected by a plurality of inductor posts, so as to form the coil inductor around the magnetic layer.

5. The electronic package of claim 1, wherein, The electrical bridging element further includes a semiconductor substrate having multiple conductive vias, such that the wiring portion is formed on the semiconductor substrate and electrically connected to the multiple conductive vias.

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