Front ultrafast standard frequency pS-level synchronous conditioning circuit
By using a pre-amplified ultra-fast standard frequency pS-level synchronous conditioning circuit, and utilizing rectification filtering and high-speed comparators to quickly detect power changes, combined with a π-decay network composed of high-precision resistors and a pS-level delay module, the frequency instability caused by power attenuation and interference in the traditional synchronous mode is solved, achieving nanosecond-level fast compensation and stable clock source output.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU JINNUOXIN HIGH-TECH CO LTD
- Filing Date
- 2025-05-19
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional external reference synchronization modes are susceptible to power attenuation and interference when connecting devices, resulting in unstable reference frequencies. Furthermore, post-compensation methods require microsecond-level time and cannot provide a stable clock source.
It adopts a pre-amplified ultra-fast standard frequency pS-level synchronous conditioning circuit, and realizes the pre-compensation of the signal through the combination of power divider module, delay module, programmable attenuation module, rectifier circuit, high-speed comparator module, low noise amplifier module and FPGA. It uses rectification filtering and high-speed comparator to quickly detect power changes. The programmable attenuation module adopts a π attenuation network composed of high-precision resistors, and the delay module adopts ps-level precise delay.
It achieves nanosecond-level fast detection and compensation, ensuring the long-term stability and accuracy of the external reference and standard frequency output, avoiding signal loss, and providing a continuous and stable clock source.
Smart Images
Figure CN224154187U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of frequency conditioning technology, specifically to a front-mounted ultra-fast standard frequency pS-level synchronous conditioning circuit. Background Technology
[0002] In the field of time synchronization, devices tame their local temperature-controlled crystal oscillators by receiving a standard frequency (e.g., 10MHz) from a higher-level source. When the external reference frequency is valid, the local frequency synchronizes with the external reference; when the external reference is invalid, the module enters a time-keeping mode. Currently, traditional external reference synchronization modes primarily rely on receiving relatively stable external frequency signals. However, because devices are connected via RF coaxial cables, the power is prone to attenuation or repeated fluctuations due to interference. While traditional control circuits can compensate through adaptive circuits, they often employ a post-compensation method, requiring microseconds of time for acquisition and compensation. This results in a period of reference instability, preventing the provision of a stable clock source for the next-level devices. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a front-mounted ultra-fast standard frequency pS-level synchronous conditioning circuit.
[0004] The objective of this utility model is achieved through the following technical solution:
[0005] This utility model discloses a pre-amplified ultra-fast standard frequency pS-level synchronous conditioning circuit, comprising: a power divider module, a delay module, a programmable attenuation module, a rectifier circuit, a high-speed comparator module, a low-noise amplifier module, and an FPGA; the input terminal of the power divider module is connected to an external input signal, the output terminal of the power divider module is connected to the input terminal of the delay module, the output terminal of the delay module is connected to the input terminal of the programmable attenuation module, the output terminal of the programmable attenuation module is connected to the input terminal of the low-noise amplifier module, the output terminal of the power divider module is also connected to the input terminal of the rectifier circuit, the output terminal of the rectifier circuit is connected to the input terminal of the high-speed comparator module, the output terminal of the high-speed comparator module is connected to the input terminal of the programmable attenuation module, the output terminal of the programmable attenuation module is connected to the input terminal of the low-noise amplifier module, and the output terminal of the low-noise amplifier module is connected to the FPGA.
[0006] Furthermore, it also includes a CPU and a crystal oscillator. The CPU is connected to the FPGA, and the output of the CPU is also connected to the input of the crystal oscillator. The output of the crystal oscillator is connected to the input of the FPGA, and the crystal oscillator outputs signals to external modules.
[0007] Preferably, the power divider module includes a connector XS14 and a first logic chip N11. One end of the connector is connected to an external signal input signal. The other end of the connector XS14 is connected to a first capacitor C121 and a first resistor R307 in sequence, and then connected to one end of the first logic chip N11. The other end of the first logic chip N11 is connected to a delay module and a rectifier circuit, respectively.
[0008] Preferably, the delay module includes a delay chip U1, one end of which is connected to the first logic chip N11, and the other end of which is connected to the second resistor R406 and then to the programmable attenuation module.
[0009] Preferably, the programmable attenuation module includes a second logic chip N2 and an analog switch chip D17. The input terminal of the second logic chip N2 is connected to the delay chip U1. The first output terminal of the second logic chip N2 is connected to the normally closed pin of the analog switch chip D17 after being connected in series with the first capacitor C112, the third resistor R403, and the second capacitor C113. The second output terminal of the second logic chip N2 is connected to the normally open pin of the analog switch chip D17 after being connected in series with the fourth resistor R404, the fifth resistor R149, and the third capacitor C29. The output terminal of the analog switch chip D17 is connected to the low noise amplifier module after being connected in series with the sixth resistor R341, the seventh resistor R393, and the fourth capacitor C115.
[0010] Preferably, the rectifier circuit includes a bidirectional TVS diode V37, one end of which is connected to the first logic chip N11, and the other end of which is connected to the high-speed comparator module.
[0011] Preferably, the high-speed comparator module includes a first high-speed comparator chip U4A and a second high-speed comparator chip U4B. The other end of the bidirectional TVS diode V37 is connected to the eighth resistor R575, and then connected to one end of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B, respectively. The other end of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B is connected to the ninth resistor R337, and then connected to the analog switch chip D17.
[0012] Preferably, the low-noise amplifier module includes amplifier N9. One end of amplifier N9 is connected to the output terminal of analog switch chip D17. The other end of amplifier N9 is connected in series with tenth resistor R398, fourth capacitor C116, eleventh resistor R155 and fifth capacitor C110, and then connected to one end of inverter chip D10. The other end of inverter chip D10 is connected in series with twelfth resistor R905 and then connected to FPGA.
[0013] The beneficial effects of this utility model are:
[0014] 1) The power detection method adopted in this utility model is to compare the rectified and filtered power with a high-speed comparator. The voltage comparison point can be set according to the detection range, the detection speed is faster, and the output digital signal can be directly applied to programmable attenuation, further reducing the processing time.
[0015] 2) The programmable attenuation module of this utility model adopts analog switch plus π attenuation. The accuracy of numerical control attenuator is generally limited by the chip attenuation step. This solution adopts a π attenuation network composed of high-precision resistors, which has higher attenuation accuracy and consistency.
[0016] 3) The delay module of this utility model can be implemented in two ways. One is to achieve a precise delay at the picosecond level by winding the PCB and reserving optional soldering resistors in the circuit. The other is to use a digital delay chip MC100EP195 or DS1023 to achieve a picosecond-level delay. This delay can be program-controlled, and the delay control accuracy is higher. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of a front-end ultra-fast standard frequency pS-level synchronous conditioning circuit according to an embodiment of the present invention;
[0018] Figure 2 This is a block diagram of the external reference detection principle in existing technology;
[0019] Figure 3 This is a schematic diagram of a pre-amplified ultra-fast standard frequency pS-level synchronous conditioning circuit according to an embodiment of the present invention. Detailed Implementation
[0020] The technical solution of this utility model will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0021] Traditional adaptive circuits are essentially post-processed, meaning the signal needs to be acquired first, then sent to the MCU for judgment, and the power is adjusted by a compensation circuit. This results in the loss of a standard frequency range at the beginning (during ADC conversion and acquisition, MCU processing, etc.), making it impossible to provide a reference. The block diagram of the existing external reference detection principle is shown below. Figure 2As shown, connector D374 is connected to ground via GND. Then, connector D374 is connected to capacitor C1190, resistor R1505 and capacitor C1685 in sequence, and then connected to one end of analog switch chip N48. The other end of analog switch chip N48 is connected to resistor R1302, capacitor C1454, resistor R1305 and capacitor C1453 in sequence, and then connected to inverter chip D55.
[0022] The technical solution used in this invention is to use a power divider to split the input standard frequency signal into two. One signal, after hardware rectification and filtering, enters a multi-channel high-speed comparator. The number of comparators and the comparison voltage can be selected according to the power adaptation range, thus directly converting the power level into a digital signal. This digital signal can be directly used for programmable attenuation circuit control. The hardware circuit time delay is relatively fixed and can be obtained through measurement. The other signal, based on the obtained hardware delay, controls a ps-level delay module to delay the signal. After being amplified by the programmable attenuation circuit and low-noise amplifier, it can be effectively identified by the FPGA. This method can complete the pre-compensation of the signal without losing the standard frequency. Due to the very fast detection rate (ns-level), the long-term stability and accuracy of the external reference and standard frequency output are consistent with the reference source. The core is an external standard frequency reference source, employing pre-amplified power compensation to ensure no signal loss and maintain reference continuity. Multiple high-speed comparators enable rapid detection of power changes (nanosecond level). The long-term stability and accuracy of the standard frequency output are consistent with the reference source. Real-time monitoring of the external reference power allows for pre-amplified power compensation at the external reference frequency, enabling the device to adapt to the external reference power. This invention, in conjunction with power detection, selects the NC channel when the input signal is in the range of -1dBm to 7dBm, and the NO channel when the input signal is in the range of 7dBm to 13dBm. This invention discloses a pre-amplified ultra-fast standard frequency pS-level synchronous conditioning circuit, the schematic diagram of which is shown below. Figure 1 As shown in the diagram, its principle is illustrated in the figure below. Figure 3 As shown, the system includes: a power divider module, a delay module, a programmable attenuation module, a rectifier circuit, a high-speed comparator module, a low-noise amplifier module, and an FPGA. The input of the power divider module is connected to an external input signal, and its output is connected to the input of the delay module. The output of the delay module is connected to the input of the programmable attenuation module, and the output of the programmable attenuation module is connected to the input of the low-noise amplifier module. The output of the power divider module is also connected to the input of the rectifier circuit, and the output of the rectifier circuit is connected to the input of the high-speed comparator module. The output of the high-speed comparator module is connected to the input of the programmable attenuation module, and the output of the programmable attenuation module is connected to the input of the low-noise amplifier module. The output of the low-noise amplifier module is connected to the FPGA.
[0023] For example, it also includes a CPU and a crystal oscillator. The CPU is connected to the FPGA, and the output of the CPU is also connected to the input of the crystal oscillator. The output of the crystal oscillator is connected to the input of the FPGA, and the crystal oscillator outputs signals to external modules.
[0024] For example, the power divider module includes a connector XS14 and a first logic chip N11. One end of the connector is connected to an external signal input signal. The other end of the connector XS14 is connected to a first capacitor C121 and a first resistor R307 in sequence, and then connected to one end of the first logic chip N11. The other end of the first logic chip N11 is connected to a delay module and a rectifier circuit, respectively. The connector XS14 is an SMA-KHD13 connector, and the first logic chip N11 is an S0093 chip.
[0025] For example, the delay module includes a delay chip U1, one end of which is connected to a first logic chip N11, and the other end of which is connected to a second resistor R406 and then to a programmable attenuation module. The delay chip U1 is a DS1023S-25+ chip.
[0026] For example, the programmable attenuation module includes a second logic chip N2 and an analog switch chip D17. The input terminal of the second logic chip N2 is connected to the delay chip U1. The first output terminal of the second logic chip N2 is connected to the normally closed pin of the analog switch chip D17 after being connected in series with the first capacitor C112, the third resistor R403 and the second capacitor C113. The second output terminal of the second logic chip N2 is connected to the normally open pin of the analog switch chip D17 after being connected in series with the fourth resistor R404, the fifth resistor R149 and the third capacitor C29. The output terminal of the analog switch chip D17 is connected to the low noise amplifier module after being connected in series with the sixth resistor R341, the seventh resistor R393 and the fourth capacitor C115. The second logic chip N2 uses an S0093 chip, and the analog switch D17 uses an SGM1157YC chip.
[0027] For example, the rectifier circuit includes a bidirectional TVS diode V37, one end of which is connected to the first logic chip N11, and the other end of which is connected to the high-speed comparator module. The bidirectional TVS diode V37 is a BP10L50SC diode.
[0028] For example, the high-speed comparator module includes a first high-speed comparator chip U4A and a second high-speed comparator chip U4B. The other end of the bidirectional TVS diode V37 is connected to an eighth resistor R575, and then connected to one end of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B, respectively. The other ends of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B are connected to a ninth resistor R337, and then connected to the analog switch chip D17. Both the first high-speed comparator chip U4A and the second high-speed comparator chip U4B use AD8072 chips.
[0029] For example, the low-noise amplifier module includes amplifier N9. One end of amplifier N9 is connected to the output of analog switch chip D17. The other end of amplifier N9 is connected in series with a tenth resistor R398, a fourth capacitor C116, an eleventh resistor R155, and a fifth capacitor C110, and then connected to one end of inverter chip D10. The other end of inverter chip D10 is connected in series with a twelfth resistor R905 and then connected to the FPGA. Amplifier N9 is a ZDH6018 / NC amplifier, and inverter chip D10 is an NC7SZU04P5X inverter chip.
[0030] This invention employs a power detection method that compares the rectified and filtered power signal with a high-speed comparator. The voltage comparison point can be set according to the detection range, resulting in faster detection speeds at the nanosecond level. The output digital signal can be directly applied to programmable attenuation, further reducing processing time. The programmable attenuation module of this invention uses analog switches and π-attenuation, unlike the digitally controlled attenuator used in the reference patent, whose accuracy is generally limited by the chip's attenuation step. This solution uses a π-attenuation network composed of high-precision resistors, resulting in higher attenuation accuracy and consistency. The delay module can be implemented in two ways: one is through PCB wiring with pre-reserved solderable resistors to achieve ps-level precise delay; the other is using digital delay chips MC100EP195 or DS1023 to achieve ps-level delay, which can be programmably controlled with higher delay control accuracy. This invention can achieve ultra-fast, high-precision ps-level external reference synchronization in the time-frequency domain and can also be applied to hot backup applications.
[0031] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.
Claims
1. A front end ultra-fast standard frequency pS class synchronization conditioning circuit, characterized in that, include: The system comprises a power divider module, a delay module, a programmable attenuation module, a rectifier circuit, a high-speed comparator module, a low-noise amplifier module, and an FPGA. The input of the power divider module is connected to an external input signal. The output of the power divider module is connected to the input of the delay module. The output of the delay module is connected to the input of the programmable attenuation module. The output of the programmable attenuation module is connected to the input of the low-noise amplifier module. The output of the power divider module is also connected to the input of the rectifier circuit. The output of the rectifier circuit is connected to the input of the high-speed comparator module. The output of the high-speed comparator module is connected to the input of the programmable attenuation module. The output of the programmable attenuation module is connected to the input of the low-noise amplifier module. The output of the low-noise amplifier module is connected to the FPGA.
2. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 1, characterized in that: It also includes a CPU and a crystal oscillator. The CPU is connected to the FPGA, and the output of the CPU is also connected to the input of the crystal oscillator. The output of the crystal oscillator is connected to the input of the FPGA, and the crystal oscillator outputs signals to external modules.
3. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 1, characterized in that: The power divider module includes a connector XS14 and a first logic chip N11. One end of the connector is connected to an external signal input signal. The other end of the connector XS14 is connected to a first capacitor C121 and a first resistor R307 in sequence, and then connected to one end of the first logic chip N11. The other end of the first logic chip N11 is connected to a delay module and a rectifier circuit respectively.
4. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 3, characterized in that: The delay module includes a delay chip U1. One end of the delay chip U1 is connected to the first logic chip N11, and the other end of the delay chip U1 is connected to the second resistor R406 and then to the programmable attenuation module.
5. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 4, characterized in that: The programmable attenuation module includes a second logic chip N2 and an analog switch chip D17. The input terminal of the second logic chip N2 is connected to the delay chip U1. The first output terminal of the second logic chip N2 is connected to the normally closed pin of the analog switch chip D17 after being connected in series with the first capacitor C112, the third resistor R403 and the second capacitor C113. The second output terminal of the second logic chip N2 is connected to the normally open pin of the analog switch chip D17 after being connected in series with the fourth resistor R404, the fifth resistor R149 and the third capacitor C29. The output terminal of the analog switch chip D17 is connected to the low noise amplifier module after being connected in series with the sixth resistor R341, the seventh resistor R393 and the fourth capacitor C115.
6. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 5, characterized in that: The rectifier circuit includes a bidirectional TVS diode V37, one end of which is connected to the first logic chip N11, and the other end of which is connected to the high-speed comparator module.
7. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 6, characterized in that: The high-speed comparator module includes a first high-speed comparator chip U4A and a second high-speed comparator chip U4B. The other end of the bidirectional TVS diode V37 is connected to the eighth resistor R575, and then connected to one end of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B, respectively. The other end of the first high-speed comparator chip U4A and the second high-speed comparator chip U4B is connected to the ninth resistor R337, and then connected to the analog switch chip D17.
8. A front-mounted ultrafast standard frequency pS-level synchronous conditioning circuit according to claim 7, characterized in that: The low-noise amplifier module comprises an amplifier N9, one end of the amplifier N9 is connected with an output end of an analog switch chip D17, the other end of the amplifier N9 is connected with one end of an inverter chip D10 in sequence after being connected with a tenth resistor R398, a fourth capacitor C116, an eleventh resistor R155 and a fifth capacitor C110 in sequence, the other end of the inverter chip D10 is connected with an FPGA after being connected with a twelfth resistor R905 in sequence.