Circuit for suppressing POP sound of TDA7265 power amplifier system
By employing adaptive timing control and on-chip integrated soft-rise circuitry, combined with common-mode-signal collaborative isolation technology, the problem of unsatisfactory pop noise suppression in the TDA7265 power amplifier system has been solved. This achieves efficient pop noise suppression under wide temperature conditions, reduces hardware complexity and cost, and improves equipment reliability and production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHUANGLING ZHONGXIANG INTELLIGENT TECHNOLOGY (ZHEJIANG) CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-04-21
AI Technical Summary
The existing TDA7265 power amplifier system has the problem of unsatisfactory pop noise suppression in scenarios such as car audio and home theater. Traditional methods lead to a conflict between hardware complexity and suppression accuracy, mismatch with dynamic operating conditions, and increase chip area and failure rate.
It adopts adaptive timing control, on-chip integrated soft-rise circuit and common-mode signal cooperative isolation technology, and dynamically adjusts the delay time by combining IO pins and transistor switches to improve dynamic response accuracy. It uses on-chip integrated soft-rise circuit to replace external DAC module, and suppresses transient noise and shutdown noise through reverse timing control and RC network fast discharge.
It achieves effective suppression of POP noise under wide temperature conditions, reduces BOM cost, reduces chip area, improves production efficiency and equipment life, enhances temperature adaptability and surge resistance, and reduces failure rate and energy consumption.
Smart Images
Figure CN224154338U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of audio engineering, and in particular to a circuit for suppressing pop noise in a TDA7265 power amplifier system. Background Technology
[0002] The TDA7265 amplifier system, a classic Class AB amplifier chip, is widely used in car audio, home theater, and smart speaker applications. Especially in the automotive audio field, it needs to meet stability and low pop noise requirements across a wide operating temperature range of -40℃ to 85℃. Existing pop noise suppression technologies are mainly divided into hardware control and feedback optimization. However, existing technologies suffer from conflicts between hardware complexity and suppression accuracy, as well as mismatches with dynamic operating conditions. Traditional reference voltage ramp-up schemes require an external DAC or RC filter network, increasing chip area by 15%-20% and requiring additional filter pins and capacitors. Traditional mute circuits cut off the output path through an external transistor switch, but this multi-stage discrete component layout is complex and has a high failure rate. Traditional delay control circuits rely on fixed resistor voltage division timing, which cannot adapt to power supply voltage fluctuations, resulting in unsatisfactory pop noise suppression effects. Summary of the Invention
[0003] The purpose of this invention is to address the shortcomings of existing technologies by proposing a circuit for suppressing pop noise in a TDA7265 power amplifier system.
[0004] To achieve the above objectives, this utility model adopts the following technical solution: a circuit for suppressing pop noise in a TDA7265 power amplifier system, comprising a system audio source, an ASP processing circuit, a power amplifier power control circuit, a power amplifier circuit, an STBY / MUTE control circuit, and a speaker. The system audio source is electrically connected to the ASP processing circuit, the ASP processing circuit is electrically connected to the power amplifier circuit, the power amplifier power control circuit is electrically connected to both the ASP processing circuit and the power amplifier circuit, the STBY / MUTE control circuit is electrically connected to the power amplifier circuit, the power amplifier circuit is electrically connected to the speaker, and the power amplifier power control circuit is responsible for managing and controlling the power supply to the power amplifier VS pin and power amplifier pin 5 of the power amplifier circuit in the audio system, and also provides power to the ASP processing circuit.
[0005] Preferably, the power amplifier power control circuit includes the following components for the power amplifier VS pin power supply circuit: a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139, and a second timer TP104. The source of the first transistor Q110 is electrically connected to VIN_POW, and the drain of the first transistor Q110 is electrically connected to AM. P_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected to the first... The electrical connection node between the fourth capacitor C171 and VIN_POW; the other end of the second capacitor C206 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW; the connection node between the first capacitor C192 and the second capacitor C206 is grounded; the gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162; the second timer TP104 is electrically connected to the electrical connection node between the other end of the second resistor R162 and the collector of the second transistor Q111; the first... The emitters of two transistors Q111 are grounded. One end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111. The third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN. The fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
[0006] Preferably, the power amplifier power control circuit, which is the power supply circuit for pin 5 of the power amplifier, includes components such as a third transistor Q117, a fourth transistor Q116, a fifth resistor R191, a sixth resistor R192, a seventh resistor R193, a fifth capacitor C248, and a sixth capacitor C249. The source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 through the sixth resistor R192, and one end of the fifth capacitor C248 is electrically connected to VIN_P. The fifth resistor R191 is electrically connected to the source of the fourth transistor Q116 at one end and to the gate of the fourth transistor Q116 at the other end. The sixth capacitor C249 is electrically connected to the base of the third transistor Q117 at one end and to the emitter of the third transistor Q117 at the other end. The seventh resistor R193 is electrically connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249 at one end and to the receiver of the MCU_AMP_5Viao_EN signal at the other end. The emitter of the third transistor Q117 is grounded.
[0007] Preferably, the power amplifier power control circuit comprises the following components for the ASP processing power supply circuit: a first voltage regulator U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131, and a ninth capacitor C132. One end of the seventh capacitor C130 is electrically connected to pin 1 of the first voltage regulator U115, and the other end is electrically connected to pin 2 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 1 of the first voltage regulator U115 is electrically connected to DVDD_12V. The third timer TP110 is electrically connected to the electrical connection between DVDD_12V and pin 1 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 2 of the first voltage regulator U115 is grounded. Pin 3 of the first voltage regulator U115 is grounded through the twelfth resistor R177. One end of the ninth resistor R173 is electrically connected to the electrical connection between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end... Electrically connected to DVDD_12V, one end of the tenth resistor R174 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. One end of the thirteenth resistor R195 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. Pin 4 of the first voltage regulator U115 is electrically connected to pin 5 of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor R... The 175 and the eighth capacitor C131 are connected in series and in parallel with the eighth resistor R172. The fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175. The electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded. The ninth capacitor C132 is connected in parallel with the eighth capacitor C131. The electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V. The fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
[0008] Preferably, the components of the STBY / MUTE control circuit include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666, and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer TP655 is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the receiving STBY signal. The base of the first NPN transistor N600 is electrically connected to one end of the fifteenth resistor R624 through the fourteenth resistor R623. The other end of the fifteenth resistor R624 is grounded. The electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to the receiving AMP_STBY signal. The sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623. The sixteenth... One end of resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is connected in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The first NPN transistor N600... The emitter of transistor 0 is electrically connected to the collector of the second NPN transistor N601 via the seventeenth resistor R626. The emitter of the second NPN transistor N601 is grounded. One end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601. The eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600. The base of the second NPN transistor N601 is electrically connected to receive the MUTE signal via the nineteenth resistor R628. The twentieth resistor... R629 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and at the other end to ground. The twenty-second resistor R637 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and at the other end to the MCU_MUTE signal receiver. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the MUTE signal receiver.
[0009] Preferably, the system audio source is the entry point of the entire audio processing system, responsible for receiving externally input audio signals and providing the initial audio data source for the audio system. The ASP processing circuit performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent audio signal processing. The processed audio signals are transmitted to the power amplifier circuit, which amplifies the audio signals and drives the speakers to emit corresponding sounds, ensuring clear and loud sound quality. The STBY / MUTE control circuit provides control and power failure recognition functions. The power amplifier power control circuit ensures that it can stably provide power to the power amplifier circuit under STBY / MUTE control and power failure recognition conditions.
[0010] Preferably, the power amplifier power supply control circuit of the power amplifier VS pin controls the base of the first transistor Q110 through the control signal AMP_POW_EN, thereby controlling the conduction and cutoff of the second transistor Q111. Under normal circumstances, when VIN_POW provides power, the circuit provides a stable power supply to the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the drive circuit operates to control the working state of the first transistor Q110 and the second transistor Q111, ensuring the protection and stable operation of the circuit.
[0011] Preferably, the power supply circuit of the power amplifier's pin 5 is controlled by the internal logic of the fourth transistor Q116 to control the conduction and cutoff of the third transistor Q117, thereby controlling the power amplifier's power supply, effectively suppressing pop noise, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192, controlling the conduction and cutoff of the fourth transistor Q116. The fourth transistor Q116 is used to conduct under the action of the control signal to complete the switching and control of the circuit.
[0012] Preferably, under normal circumstances, the ASP processing power supply circuit of the power amplifier power control circuit provides power to the circuit via DVDD_12V. After filtering by capacitors and voltage regulation by the first regulator U115, the circuit can provide a stable and clean power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will operate to ensure that the circuit can smoothly transition when the ASP processing system is turned on or off, effectively suppressing the generation of POP noise and ensuring that the circuit can smoothly transition when the ASP processing system is turned on or off.
[0013] Preferably, the STBY / MUTE control circuit controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to pin 5 of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 is turned on, so that the voltage of pin 5 of the power amplifier is maintained. When the STBY signal is low, the first NPN transistor N600 is turned off, and the voltage of pin 5 of the power amplifier is pulled down through other paths to avoid the popping sound caused by complete power failure. Under the control of the MUTE signal, the second NPN transistor N601 directly pulls the voltage of pin 5 of the power amplifier down to ground potential. When the MUTE signal is low, the second NPN transistor N601 is not turned on, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is high, the second NPN transistor N601 is turned on, pulling down the voltage of pin 5 of the power amplifier to achieve mute.
[0014] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention systematically solves the problems of conflict between hardware complexity and suppression accuracy, and mismatch between dynamic operating conditions, through adaptive timing control, on-chip integrated soft-rise circuit, and common-mode-signal cooperative isolation technology. It also considers production efficiency, energy consumption optimization, and environmental protection requirements, making it suitable for high-demand scenarios such as high-fidelity audio equipment and automotive electronics. This invention employs adaptive timing control (i.e., dynamically adjusting the delay time by combining IO pins and transistor switches) and dynamic loop feedback, improving dynamic response accuracy, suppressing transient noise, and exhibiting strong adaptability to power fluctuations. This invention uses an on-chip integrated soft-rise circuit (i.e., multiplexing the audio DAC to generate a soft-rise reference voltage) to replace the traditional external DA. The C module and discrete filter components reduce the need for external DAC chips, filter capacitors, and other components, resulting in lower BOM costs, smaller chip area, and a more compact PCB layout. This eliminates the soldering and debugging steps for external components, improving production line yield and shortening the production cycle. This invention employs common-mode-signal collaborative isolation (covering a temperature range of -40℃ to 85℃) and an internal resistor network for temperature drift compensation, enhancing temperature adaptability and reliability, improving surge resistance, and reducing failure rate. This invention utilizes reverse timing control and RC network for rapid discharge, improving shutdown transient suppression efficiency, eliminating shutdown noise, and reducing energy consumption. This invention uses lead-free packaging technology and long-life electrolytic capacitors, reducing electronic waste, extending equipment life, and meeting environmental protection requirements. Attached Figure Description
[0015] Figure 1 This is a flowchart of the audio workflow of this utility model.
[0016] Figure 2 The power amplifier power control circuit of this utility model is a schematic diagram of a power amplifier circuit that provides independent power supply to the VS pin of the power amplifier.
[0017] Figure 3 The power amplifier power control circuit of this utility model provides an independent power supply for pin 5 of the power amplifier.
[0018] Figure 4 The schematic diagram of the power amplifier circuit of this utility model is a power amplifier circuit that provides independent power to the ASP processing circuit.
[0019] Figure 5 This is the STBY and MUTE control circuit diagram of this utility model.
[0020] Figure 6 This invention relates to a scenario where the vehicle's infotainment system produces a pop sound.
[0021] Figure 7 This is the timing sequence for the power-on mode audio system of this utility model.
[0022] Figure 8 This is the timing sequence for the ACC off sleep scene audio system of this utility model.
[0023] Figure 9 The timing of the audio system for the factory reset scene of this utility model. Detailed Implementation
[0024] To provide a better understanding of the purpose, structure, features, and functions of this utility model, detailed descriptions are provided below with reference to specific embodiments.
[0025] Please refer to the reference. Figure 1 This utility model provides a circuit for suppressing pop noise in a TDA7265 power amplifier system, including a system audio source 101, an ASP processing circuit 102, a power amplifier power control circuit 103, a power amplifier circuit 104, an STBY / MUTE control circuit 105, and a speaker 106. The system audio source 101 is electrically connected to the ASP processing circuit 102, the ASP processing circuit 102 is electrically connected to the power amplifier circuit 104, the power amplifier power control circuit 103 is electrically connected to both the ASP processing circuit 102 and the power amplifier circuit 104, the STBY / MUTE control circuit 105 is electrically connected to the power amplifier circuit 104, and the power amplifier circuit 104 is electrically connected to the speaker 106. The power amplifier power control circuit 103 is responsible for managing and controlling the power supply to the power amplifier VS pin and power amplifier pin 5 of the power amplifier circuit in the audio system, and also provides power to the ASP processing circuit.
[0026] The system audio source 101, ASP processing circuit 102, power amplifier circuit 104 and speaker 106 adopt existing technology, and this utility model does not make any improvements to them.
[0027] In one embodiment, such as Figure 1As shown, the system audio source 101 is the entry point of the entire audio processing system, responsible for receiving externally input audio signals and providing the initial audio data source for the audio system. The ASP processing circuit 102 performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent audio signal processing. The processed audio signals are transmitted to the power amplifier circuit 104, which amplifies the audio signals and drives the speaker 106 to emit corresponding sounds, ensuring clear and loud sound quality. The STBY / MUTE control circuit 105 provides control and power failure recognition functions. The power amplifier power control circuit 103 ensures that the power amplifier circuit can stably provide power under STBY / MUTE control and power failure recognition conditions.
[0028] In one embodiment, such as Figure 2As shown, the power amplifier power control circuit 103 includes the following components for the power supply circuit to the VS pin of the power amplifier: a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139, and a second timer TP104. The source of the first transistor Q110 is electrically connected to VIN_POW, and the drain of the first transistor Q110 is electrically connected to A. MP_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected to The electrical connection node between the fourth capacitor C171 and VIN_POW; the other end of the second capacitor C206 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW; the connection node between the first capacitor C192 and the second capacitor C206 is grounded; the gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162; the second timer TP104 is electrically connected to the electrical connection node between the other end of the second resistor R162 and the collector of the second transistor Q111; the first... The emitters of two transistors Q111 are grounded. One end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111. The third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN. The fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
[0029] In one embodiment, such as Figure 2As shown, the power amplifier power control circuit 103 uses the control signal AMP_POW_EN to control the base of the first transistor Q110, thereby controlling the conduction and cutoff of the second transistor Q111. Under normal circumstances, when VIN_POW provides power, the circuit provides a stable power supply to the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the drive circuit operates to control the working state of the first transistor Q110 and the second transistor Q111, ensuring the protection and stable operation of the circuit.
[0030] The first capacitor C192 and the second capacitor C206 are used for power supply decoupling and filtering to ensure power supply stability. The first transistor Q110 and the second transistor Q111 serve as switches and protectors. The second transistor Q111 is used to protect subsequent circuits from damage caused by transient voltages. The third resistor R105 and the fourth resistor R194 are used for current limiting and voltage distribution, respectively, to ensure that the circuit operates at a safe operating point. The third capacitor C184 and the fourth capacitor C171 are both used to further filter the power supply signal.
[0031] Furthermore, the first transistor Q110 is model UTT50P06G-TN3-R, the second transistor Q111 is model DTC124EKA, the first capacitor C192 and the second capacitor C206 are both 1000UF / 50V, the fourth capacitor C171 is 1UF, the third capacitor C184 is 0.1UF, the first resistor R161 is 1MΩ, the second resistor R162 is 2MΩ, the third resistor R105 is NC / 1KΩ, and the fourth resistor R194 is 1KΩ.
[0032] In one embodiment, such as Figure 3As shown, the power amplifier power control circuit 103 includes components for the power supply circuit to pin 5 of the power amplifier, including a third transistor Q117, a fourth transistor Q116, a fifth resistor R191, a sixth resistor R192, a seventh resistor R193, a fifth capacitor C248, and a sixth capacitor C249. The source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, and the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 through the sixth resistor R192. One end of the fifth capacitor C248 is electrically connected to VIN_ The POW resistor is connected to the gate of the fourth transistor Q116 at one end. The fifth resistor R191 is connected to the source of the fourth transistor Q116 at one end and to the gate of the fourth transistor Q116 at the other end. The sixth capacitor C249 is connected to the base of the third transistor Q117 at one end and to the emitter of the third transistor Q117 at the other end. The seventh resistor R193 is connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249 at one end and to the receiver of the MCU_AMP_5Viao_EN signal at the other end. The emitter of the third transistor Q117 is grounded.
[0033] In one embodiment, such as Figure 3 As shown, the power supply circuit of the power amplifier power control circuit 103 controls the power supply of the third transistor Q117 through the internal logic of the fourth transistor Q116, thereby controlling the power supply of the power amplifier, effectively suppressing the pop noise, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192, controlling the switching of the fourth transistor Q116. The fourth transistor Q116 is used to conduct under the action of the control signal to complete the switching and control of the circuit.
[0034] The seventh resistor R193 is used for current limiting to protect the base of the third transistor Q117 from damage by excessive current. The fifth capacitor C248 and the sixth capacitor C249 are used for filtering to remove high-frequency noise in the power supply and ensure the circuit's voltage regulation.
[0035] Furthermore, the third transistor Q117 is model DTC124EKA, the fourth transistor Q1167 is model NCE2309, the fifth resistor R191 is 1MΩ, the sixth resistor R192 is 2MΩ, the seventh resistor R193 is 1KΩ, and the fifth capacitor C248 and the sixth capacitor C249 are both NC / 0.1UF.
[0036] In one embodiment, such as Figure 4As shown, the power amplifier power control circuit 103, which supplies power to the ASP processing circuit, includes components such as a first voltage regulator U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131, and a ninth capacitor C132. One end of the seventh capacitor C130 is electrically connected to pin 1 of the first voltage regulator U115, and the other end is electrically connected to pin 2 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 1 of the first voltage regulator U115 is electrically connected to DVDD_12V. The third timer TP110 is electrically connected to the electrical connection between DVDD_12V and pin 1 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 2 of the first voltage regulator U115 is grounded. Pin 3 of the first voltage regulator U115 is grounded through the twelfth resistor R177. One end of the ninth resistor R173 is electrically connected to the electrical connection between pin 3 of the first voltage regulator U115 and the twelfth resistor R177. The tenth resistor R174 is electrically connected to DVDD_12V. One end of the tenth resistor R174 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. One end of the thirteenth resistor R195 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. Pin 4 of the first voltage regulator U115 is electrically connected to pin 5 of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor... Resistor R175 and the eighth capacitor C131 are connected in series and in parallel with the eighth resistor R172. The fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175. The electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded. The ninth capacitor C132 is connected in parallel with the eighth capacitor C131. The electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V. The fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
[0037] In one embodiment, such as Figure 4As shown, under normal circumstances, the ASP processing power supply circuit of the power amplifier power control circuit 103 uses DVDD_12V to provide power to the circuit. After filtering by capacitors and voltage regulation by the first regulator U115, the circuit can provide a stable and clean power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will operate to ensure that the circuit can smoothly transition when the ASP processing system is turned on or off, effectively suppressing the generation of POP noise and ensuring that the circuit can smoothly transition when the ASP processing system is turned on or off.
[0038] The first voltage regulator U115 regulates the input DVDD_12V voltage to an 8V output, providing a stable power supply voltage for subsequent circuit modules. The twelfth resistor R177 plays the role of current limiting and voltage distribution in the circuit. The eighth resistor R172 and the eleventh resistor R175 serve as feedback and bias resistors. The seventh capacitor C130, the eighth capacitor C131, and the ninth capacitor C132 are used for filtering.
[0039] Furthermore, the first voltage regulator U115 is model ETA5095S2F, the eighth resistor R172 is 100KJ (100KJ resistor is a 100KΩ ±5% precision resistor), the ninth resistor R173 is NC / 10KΩ, the tenth resistor R174 is NC / 10KΩ, the eleventh resistor R175 is 16KJ, the twelfth resistor R177 is 100KΩ, the thirteenth resistor R195 is 1KΩ, the seventh capacitor C130 is 10UF / 25V, the eighth capacitor C131 is 0.1UF, and the ninth capacitor C132 is 10UF / 25V.
[0040] In one embodiment, such as Figure 5As shown, the components of the STBY / MUTE control circuit 105 include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666, and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer TP655 is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the receiving STBY signal. The base of the first NPN transistor N600 is electrically connected to one end of the fifteenth resistor R624 through the fourteenth resistor R623. The other end of the fifteenth resistor R624 is grounded. The electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to the receiving AMP_STBY signal. The sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623. The sixteenth... One end of resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is connected in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The first NPN transistor N600... The emitter of transistor 0 is electrically connected to the collector of the second NPN transistor N601 via the seventeenth resistor R626. The emitter of the second NPN transistor N601 is grounded. One end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601. The eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600. The base of the second NPN transistor N601 is electrically connected to receive the MUTE signal via the nineteenth resistor R628. The twentieth resistor... R629 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and at the other end to ground. The twenty-second resistor R637 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and at the other end to the MCU_MUTE signal receiver. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the MUTE signal receiver.
[0041] In one embodiment, such as Figure 5As shown, the STBY / MUTE control circuit 105 controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to pin 5 of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 is turned on, so that the voltage of pin 5 of the power amplifier is maintained. When the STBY signal is low, the first NPN transistor N600 is turned off, and the voltage of pin 5 of the power amplifier is pulled down through other paths to avoid the popping sound caused by complete power failure. Under the control of the MUTE signal, the second NPN transistor N601 directly pulls the voltage of pin 5 of the power amplifier down to ground potential. When the MUTE signal is low, the second NPN transistor N601 is not turned on, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is high, the second NPN transistor N601 is turned on, pulling down the voltage of pin 5 of the power amplifier to achieve mute.
[0042] The tenth capacitor C681 is used for filtering to remove high-frequency noise in the power supply and ensure the stability of the voltage at pin 5 of the power amplifier. The nineteenth resistor R628 is connected to the MUTE signal and affects the voltage at pin 5 of the power amplifier by controlling the base voltage of the second NPN transistor N601.
[0043] Furthermore, the first NPN transistor N600 and the second NPN transistor N601 are both model BC817-25,215, the tenth capacitor C681 is 22uF / 10V, the fourteenth resistor R623 is NC / 10KΩ, the fifteenth resistor R624 is 4.7KΩ, the sixteenth resistor R625 is 47KΩ, the seventeenth resistor R626 is 13KJ, the eighteenth resistor R627 is 23.4KJ, the nineteenth resistor R628 is NC / 10KΩ, the twentieth resistor R629 is 47KΩ, the twenty-first resistor R660 is 10KΩ, and the twenty-second resistor R637 is 10KΩ.
[0044] In one embodiment, such as Figure 6 As shown, the following are some scenarios used to describe the appearance of the pop sound on the in-vehicle infotainment system:
[0045] Power-on mode 201: As the initial state of the entire system, when the vehicle system is powered on, the car audio system starts to start. If the capacitor in the power amplifier circuit is not fully charged at this time, a pop sound may occur.
[0046] ACC off hibernation 202: When the ACC status of the vehicle's infotainment system is turned off, the system enters hibernation mode. At this time, the power amplifier power control circuit should control the power amplifier circuit to enter a low-power state. If the power control is improper or the circuit is not completely powered off, it will cause the capacitor to discharge incompletely, resulting in a popping sound when restarting.
[0047] Factory Reset 203: In some cases, the car audio system may need to be reset to factory settings. During the system reset process, if the power control or circuit initialization is not done properly, it may cause instability in the capacitor discharge and charging process, resulting in a popping sound.
[0048] In one embodiment, such as Figure 7 As shown, the MCU controls and processes the audio system to meet the timing requirements of the power-on mode, thereby suppressing the pop noise in the TDA7265 amplifier system. The specific operation is as follows:
[0049] 1) The following status pins are disabled by default when the MCU is powered on for the first time (this is written in the Boot code to avoid them being pulled high when there is no control and then pulled low after the program runs, causing a popping sound).
[0050] PC1=0;
[0051] PC2=0;
[0052] PC8=0;
[0053] PB15=0;
[0054] PC6=0;
[0055] 2) After ACC is detected as on
[0056] 3) Turn on the audio output power.
[0057] PC6=1
[0058] 4) Wait 500ms
[0059] 5) Set the amplifier to playback mode.
[0060] PC8=1; (STBY)
[0061] PB15=1; (MUTE)
[0062] PC2=1; (Pin 5 pull-up power supply)
[0063] 6) Wait 18 seconds
[0064] 7) Turn on the power amplifier.
[0065] PC1=1
[0066] In one embodiment, such as Figure 8 As shown, the audio system timing requirements for the ACC off sleep scenario are met through the following MCU control processing, thereby suppressing the pop noise of the TDA7265 power amplifier system. The specific operation is as follows:
[0067] 1) ACC off detected
[0068] 2) Switch to silent mode
[0069] PC8=1; (STBY)
[0070] PB15=0; (MUTE)
[0071] PC2=1; (Pin 5 pull-up power supply)
[0072] 3) Set a hibernation timer
[0073] 4) Before the end of hibernation:
[0074] ① Switch the amplifier to power off state
[0075] Turn off the amplifier:
[0076] PC8=0; (STBY)
[0077] PB15=0; (MUTE)
[0078] PC2=1; (Pin 5 pull-up power supply)
[0079] Delay 200ms
[0080] ② Turn off the sound effects power
[0081] Turn off sound effects power: PC6=0;
[0082] ③Wait 100ms
[0083] ④ Turn off the power amplifier.
[0084] Power amplifier off: PC1=0;
[0085] 5) Enter hibernation after 10 seconds.
[0086] In one embodiment, such as Figure 9 As shown, after the audio system timing requirements for the factory reset scenario are met through the MCU's control processing, the pop noise of the TDA7265 power amplifier system is suppressed. The specific operation is as follows:
[0087] MCU:
[0088] 1) Received factory reset command from MPU
[0089] 2) Switch to mute mode and maintain it for 200ms.
[0090] PC8=0; (STBY)
[0091] PB15=0; (MUTE)
[0092] PC2=1; (Pin 5 pull-up power supply)
[0093] 3) Until the next time the MPU sends a playback command to the MCU
[0094] PC8=1; (STBY)
[0095] PB15=1; (MUTE)
[0096] PC2=1; (Pin 5 pull-up power supply).
[0097] Usage: Combine Figures 1-9 As shown, this utility model receives externally input audio signals from the system audio source 101, providing the initial audio data source for the audio system. The ASP processing circuit 102 performs analog signal processing on the received audio signals. The processed audio signals are then transmitted to the power amplifier circuit 104, which amplifies the audio signals and drives the speaker 106 to emit corresponding sounds, ensuring clear and loud sound quality. The STBY / MUTE control circuit 105 provides control and power-off recognition functions. The power amplifier power control circuit 103 ensures that the power amplifier circuit can stably provide power under STBY / MUTE control and power-off recognition conditions.
[0098] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A circuit for suppressing pop noise in a TDA7265 power amplifier system, characterized in that: The system includes a system audio source (101), an ASP processing circuit (102), a power amplifier power control circuit (103), a power amplifier circuit (104), an STBY / MUTE control circuit (105), and a speaker (106). The system audio source (101) is electrically connected to the ASP processing circuit (102), the ASP processing circuit (102) is electrically connected to the power amplifier circuit (104), the power amplifier power control circuit (103) is electrically connected to the ASP processing circuit (102) and the power amplifier circuit (104) respectively, the STBY / MUTE control circuit (105) is electrically connected to the power amplifier circuit (104), and the power amplifier circuit (104) is electrically connected to the speaker (106). The power amplifier power control circuit (103) is responsible for managing and controlling the power supply to the power amplifier VS pin and power amplifier 5 pin of the power amplifier circuit in the audio system, and also provides power to the ASP processing circuit.
2. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 1, characterized in that: The power amplifier power control circuit (103) includes the following components for the power supply circuit to the VS pin of the power amplifier: a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139, and a second timer TP104. The source of the first transistor Q110 is electrically connected to VIN_POW, and the drain of the first transistor Q110 is electrically connected to A. MP_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected to The electrical connection node between the fourth capacitor C171 and VIN_POW; the other end of the second capacitor C206 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW; the connection node between the first capacitor C192 and the second capacitor C206 is grounded; the gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162; the second timer TP104 is electrically connected to the electrical connection node between the other end of the second resistor R162 and the collector of the second transistor Q111; the first... The emitters of two transistors Q111 are grounded. One end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111. The third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN. The fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
3. The circuit for suppressing pop noise in a TDA7265 power amplifier system as described in claim 1, characterized in that: The power amplifier power control circuit (103) includes the following components for the power supply circuit of pin 5: a third transistor Q117, a fourth transistor Q116, a fifth resistor R191, a sixth resistor R192, a seventh resistor R193, a fifth capacitor C248, and a sixth capacitor C249. The source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 through the sixth resistor R192, and one end of the fifth capacitor C248 is electrically connected to VIN_P. The fifth resistor R191 is electrically connected to the source of the fourth transistor Q116 at one end and to the gate of the fourth transistor Q116 at the other end. The sixth capacitor C249 is electrically connected to the base of the third transistor Q117 at one end and to the emitter of the third transistor Q117 at the other end. The seventh resistor R193 is electrically connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249 at one end and to the receiver of the MCU_AMP_5Viao_EN signal at the other end. The emitter of the third transistor Q117 is grounded.
4. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 1, characterized in that: The power amplifier power control circuit (103) includes the following components for the ASP processing power supply circuit: a first voltage regulator U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131, and a ninth capacitor C132. One end of the seventh capacitor C130 is electrically connected to pin 1 of the first voltage regulator U115, and the other end is electrically connected to pin 2 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 1 of the first voltage regulator U115 is electrically connected to DVDD_12V. The third timer TP110 is electrically connected to the electrical connection between DVDD_12V and pin 1 of the first voltage regulator U115. The electrical connection between the seventh capacitor C130 and pin 2 of the first voltage regulator U115 is grounded. Pin 3 of the first voltage regulator U115 is grounded through the twelfth resistor R177. One end of the ninth resistor R173 is electrically connected to the electrical connection between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end... Electrically connected to DVDD_12V, one end of the tenth resistor R174 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. One end of the thirteenth resistor R195 is electrically connected to the electrical connection node between pin 3 of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. Pin 4 of the first voltage regulator U115 is electrically connected to pin 5 of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor R... The 175 and the eighth capacitor C131 are connected in series and in parallel with the eighth resistor R172. The fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175. The electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded. The ninth capacitor C132 is connected in parallel with the eighth capacitor C131. The electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V. The fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
5. The circuit for suppressing pop noise in a TDA7265 power amplifier system as described in claim 1, characterized in that: The components of the STBY / MUTE control circuit (105) include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666, and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer TP655 is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the receiving STBY signal. The base of the first NPN transistor N600 is electrically connected to one end of the fifteenth resistor R624 through the fourteenth resistor R623. The other end of the fifteenth resistor R624 is grounded. The electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to the receiving AMP_STBY signal. The sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623. The sixteenth... One end of resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is connected in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The first NPN transistor N600... The emitter of transistor 0 is electrically connected to the collector of the second NPN transistor N601 via the seventeenth resistor R626. The emitter of the second NPN transistor N601 is grounded. One end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601. The eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600. The base of the second NPN transistor N601 is electrically connected to receive the MUTE signal via the nineteenth resistor R628. The twentieth resistor... R629 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and at the other end to ground. The twenty-second resistor R637 is electrically connected at one end to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and at the other end to the MCU_MUTE signal receiver. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the MUTE signal receiver.
6. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 1, wherein: The system audio source (101) is the entry point of the entire audio processing system, responsible for receiving externally input audio signals and providing the initial audio data source for the audio system. The ASP processing circuit (102) performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent audio signal processing. The processed audio signals are transmitted to the power amplifier circuit (104). The power amplifier circuit (104) amplifies the audio signals and drives the speaker (106) to emit corresponding sounds, ensuring clear and loud sound quality. The STBY / MUTE control circuit (105) plays a control and power-down identification role. The power amplifier power control circuit (103) ensures that it can stably provide power to the power amplifier circuit under STBY / MUTE control and power-down identification.
7. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 2, characterized in that: The power amplifier power control circuit (103) uses the power amplifier VS pin power supply circuit to control the base of the first transistor Q110 through the control signal AMP_POW_EN, thereby controlling the conduction and cutoff of the second transistor Q111. Under normal circumstances, when VIN_POW provides power, the circuit provides a stable power supply to the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the drive circuit operates to control the working state of the first transistor Q110 and the second transistor Q111, ensuring the protection and stable operation of the circuit.
8. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 3, characterized in that: The power amplifier power supply control circuit (103) controls the power supply of the third transistor Q117 through the internal logic of the fourth transistor Q116, thereby controlling the power supply of the power amplifier, effectively suppressing the pop noise, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192, controlling the switching of the fourth transistor Q116. The fourth transistor Q116 is used to conduct under the action of the control signal to complete the switching and control of the circuit.
9. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 4, characterized in that: Under normal circumstances, the ASP processing power supply circuit of the power amplifier power control circuit (103) provides power to the circuit via DVDD_12V. After filtering by capacitors and voltage regulation by the first regulator U115, the circuit can provide a stable and clean power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will operate to ensure that the circuit can smoothly transition when the ASP processing system is turned on or off, effectively suppressing the generation of POP noise and ensuring that the circuit can smoothly transition when the ASP processing system is turned on or off.
10. The circuit for suppressing the POP sound of the TDA7265 power amplifier system according to claim 5, characterized in that: The STBY\MUTE control circuit (105) controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to pin 5 of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 is turned on, so that the voltage of pin 5 of the power amplifier can be maintained. When the STBY signal is low, the first NPN transistor N600 is turned off, and the voltage of pin 5 of the power amplifier is pulled down through other paths to avoid the pop sound caused by complete power failure. Under the control of the MUTE signal, the second NPN transistor N601 directly pulls the voltage of pin 5 of the power amplifier down to ground potential. When the MUTE signal is low, the second NPN transistor N601 is not turned on, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is high, the second NPN transistor N601 is turned on, pulling the voltage of pin 5 of the power amplifier down to achieve mute.