485 bus data recording device circuit

Abstract

The utility model discloses a 485 bus data recording device circuit, which comprises a processor chip U1, a crystal oscillator Y1, a crystal oscillator Y2, a capacitor C10, a capacitor C11, a capacitor C9, a capacitor C22, a power supply circuit and a bus isolation module, and is characterized in that the eighth pin of the processor chip U1 is connected with one end of the crystal oscillator Y1, and the other end of the crystal oscillator Y1 is connected with the ninth pin of the processor chip U1; and one end of the crystal oscillator Y2 is connected with the twelfth pin of the processor chip U1. The utility model belongs to the technical field of 485 bus data recording, and aims to solve the problem that the analysis and diagnosis functions of communication of remote 485 equipment are limited due to the fact that communication data cannot be automatically recorded after power-on in the prior art. The method has the technical effects that the problem that data of the 485 communication network cannot be recorded is effectively solved, tracking and analysis of the communication process after the event are facilitated, and powerful support is provided for the occurring 485 communication problem.

Description

Technical Field

[0001] This application relates to the field of 485 bus data recording technology, and specifically to a 485 bus data recording device circuit. Background Technology

[0002] Currently, devices using RS-485 networks as a communication method are widely used in various fields. As a commonly adopted communication method, RS-485 networks are known for their ease of connection and excellent anti-interference capabilities, and are widely used in various instruments, motors, and sensors. With the increasing prevalence of these devices, the demand for debugging and data recording of RS-485 communication systems is also growing.

[0003] The advantages of RS-485 communication lie in its stable data transmission performance and high reliability, making it an indispensable part of industrial automation and control systems. Whether in harsh industrial environments or complex electrical systems, RS-485 networks ensure accurate data transmission and reduce communication errors caused by interference. Therefore, mastering RS-485 network debugging techniques and effective data logging methods is crucial. This not only helps improve the overall operating efficiency of the system but also ensures that problems can be quickly located and resolved, thereby guaranteeing the continuity and stability of production and operations.

[0004] However, most 485 bus data recording devices currently have simple wiring and cannot automatically record communication data after power-on, which limits the analysis and diagnosis functions of 485 communication between remote devices. Utility Model Content

[0005] To address this issue, this application provides a 485 bus data recording device circuit to solve the problem that existing circuits have simple wiring but cannot automatically record communication data after power-on, thus limiting the analysis and diagnostic functions of remote 485 device communication.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A 485 bus data recording device circuit includes a processor chip U1, a crystal oscillator Y1, a crystal oscillator Y2, capacitors C10, C11, C9, and C22, a power supply circuit, and a bus isolation module. The 8th pin of the processor chip U1 is connected to one end of the crystal oscillator Y1, and the other end of the crystal oscillator Y1 is connected to the 9th pin of the processor chip U1.

[0008] One end of the crystal oscillator Y2 is connected to pin 12 of the processor chip U1, and the other end of the crystal oscillator Y2 is connected to pin 13 of the processor chip U1.

[0009] The power supply circuit includes a gas discharge tube TV1, a fuse F3, a varistor R27, a diode D8, a diode D7, capacitors C24, C26, C23, C25, C1, C2, C3, C4, an inductor L1, a chip P2, and a processor chip U3.

[0010] The bus isolation module includes processor chip U4, processor chip U2, TVS diode NUP2105, gas discharge tube 3R090A, resistor R, capacitor C8 and connector JP8.

[0011] Pin 68 of processor chip U1 is connected to pin 1 of processor chip U4, pin 69 of processor chip U1 is connected to pin 2 of processor chip U4, and pins 6 and 7 of processor chip U4 are connected to pins 1 and 2 of connector JP8, respectively.

[0012] The first pin of the TVS diode NUP2105 is connected to the sixth pin of the processor chip U4, and the second pin of the TVS diode NUP2105 is connected to the seventh pin of the processor chip U4.

[0013] Furthermore, the first pin of capacitor C10 is connected to the first pin of crystal oscillator Y1, and the second pin of capacitor C10 is connected to GND.

[0014] Furthermore, the first pins of capacitors C9 and C22 are connected to the first and third pins of crystal oscillator Y2, respectively, and the second pins of capacitors C9 and C22 are both connected to GND.

[0015] Furthermore, pin 72 of the processor chip U1 is connected to pin 2 of connector JP4, pin 1 of connector JP4 is connected to VCC3.3 power supply, pin 3 of connector JP4 is connected to pin 76 of the processor chip U1, and pin 4 of connector JP4 is connected to GND.

[0016] Furthermore, the first pin of the fuse F3 is connected to 24V+, and the second pin of the fuse F3 is connected to the first pins of the varistor R27, diode D1, and diode D8, respectively. The second pins of the varistor R27 and diode D1 are both connected to the GND network, and the second pin of diode D8 is connected to the first pins of capacitor C24 and capacitor C26, respectively, and finally connected to the first pin of chip P2.

[0017] Furthermore, the second pin of the chip P2 is connected to the first pin of the inductor L1 and the first pin of the diode D7. The second pin of the inductor L1 is connected to the first pins of the capacitors C23 and C25 respectively, outputting a 5V power supply. The second pins of the diode D7, capacitor C23, and capacitor C25 are all connected to GND.

[0018] Furthermore, the first pin of the processor chip U3 is connected to the first pins of capacitors C1 and C2, the fifth pin of the processor chip U3 is connected to the first pins of capacitors C3 and C4 and outputs VCC power, and the second pins of capacitors C1, C2, C3 and C4 and the second pin of the processor chip U3 are respectively connected to the GND network.

[0019] Furthermore, the third pin of the TVS diode NUP2105 is simultaneously connected to the first pin of resistor R21 and capacitor C8, the second pin of resistor R21 and capacitor C8 is connected to the third pin of gas discharge tube 3R090A, the fifth pin of processor chip U4 is connected to the third pin of UP2105, and the third pin of gas discharge tube 3R090A is connected to the third pin of connector JP8.

[0020] Compared with the prior art, this application has at least the following beneficial effects:

[0021] 1. The bus isolation module includes processor chip U4, processor chip U2, TVS diode NUP2105, gas discharge tube 3R090A, resistor R, capacitor C8, and connector JP8. This circuit can be connected to a 485 bus. After configuring the bus communication rate, the circuit automatically records communication data upon power-up, and the recorder with RTC circuitry records the retention time. Furthermore, the circuit uses an SD card for convenient post-event analysis and retrieval, improving the communication analysis and diagnostic capabilities of remote 485 devices. It solves the problem of unrecorded data in 485 communication networks, facilitating post-event communication process tracking and analysis, and providing strong support for addressing 485 communication problems. Attached Figure Description

[0022] To more intuitively illustrate the prior art and this application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing this application; for example, based on the technical concept disclosed in this application and the exemplary drawings, those skilled in the art are able to easily make conventional adjustments or further optimizations to the addition / reduction / classification, specific shapes, positional relationships, connection methods, size ratios, etc. of certain units (components).

[0023] Figure 1A circuit schematic diagram of a 485 bus data recording device circuit provided for one embodiment of this application;

[0024] Figure 2 A power supply circuit schematic diagram of a 485 bus data recording device circuit provided in one embodiment of this application;

[0025] Figure 3 This is a schematic diagram of a bus isolation module circuit for a 485 bus data recording device circuit provided in one embodiment of this application. Detailed Implementation

[0026] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] like Figures 1 to 3 As shown in the figure, a 485 bus data recording device circuit in this embodiment includes: a processor chip U1, crystal oscillators Y1 and Y2, capacitors C10, C11, C9, and C22, a power supply circuit, and a bus isolation module. The processor chip U1 is a high-performance microcontroller from STMicroelectronics, responsible for data acquisition for this part of the circuit, and connects to a PC via USB communication. Crystal oscillators Y1 and Y2 are both low-speed crystal oscillators providing a low-speed clock, and high-speed crystal oscillators provide a high-speed clock. Capacitors C10, C11, C9, and C22 are all resonant circuits. A battery CR1 is also included in this circuit.

[0028] The circuit also includes connector JP6, resistors R13, R15, and R16, diodes D3, D4, D5, and D6, resistors R26, R23, R24, and R25, and capacitors C12-C21. Connector JP6 (resistor R25) is connected to pins 70 and 71 of the processor chip U1 via circuits R13 and R15, and resistor R16 pulls up the DEVDP network. Diodes D3, D4, and D5, along with resistors R26, R23, and R24, form an indicator light circuit. Capacitors C12-C21 are filter capacitors for filtering the chip. Pin 1 of resistor R25 is connected to pin 82 of the processor chip U1, pin 2 of resistor R25 is connected to pin 2 of diode D6, pin 1 of diode D6 is connected to the VCC-3.3 power network, and the USB interface is connected to pins 70 and 71 of the processor chip via resistors R13 and R15.

[0029] Pin 8 of processor chip U1 is connected to one end of crystal oscillator Y1, and the other end of crystal oscillator Y1 is connected to pin 9 of processor chip U1. One end of crystal oscillator Y2 is connected to pin 12 of processor chip U1, and the other end of crystal oscillator Y2 is connected to pin 13 of processor chip U1.

[0030] The first pins of capacitors C9 and C22 are connected to the first and third pins of crystal oscillator Y2, respectively, and the second pins of both capacitors C9 and C22 are connected to GND.

[0031] The first pin of capacitor C10 is connected to the first pin of crystal oscillator Y1, and the second pin of capacitor C10 is connected to GND.

[0032] Pin 72 of processor chip U1 is connected to pin 2 of connector JP4, pin 1 of connector JP4 is connected to VCC3.3 power supply, pin 3 of connector JP4 is connected to pin 76 of processor chip U1, and pin 4 of connector JP4 is connected to GND, which is the program download and debugging circuit.

[0033] The power supply circuit includes a gas discharge tube TV1, a fuse F3, a varistor R27, a diode D8, a diode D7, capacitors C24, C26, C23, C25, C1, C2, C3, C4, an inductor L1, a chip P2, and a processor chip U3.

[0034] The gas discharge tube TV1 is connected to the input power supply terminals 24V+ and 24V-. The first pin of the fuse F3 is connected to 24V+. The second pin of the fuse F3 is connected to the first pins of the varistor R27, diode D1, and diode D8, respectively. The second pins of the varistor R27 and diode D1 are both connected to the GND network. The second pin of diode D8 is connected to the first pins of capacitors C24 and C26, respectively, and finally connected to the first pin of chip P2.

[0035] Pin 2 of chip P2 is connected to pin 1 of inductor L1 and pin 1 of diode D7. Pin 2 of inductor L1 is connected to pin 1 of capacitors C23 and C25, outputting a 5V power supply. Pin 2 of diode D7, and pins 2 of capacitors C23 and C25 are all connected to GND. Pin 1 of processor chip U3 is connected to pins 1 of capacitors C1 and C2, and pin 3 of processor chip U3. Pin 5 of processor chip U3 is connected to pins 1 of capacitors C3 and C4, outputting a VCC power supply. Pins 2 of capacitors C1, C2, C3, and C4, and pin 2 of processor chip U3 are connected to the GND network.

[0036] The bus isolation module includes processor chip U4, processor chip U2, TVS diode NUP2105, gas discharge tube 3R090A, resistor R, capacitor C8 and connector JP8;

[0037] Pin 68 of processor chip U1 is connected to pin 1 of processor chip U4, pin 69 of processor chip U1 is connected to pin 2 of processor chip U4, and pins 6 and 7 of processor chip U4 are connected to pins 1 and 2 of connector JP8 respectively, so that the output of the CAN circuit is connected to an external CAN network.

[0038] Pin 1 of TVS diode NUP2105 is connected to pin 6 of processor chip U4, and pin 2 of TVS diode NUP2105 is connected to pin 7 of processor chip U4.

[0039] Pin 1 of processor chip U3 is connected to pin 1 of capacitors C1 and C2. Pin 5 of processor chip U3 is connected to pin 1 of capacitors C3 and C4 and outputs VCC power. Pins 2 of capacitors C1, C2, C3, and C4, as well as pin 2 of processor chip U3, are connected to the GND network.

[0040] Pin 3 of the TVS diode NUP2105 is connected to pin 1 of both resistor R21 and capacitor C8. Pin 2 of resistor R21 and capacitor C8 is connected to pin 3 of the gas discharge tube 3R090A. Pin 5 of processor chip U4 is connected to pin 3 of UP2105. Pin 3 of the gas discharge tube 3R090A is connected to pin 3 of connector JP8. TF1 is an SD card interface; pins 7, 8, 1, 2, 5, 3, and 9 are connected to pins 65, 66, 78, 79, and 80 of processor chip U1, respectively, for the main controller to read and write to the SD card. Processor chip U2 is an onboard memory interface; pins 1, 2, 5, and 6 of processor chip U2 are connected to pins 29, 30, 31, and 32 of processor chip U1, for temporary storage when an SDK card is missing.

[0041] The aforementioned circuit can be connected to a 485 bus. After configuring the bus communication rate, the circuit automatically records communication data upon power-up, and the recorder, equipped with an RTC circuit, records the holding time. Furthermore, the circuit uses an SD card for convenient post-event analysis and retrieval, improving the communication analysis and diagnostic capabilities of remote 485 devices. It solves the problem of unrecorded data in 485 communication networks, facilitating post-event communication process tracking and analysis, and providing strong support for addressing 485 communication problems.

[0042] The technical features of the above embodiments can be combined in any way (as long as there is no contradiction in the combination of these technical features). For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered to be within the scope of this specification.

Claims

1. A 485 bus data recording device circuit, comprising a processor chip U1, crystal oscillator Y1, crystal oscillator Y2, capacitors C10, C11, C9, and C22, a power supply circuit, and a bus isolation module, characterized in that, The 8th pin of the processor chip U1 is connected to one end of the crystal oscillator Y1, and the other end of the crystal oscillator Y1 is connected to the 9th pin of the processor chip U1. One end of the crystal oscillator Y2 is connected to pin 12 of the processor chip U1, and the other end of the crystal oscillator Y2 is connected to pin 13 of the processor chip U1. The power supply circuit includes a gas discharge tube TV1, a fuse F3, a varistor R27, a diode D8, a diode D7, capacitors C24, C26, C23, C25, C1, C2, C3, C4, an inductor L1, a chip P2, and a processor chip U3. The bus isolation module includes processor chip U4, processor chip U2, TVS diode NUP2105, gas discharge tube 3R090A, resistor R, capacitor C8 and connector JP8. Pin 68 of processor chip U1 is connected to pin 1 of processor chip U4, pin 69 of processor chip U1 is connected to pin 2 of processor chip U4, and pins 6 and 7 of processor chip U4 are connected to pins 1 and 2 of connector JP8, respectively. The first pin of the TVS diode NUP2105 is connected to the sixth pin of the processor chip U4, and the second pin of the TVS diode NUP2105 is connected to the seventh pin of the processor chip U4.

2. The 485 bus data recording device circuit according to claim 1, characterized in that, The first pin of capacitor C10 is connected to the first pin of crystal oscillator Y1, and the second pin of capacitor C10 is connected to GND.

3. The 485 bus data recording device circuit according to claim 1, characterized in that, The first pins of capacitors C9 and C22 are connected to the first and third pins of crystal oscillator Y2, respectively, and the second pins of capacitors C9 and C22 are both connected to GND.

4. The 485 bus data recording device circuit according to claim 1, characterized in that, Pin 72 of the processor chip U1 is connected to pin 2 of connector JP4, pin 1 of connector JP4 is connected to VCC3.3 power supply, pin 3 of connector JP4 is connected to pin 76 of the processor chip U1, and pin 4 of connector JP4 is connected to GND.

5. The 485 bus data recording device circuit according to claim 1, characterized in that, The first pin of the fuse F3 is connected to 24V+. The second pin of the fuse F3 is connected to the first pins of the varistor R27, diode D1 and diode D8 respectively. The second pins of the varistor R27 and diode D1 are both connected to the GND network. The second pin of diode D8 is connected to the first pins of capacitor C24 and capacitor C26 respectively, and finally connected to the first pin of chip P2.

6. The 485 bus data recording device circuit according to claim 5, characterized in that, The second pin of chip P2 is connected to the first pin of inductor L1 and the first pin of diode D7. The second pin of inductor L1 is connected to the first pins of capacitors C23 and C25 respectively, outputting a 5V power supply. The second pins of diode D7, capacitor C23 and capacitor C25 are all connected to GND.

7. The 485 bus data recording device circuit according to claim 1, characterized in that, The first pin of the processor chip U3 is connected to the first pins of capacitors C1 and C2. The fifth pin of the processor chip U3 is connected to the first pins of capacitors C3 and C4 and outputs VCC power. The second pins of capacitors C1, C2, C3, and C4, as well as the second pin of the processor chip U3, are connected to the GND network.

8. The 485 bus data recording device circuit according to claim 1, characterized in that, The third pin of the TVS diode NUP2105 is simultaneously connected to the first pin of resistor R21 and capacitor C8. The second pin of resistor R21 and capacitor C8 is connected to the third pin of gas discharge tube 3R090A. The fifth pin of processor chip U4 is connected to the third pin of UP2105. The third pin of gas discharge tube 3R090A is connected to the third pin of connector JP8.

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