Circuit board
By using an embedded redistribution layer to achieve electrical connections between chips on the same or different layers, the problem of high cost in traditional circuit boards is solved, and signal transmission paths are shortened and low-cost circuit board designs are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- UNIMICRON TECH CORP
- Filing Date
- 2025-04-30
- Publication Date
- 2026-04-24
AI Technical Summary
Traditional circuit boards struggle to achieve both short signal transmission paths and low manufacturing costs, especially with the use of silicon through-hole (STI) interposers and embedded silicon bridges leading to increased costs.
An embedded redistribution layer is used to achieve electrical connections between wafers on the same or different layers, eliminating the need for silicon bridges or silicon interposers. Horizontal and vertical conduction are achieved through the embedded redistribution layer.
While shortening the signal transmission path, it reduces the manufacturing cost of the circuit board, and the overall thickness of the circuit board is also thinner because the silicon interposer is eliminated.
Smart Images
Figure CN224164929U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a circuit board, and more particularly to a circuit board containing a chip. Background Technology
[0002] In recent years, with the rapid development of artificial intelligence technology, various electronic products have increasingly higher requirements for computing efficiency. In order to improve computing efficiency by shortening the signal transmission path, some manufacturers use silicon interposers with through-silicon vias (TSVs) in the circuit boards of electronic products to achieve vertical signal transmission, or use embedded silicon bridges to achieve horizontal signal transmission.
[0003] However, both silicon interposers with through-silicon vias and embedded silicon bridges significantly increase the manufacturing cost of circuit boards. In other words, traditional circuit boards struggle to shorten signal transmission paths while maintaining low manufacturing costs. Utility Model Content
[0004] The present invention provides a circuit board that uses an embedded rewiring layer to electrically connect chips, thereby shortening the signal transmission path while maintaining low manufacturing cost of the circuit board.
[0005] An embodiment of this utility model discloses a circuit board comprising an embedded redistribution layer and two first chips. The two first chips are disposed on the same layer of the embedded redistribution layer and electrically connected to each other through the embedded redistribution layer.
[0006] In one embodiment of this utility model, the embedded redistribution layer includes a first embedded redistribution layer and a second embedded redistribution layer. The first embedded redistribution layer includes a first dielectric layer and a first circuit structure disposed in the first dielectric layer. The second embedded redistribution layer is disposed on the first embedded redistribution layer and includes a second dielectric layer and a second circuit structure disposed in the second dielectric layer. Two first chips are disposed on the first dielectric layer and are electrically connected to each other through the first circuit structure and the second circuit structure.
[0007] In one embodiment of this utility model, the embedded redistribution layer further includes a third embedded redistribution layer and two second chips. The third embedded redistribution layer is disposed on the second embedded redistribution layer and includes a third dielectric layer and a third circuit structure disposed in the third dielectric layer. The two second chips are disposed on the third dielectric layer and are electrically connected to the two first chips through the first circuit structure, the second circuit structure and the third circuit structure, respectively.
[0008] In one embodiment of this utility model, the embedded redistribution layer further includes a fourth embedded redistribution layer. The fourth embedded redistribution layer is disposed between the second and third embedded redistribution layers and includes a fourth dielectric layer and a fourth circuit structure disposed within the fourth dielectric layer. The two second chips are electrically connected to each other through the third and fourth circuit structures. The two second chips are electrically connected to the two first chips respectively through the first, second, third, and fourth circuit structures.
[0009] In one embodiment of this utility model, the circuit board further includes a solder resist layer. The solder resist layer is disposed on the third embedded redistribution layer and has two openings. Two second chips are respectively located in the two openings.
[0010] In one embodiment of this utility model, the circuit board further includes two encapsulating colloids. The two encapsulating colloids respectively fill the two openings and respectively encapsulate the two second wafers.
[0011] In one embodiment of this utility model, the first dielectric layer has two cavities. Two first wafers are respectively disposed in the two cavities.
[0012] In one embodiment of this utility model, the circuit board further includes two encapsulating colloids. The two encapsulating colloids respectively fill two cavities and respectively encapsulate two first wafers.
[0013] Another embodiment of this utility model discloses a circuit board comprising an embedded redistribution layer, a first chip, and a second chip. The first chip and the second chip are respectively disposed on different layers of the embedded redistribution layer and electrically connected to each other through the embedded redistribution layer.
[0014] In one embodiment of this utility model, the circuit board further includes a packaging substrate and a packaging colloid. The embedded redistribution layer is electrically connected to the packaging substrate, and the packaging colloid fills the space between the embedded redistribution layer and the packaging substrate.
[0015] According to the circuit board disclosed in the above embodiments, since horizontal conduction between two first wafers on the same layer or vertical conduction between a first wafer and a second wafer on different layers is achieved through an embedded redistribution layer, the provision of silicon bridges or silicon interposers can be eliminated. In this way, the signal transmission path in the circuit board can be shortened while maintaining low manufacturing costs.
[0016] In addition, silicon interposers typically have a certain thickness, so circuit boards can have a thinner overall thickness when the silicon interposer is omitted. Attached Figure Description
[0017] Figure 1 This is a cross-sectional schematic diagram of a circuit board according to the first embodiment of the present invention.
[0018] Figures 2 to 17 for Figure 1 Cross-sectional schematic diagrams of circuit boards at different process stages.
[0019] Figure 18 This is a cross-sectional schematic diagram of a circuit board according to the second embodiment of the present invention.
[0020] Figures 19 to 35 for Figure 18 Cross-sectional schematic diagrams of circuit boards at different process stages. Detailed Implementation
[0021] The following detailed description of the embodiments of this utility model outlines its features and advantages. This description is sufficient to enable any person skilled in the art to understand the technical content of the embodiments of this utility model and to implement them accordingly. Furthermore, based on the disclosure, claims, and drawings in this specification, any person skilled in the art can easily understand the related objectives and advantages of this utility model. The following embodiments further illustrate the viewpoints of this utility model in detail, but are not intended to limit the scope of this utility model in any way.
[0022] Please see Figure 1 . Figure 1 This is a cross-sectional schematic diagram of a circuit board according to a first embodiment of the present invention. In this embodiment, the circuit board 10 includes, for example, an embedded redistribution layer 50, a solder resist layer 400, two first wafers 500, two encapsulants 550, two second wafers 600, two encapsulants 650, an encapsulation substrate 700, and encapsulants 750.
[0023] In this embodiment, the embedded redistribution layer 50 includes, for example, a first embedded redistribution layer 100, a second embedded redistribution layer 200, and a third embedded redistribution layer 300. The first embedded redistribution layer 100 includes a first dielectric layer 110 and a first circuit structure 120 disposed in the first dielectric layer 110. The first dielectric layer 110, for example, has two cavities 111. The first circuit structure 120 includes, for example, a seed layer 121, a plurality of conductive vias 122, and a plurality of pads 123, 124, and 125.
[0024] The second embedded redistribution layer 200 is disposed on the first embedded redistribution layer 100 and includes a second dielectric layer 210 and a second circuit structure 220 disposed in the second dielectric layer 210. The second circuit structure 220 includes, for example, a plurality of conductive vias 221, 222 and a plurality of pads 223, 224, 225.
[0025] The third embedded redistribution layer 300 is disposed on the second embedded redistribution layer 200 and includes a third dielectric layer 310 and a third circuit structure 320 disposed in the third dielectric layer 310. The third circuit structure 320 includes, for example, a plurality of conductive vias 321, 322 and a plurality of pads 323, 324.
[0026] The solder resist layer 400 is disposed on the third embedded redistribution layer 300 and has two openings 410. Two pads 324 are respectively located in the two openings 410.
[0027] Two first chips 500 are disposed on the same layer of the embedded redistribution layer 50. Specifically, the two first chips 500 are disposed, for example, in two cavities 111 of the first dielectric layer 110. Two encapsulating colloids 550 are respectively filled in the two cavities 111 and respectively encapsulate the two first chips 500.
[0028] Two second wafers 600 are disposed on the third dielectric layer 310. Furthermore, the two second wafers 600 are respectively located in two openings 410. Two encapsulating colloids 650 are respectively filled in the two openings 410 and respectively encapsulate the two second wafers 600. The two first wafers 500 and the two second wafers 600 are respectively disposed on different layers of the embedded redistribution layer 50 (i.e., the first dielectric layer 110 and the third dielectric layer 310).
[0029] The electrical connection method of the first chip 500 and the second chip 600 will be described below. The two first chips 500 are electrically connected to each other through a first circuit structure 120 and a second circuit structure 220. Specifically, the two first chips 500 are electrically connected to each other through a pad 124, a conductive via 222, a pad 225, and a pad 125. It should be noted that in other embodiments, the first embedded redistribution layer and the second embedded redistribution layer may also be integrated into a single embedded redistribution layer, so that the two first chips are electrically connected to each other through the aforementioned single embedded redistribution layer.
[0030] Two second chips 600 are electrically connected to two first chips 500 via a first circuit structure 120, a second circuit structure 220, and a third circuit structure 320, respectively. Specifically, the two second chips 600 are electrically connected to the two first chips 500 via pads 324, conductive vias 322, 224, 222, and pads 124 and 125, respectively. It should be noted that in other embodiments, the first, second, and third embedded redistribution layers can be integrated into a single embedded redistribution layer, and the number of both first and second chips can be adjusted to one, with this first chip electrically connected to the second chip via the aforementioned single embedded redistribution layer.
[0031] Because horizontal communication between two first wafers 500 on the same layer or vertical communication between a first wafer 500 and a second wafer 600 on different layers is achieved through an embedded redistribution layer 50, the need for silicon bridges or silicon interposers can be eliminated. This allows for a shorter signal transmission path in the circuit board 10 while maintaining low manufacturing costs.
[0032] In addition, silicon interposers typically have a certain thickness, so the circuit board 10 can have a thinner overall thickness when the silicon interposer is omitted.
[0033] Furthermore, the two pads 124 are electrically connected to one of the first wafers 500, for example, through a seed layer 121 and two flux layers 126, respectively, and the pads 125 are electrically connected to the other first wafer 500, for example, through a seed layer 121 and two flux layers 127, respectively. The two pads 324 are electrically connected to the two second wafers 600, for example, through two flux layers 325, respectively.
[0034] In addition, the seed layer 121 is electrically connected to the pad 323 through the conductive via 122, the pad 123, the conductive via 221, the pad 223 and the conductive via 321.
[0035] An embedded redistribution layer is electrically connected to the package substrate 700. Specifically, the seed layer 121 is electrically connected to the package substrate 700 via two solder layers 710 and two solder balls 720. The encapsulant 750 is, for example, filled between the first dielectric layer 110 of the first embedded redistribution layer 100 and the package substrate 700.
[0036] The following will refer to Figures 1 to 17 Describe the manufacturing method of circuit board 10. Figures 2 to 17 for Figure 1 Cross-sectional schematic diagrams of circuit boards at different process stages.
[0037] like Figure 2 As shown, the release layer 30 is placed on the first temporary carrier plate 20. Figure 3 As shown, a patterned photoresist layer 40 (such as a dry film) is disposed on the release layer 30.
[0038] like Figure 3 and Figure 4 As shown, for example, a patterned photoresist layer 40 is used to form a circuit layer 50 and a surface treatment layer 60 on a release layer 30 using a photolithography process, and then the patterned photoresist layer 40 is removed. The circuit layer 50 is made of copper, for example. The surface treatment layer 60 is made of nickel, for example.
[0039] like Figure 5 As shown, for example, a first dielectric layer 110 is formed on the release layer 30 and the surface treatment layer 60 using a photolithography process. Figure 6 As shown, a seed layer 1210 is conformally formed on the first dielectric layer 110. As... Figure 7 As shown, a circuit layer 51 is formed on the seed layer 1210.
[0040] like Figure 8As shown, for example, a portion of the circuit layer 51 and a portion of the seed layer 1210 are removed by a planarization process to form a first circuit structure 120 including a seed layer 121, a conductive via 122, and pads 123, 124, and 125. The first dielectric layer 110 and the first circuit structure 120 together constitute a first embedded redistribution layer 100.
[0041] like Figure 9 As shown, a second embedded redistribution layer 200 is formed on the first dielectric layer 110 and the first circuit structure 120. Figure 10 As shown, a third embedded redistribution layer 300 is formed on the second embedded redistribution layer 200.
[0042] like Figure 11 As shown, a solder resist layer 400 is formed on the third embedded redistribution layer 300. (As indicated...) Figure 12 As shown, a second wafer 600 and an encapsulating colloid 650 covering the second wafer 600 are formed in the two openings 410 of the solder resist layer 400, respectively.
[0043] like Figure 13 As shown, the second temporary carrier plate 21 is placed on the solder resist layer 400. Figure 13 and Figure 14 As shown, the second temporary carrier 21 is reversed and the first temporary carrier 20 is removed.
[0044] like Figure 14 and Figure 15 As shown, the circuit layer 50 and the surface treatment layer 60 are removed from the two cavities 111 of the first dielectric layer 110. Figure 16 As shown, two first wafers 500 and two encapsulating colloids 550 are respectively disposed in two cavities 111.
[0045] like Figure 16 and Figure 17 As shown, remove the second temporary carrier plate 21 and reverse it. Figure 1 As shown, the first embedded redistribution layer 100 is electrically connected to the packaging substrate 700, and the space between the first embedded redistribution layer 100 and the packaging substrate 700 is filled with encapsulating adhesive 750. At this point, the manufacturing of the circuit board 10 is complete.
[0046] By using an embedded redistribution layer 50 instead of a silicon bridge or silicon interposer as the medium for transmitting signals, the complexity and difficulty of the circuit board 10 manufacturing process are reduced. Furthermore, since the embedded redistribution layer can be fabricated using, for example, photolithography instead of laser drilling, denser pads can be created in the circuit board 10, thereby increasing the number of I / Os in the circuit board 10.
[0047] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.
[0048] The embedded redistribution layer of this invention is not limited to a three-layer structure. Please refer to [link / reference]. Figure 18 . Figure 18 This is a cross-sectional schematic diagram of a circuit board according to the second embodiment of the present invention. The main difference between the circuit board 10a of this embodiment and the circuit board 10 of the first embodiment is that the embedded redistribution layer 50a of the circuit board 10a in this embodiment further includes a fourth embedded redistribution layer 800a, and the third circuit structure 320a of the third embedded redistribution layer 300a of the circuit board 10a additionally includes two conductive vias 322 and two pads 324. In detail, in this embodiment, the fourth embedded redistribution layer 800a is disposed between the second embedded redistribution layer 200 and the third embedded redistribution layer 300a, and includes a fourth dielectric layer 810a and a fourth circuit structure 820a disposed in the fourth dielectric layer 810a. The fourth circuit structure 820a includes, for example, a plurality of conductive vias 821a, 822a and a plurality of pads 823a, 824a, 825a.
[0049] The two second chips 600 are electrically connected to each other via a third circuit structure 320a and a fourth circuit structure 820a. Specifically, the two second chips 600 are electrically connected to each other, for example, via a pad 324, a conductive via 322, and a pad 825a. The two second chips 600 are electrically connected to the two first chips 500 via a first circuit structure 120, a second circuit structure 220, a third circuit structure 320a, and a fourth circuit structure 820a, respectively. Further, the second circuit structure 220 is electrically connected to the third circuit structure 320a, for example, via a conductive via 822a and a pad 824a.
[0050] The following will refer to Figures 18 to 35 Describe the manufacturing method of circuit board 10a. Figures 19 to 35 for Figure 18 Cross-sectional schematic diagrams of circuit boards at different process stages.
[0051] like Figure 19 As shown, the release layer 30 is placed on the first temporary carrier plate 20. Figure 20 As shown, a patterned photoresist layer 40 is disposed on the release layer 30.
[0052] like Figure 20 and Figure 21As shown, for example, a patterned photoresist layer 40 is used to form a circuit layer 50 and a surface treatment layer 60 on a release layer 30 using a photolithography process, and then the patterned photoresist layer 40 is removed.
[0053] like Figure 22 As shown, for example, a first dielectric layer 110 is formed on the release layer 30 and the surface treatment layer 60 using a photolithography process. Figure 23 As shown, a seed layer 1210 is conformally formed on the first dielectric layer 110. As... Figure 24 As shown, a circuit layer 51 is formed on the seed layer 1210.
[0054] like Figure 25 As shown, for example, a portion of the circuit layer 51 and a portion of the seed layer 1210 are removed by a planarization process to form a first circuit structure 120 including a seed layer 121, a conductive via 122, and pads 123, 124, and 125. The first dielectric layer 110 and the first circuit structure 120 together constitute a first embedded redistribution layer 100.
[0055] like Figure 26 As shown, a second embedded redistribution layer 200 is formed on the first dielectric layer 110 and the first circuit structure 120. Figure 27 As shown, a fourth embedded redistribution layer 800a is formed on the second embedded redistribution layer 200. Figure 28 As shown, a third embedded redistribution layer 300a is formed on the fourth embedded redistribution layer 800a.
[0056] like Figure 29 As shown, a solder resist layer 400 is formed on the third embedded redistribution layer 300a. (As indicated...) Figure 30 As shown, a second wafer 600 and an encapsulating colloid 650 covering the second wafer 600 are formed in the two openings 410 of the solder resist layer 400, respectively.
[0057] like Figure 31 As shown, the second temporary carrier plate 21 is placed on the solder resist layer 400. Figure 31 and Figure 32 As shown, the second temporary carrier 21 is reversed and the first temporary carrier 20 is removed.
[0058] like Figure 32 and Figure 33 As shown, the circuit layer 50 and the surface treatment layer 60 are removed from the two cavities 111 of the first dielectric layer 110. Figure 34 As shown, two first wafers 500 and two encapsulating colloids 550 are respectively disposed in two cavities 111.
[0059] like Figure 34 and Figure 35 As shown, remove the second temporary carrier plate 21 and reverse it. Figure 18 As shown, the first embedded redistribution layer 100 is electrically connected to the packaging substrate 700, and the space between the first embedded redistribution layer 100 and the packaging substrate 700 is filled with encapsulating adhesive 750. Thus, the manufacturing of the circuit board 10a is complete.
[0060] According to the circuit board disclosed in the above embodiments, since horizontal conduction between two first wafers on the same side or vertical conduction between a first wafer and a second wafer on different sides is achieved through a first embedded redistribution layer, the provision of silicon bridges or silicon interposers can be eliminated. In this way, the signal transmission path in the circuit board can be shortened while maintaining low manufacturing costs.
[0061] In addition, silicon interposers typically have a certain thickness, so circuit boards can have a thinner overall thickness when the silicon interposer is omitted.
[0062] [Symbol Explanation]
[0063] 10,10a: Circuit board
[0064] 50, 50a: Embedded redistribution layer
[0065] 100: First Embedded Rewire Layer
[0066] 110: First dielectric layer
[0067] 111: Cavity
[0068] 120: First Line Structure
[0069] 121: Seed Layer
[0070] 122,221,222,321,322,821a,822a: Conductive vias
[0071] 123,124,125,223,224,225,323,324,823a,824a,825a: Sealing pads
[0072] 126, 127, 325, 710: Solder flux layer
[0073] 200: Second Embedded Rewiring Layer
[0074] 210: Second dielectric layer
[0075] 220: Second line structure
[0076] 300, 300a: Third Embedded Rewiring Layer
[0077] 310: Third dielectric layer
[0078] 320, 320a: Third line structure
[0079] 400: Solder resist layer
[0080] 410: Opening
[0081] 500: First chip
[0082] 550, 650, 750: Encapsulating colloids
[0083] 600: Second chip
[0084] 700: Packaging substrate
[0085] 720: Welding ball
[0086] 800a: Fourth Embedded Rewiring Layer
[0087] 810a: Fourth dielectric layer
[0088] 820a: Fourth line structure
[0089] 20: First temporary carrier board
[0090] 21: Second Temporary Carrier
[0091] 30: Release layer
[0092] 40: Patterned photoresist layer
[0093] 50, 51: Line Layer
[0094] 60: Surface treatment layer
[0095] 1210: Seed layer.
Claims
1. A circuit board, characterized in that, Include: Embedded redistribution layer; and The first chip and the second chip are respectively disposed on different layers of the embedded redistribution layer and electrically connected to each other through the embedded redistribution layer.
2. The circuit board according to claim 1, characterized in that, The number of the first wafers is two, and the two first wafers are disposed on the same layer of the embedded redistribution layer and electrically connected to each other through the embedded redistribution layer.
3. The circuit board according to claim 2, characterized in that, The embedded redistribution layer includes a first embedded redistribution layer and a second embedded redistribution layer. The first embedded redistribution layer includes a first dielectric layer and a first circuit structure disposed in the first dielectric layer. The second embedded redistribution layer is disposed on the first embedded redistribution layer and includes a second dielectric layer and a second circuit structure disposed in the second dielectric layer. The two first chips are disposed on the first dielectric layer and are electrically connected to each other through the first circuit structure and the second circuit structure.
4. The circuit board according to claim 3, characterized in that, The embedded redistribution layer further includes a third embedded redistribution layer. There are two second wafers. The third embedded redistribution layer is disposed on the second embedded redistribution layer and includes a third dielectric layer and a third circuit structure disposed in the third dielectric layer. The two second wafers are disposed on the third dielectric layer and are electrically connected to the two first wafers through the first circuit structure, the second circuit structure and the third circuit structure, respectively.
5. The circuit board according to claim 4, characterized in that, The embedded redistribution layer further includes a fourth embedded redistribution layer, which is disposed between the second embedded redistribution layer and the third embedded redistribution layer, and includes a fourth dielectric layer and a fourth circuit structure disposed in the fourth dielectric layer. The two second chips are electrically connected to each other through the third circuit structure and the fourth circuit structure, and the two second chips are electrically connected to the two first chips through the first circuit structure, the second circuit structure, the third circuit structure and the fourth circuit structure, respectively.
6. The circuit board according to claim 4, characterized in that, It also includes a solder resist layer disposed on the third embedded redistribution layer and having two openings, wherein the two second wafers are respectively located in the two openings.
7. The circuit board according to claim 6, characterized in that, It also includes two encapsulating colloids, which fill the two openings respectively and encapsulate the two second wafers respectively.
8. The circuit board according to claim 3, characterized in that, The first dielectric layer has two cavities, and the two first wafers are respectively disposed in the two cavities.
9. The circuit board according to claim 8, characterized in that, It also includes two encapsulating colloids, which fill the two cavities respectively and encapsulate the two first wafers.
10. The circuit board according to claim 1 or 2, characterized in that, It also includes a packaging substrate and a packaging colloid, wherein the embedded redistribution layer is electrically connected to the packaging substrate, and the packaging colloid fills the space between the embedded redistribution layer and the packaging substrate.