Semiconductor structure

Abstract

The semiconductor structure includes a plurality of backside power lines and a memory unit. A plurality of backside power lines are on the semiconductor substrate. The memory unit is located above the plurality of backside power lines. The memory unit comprises a first pull-up transistor and a second pull-up transistor which are positioned at a first height, and a first pull-down transistor and a second pull-down transistor which are positioned at a second height different from the first height; and a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor at a third height different from the first height and the second height.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to the production of generation after generation of ICs, each generation being smaller and more complex than the last. However, these advancements have also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are necessary to realize these advancements.

[0003] In the evolution of integrated circuits, functional density (i.e., the number of interconnect components per wafer region) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also results in relatively high power dissipation values, which can be addressed by using low-power dissipation components such as complementary metal-oxide-semiconductor (CMOS) devices. Utility Model Content

[0004] In some embodiments, the semiconductor structure includes a plurality of back-side power lines and a memory cell. The plurality of back-side power lines are located on a semiconductor substrate. The memory cell is located above the plurality of back-side power lines. The memory cell includes a first pull-up transistor and a second pull-up transistor located at a first height, a first pull-down transistor and a second pull-down transistor located at a second height different from the first height, and a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor located at a third height different from the first and second heights.

[0005] In some embodiments, the semiconductor structure includes a substrate, a first bottom-layer pull-up transistor, a second bottom-layer pull-up transistor, a first middle-layer pull-down transistor, a second middle-layer pull-down transistor, a first top-layer switching transistor, a second top-layer switching transistor, a third top-layer switching transistor, and a fourth top-layer switching transistor. The first and second bottom-layer pull-up transistors are located above the substrate, and are included within a memory cell. The first and second middle-layer pull-down transistors are located above the first and second bottom-layer pull-up transistors, and are included within a memory cell. The first, second, third, and fourth top-layer switching transistors are located above the first and second middle-layer pull-down transistors, and are included within a memory cell.

[0006] In some embodiments, the semiconductor structure includes a substrate, a first semiconductor nanostructure, a plurality of first epitaxial structures, a first gate structure, a second semiconductor nanostructure, a third semiconductor nanostructure, a fourth semiconductor nanostructure, a fifth semiconductor nanostructure, a plurality of second epitaxial structures, a plurality of third epitaxial structures, a plurality of fourth epitaxial structures, a plurality of fifth epitaxial structures, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure. The first semiconductor nanostructure is located at a first height above the substrate, wherein the first semiconductor nanostructure is included in a static random access memory (SRAM) cell. The plurality of first epitaxial structures are located on opposite sides of the first semiconductor nanostructure. The first gate structure surrounds the first semiconductor nanostructure. The second, third, fourth, and fifth semiconductor nanostructures are located at a second height above the substrate, wherein the second, third, fourth, and fifth semiconductor nanostructures are included in the SRAM cell. The plurality of second epitaxial structures are located on opposite sides of the second semiconductor nanostructure. The plurality of third epitaxial structures are located on opposite sides of the third semiconductor nanostructure. The plurality of fourth epitaxial structures are located on opposite sides of the fourth semiconductor nanostructure. Multiple fifth epitaxial structures are located on opposite sides of the fifth semiconductor nanostructure. A second gate structure surrounds the second semiconductor nanostructure. A third gate structure surrounds the third semiconductor nanostructure. A fourth gate structure surrounds the fourth semiconductor nanostructure. A fifth gate structure surrounds the fifth semiconductor nanostructure. Attached Figure Description

[0007] When viewed in conjunction with the accompanying drawings, the best understanding of the nature of this disclosure is derived from the following detailed illustrations. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 The layout of a static random access memory (SRAM) array according to some embodiments of the present disclosure is illustrated, the layout including a sensing amplifier and a word line driver;

[0009] Figure 2A and Figure 2B Circuit diagrams according to some embodiments of this disclosure are shown;

[0010] Figure 3A and Figure 3B A perspective view of a semiconductor structure according to some embodiments of the present disclosure is shown;

[0011] Figure 3C Some embodiments according to this disclosure are illustrated. Figure 3B A magnified view of the central region R1;

[0012] Figure 4A and Figure 4B The top-level semiconductor structure layout according to some embodiments of this disclosure is illustrated;

[0013] Figures 5 to 10B It depicts the from Figure 3A and Figure 3B The cross-sectional views obtained from reference sections A1-A1', B1-B1', A2-A2', B2-B2', A3-A3', B3-B3', A4-A4', B4-B4', A5-A5', B5-B5', A6-A6', and B6-B6'.

[0014] Figure 11A and Figure 11B The illustration shows a comparative analysis of the read time of two types of static random access memory bit cells in static random access memory arrays at different locations, according to some embodiments of the present disclosure.

[0015] Figure 11C and Figure 11DThe illustration shows a comparative analysis of the energy delay product of two types of state random access memory (SRAM) bit cells in state random access memory arrays at different locations, according to some embodiments of this disclosure.

[0016] Figures 12 to 55B The illustration shows a schematic diagram of an intermediate stage in the formation of a semiconductor structure according to some embodiments of the present disclosure.

[0017] [Symbol Explanation]

[0018] 1: Location

[0019] 2: Location

[0020] 3: Location

[0021] 4: Location

[0022] 5: Static Random Access Memory Array

[0023] 6: Sensing Amplifier

[0024] 7: Word line driver

[0025] 10a: Static Random Access Memory (SRAM) bit unit

[0026] 10b: Static Random Access Memory (SRAM) bit unit

[0027] 100: Substrate

[0028] 101: Sacrifice Layer

[0029] 102: Channel Layer

[0030] 103a: Contact

[0031] 103b: Contact

[0032] 103c: Contact

[0033] 103d: Contact

[0034] 104: Dummy Gate Layer

[0035] 105: Hard mask layer

[0036] 106: Gate spacer layer

[0037] 106': Spacer material

[0038] 107: Internal spacer layer

[0039] 108: Source / Drain Region

[0040] 109: Source / Drain Contact

[0041] 110: Interlayer dielectric layer

[0042] 111: Interface Layer

[0043] 113: High dielectric constant dielectric layer

[0044] 115: Gate electrode layer

[0045] 117: Hard mask layer

[0046] 121: Mid-section line layer

[0047] 201: Sacrifice Layer

[0048] 202: Channel Layer

[0049] 203a: Contact

[0050] 203a1: Contact

[0051] 203a2: Contact

[0052] 203b: Contact

[0053] 203c: Contact

[0054] 203d: Contact

[0055] 203d1 contact

[0056] 203d2 contact

[0057] 203e: Contact

[0058] 203f: Contact

[0059] 204: Dummy gate layer

[0060] 205: Hard mask layer

[0061] 206: Gate spacer layer

[0062] 206': Spacer material

[0063] 207: Internal spacer layer

[0064] 208: Source / Drain Region

[0065] 209: Source / Drain Contact

[0066] 210: Interlayer dielectric layer

[0067] 211: Interface Layer

[0068] 213: High dielectric constant dielectric layer

[0069] 215: Gate electrode layer

[0070] 217: Hard mask layer

[0071] 221: Mid-section line layer

[0072] 301: Sacrificial Layer

[0073] 302: Channel Layer

[0074] 303a: Contact

[0075] 303b: Contact

[0076] 304: Dummy gate layer

[0077] 305: Hard mask layer

[0078] 306: Gate spacer

[0079] 306': Spacer material

[0080] 308: Source / Drain Region

[0081] 309: Source / Drain Contact

[0082] 310: Interlayer dielectric layer

[0083] 311: Interface Layer

[0084] 313: High dielectric constant dielectric layer

[0085] 315: Gate electrode layer

[0086] 317: Hard mask layer

[0087] 322: Interconnection Structure

[0088] 323: Intermetallic dielectric layer

[0089] 403a: Contact

[0090] 403b: Contact

[0091] 403c: Contact

[0092] 403d: Contact

[0093] 403e: Contact

[0094] 403f: Contact

[0095] 403g: Contact

[0096] 403h: Contact

[0097] 404a: Contact

[0098] 404b: Contact

[0099] 404c: Contact

[0100] 404d: Contact

[0101] 404e: Contact

[0102] 404F: Contact

[0103] 404g: Contact

[0104] 404h: Contact

[0105] A1-A1': Reference section

[0106] A2-A2': Reference section

[0107] A3-A3': Reference section

[0108] A4-A4': Reference Section

[0109] A5-A5': Reference Section

[0110] A6-A6': Reference Section

[0111] B1-B1': Reference section

[0112] B2-B2': Reference section

[0113] B3-B3': Reference Section

[0114] B4-B4': Reference Section

[0115] B5-B5': Reference Section

[0116] B6-B6': Reference Section

[0117] BL: Bitline

[0118] BL1: Bitline

[0119] BL2: Bitline

[0120] BLB: Bitline

[0121] BLB1: Bitline

[0122] BLB2: Bitline

[0123] BLB2: Bitline

[0124] C1: Dataset

[0125] C2: Dataset

[0126] C3: Dataset

[0127] C4: Dataset

[0128] C5: Dataset

[0129] C6: Dataset

[0130] C7: Dataset

[0131] C8: Dataset

[0132] C1-C1': Reference section

[0133] G1: Gate structure

[0134] G2: Gate structure

[0135] G3: Gate structure

[0136] M1: First metal layer

[0137] M2: Second metal layer

[0138] O11: Opening

[0139] O21: Opening

[0140] O31: Opening

[0141] PG L1 :transistor

[0142] PG L2 :transistor

[0143] PD L :transistor

[0144] PD R :transistor

[0145] PG R1 :transistor

[0146] PG R2 :transistor

[0147] PU L :transistor

[0148] PU R :transistor

[0149] Q: Storage Node

[0150] QB: Storage Node

[0151] R1: Region

[0152] R11: Groove

[0153] R12: Groove

[0154] R13: Groove

[0155] R14: Groove

[0156] R21: Groove

[0157] R22: Groove

[0158] R23: Groove

[0159] R24: Groove

[0160] R31: Groove

[0161] R32: Groove

[0162] R33: Groove

[0163] R34: Groove

[0164] WL: Word Line

[0165] WL1: Wordline

[0166] WL2: Wordline

[0167] VDD: Voltage source line

[0168] VSS: Grounding wire

[0169] VSS-1: Grounding wire

[0170] VSS-2: Grounding wire Detailed Implementation

[0171] The following disclosure provides numerous different implementations or examples for implementing various features of the provided object. Specific examples of components and configurations are illustrated below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following illustrations, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define the relationships between the various implementations and / or configurations discussed.

[0172] Additionally, for ease of illustration, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, are used herein to illustrate the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Elements may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative illustration terms used herein may be interpreted accordingly. As used herein, “approximately,” “probably,” “around,” or “substantially” can mean within 20%, 10%, or 5% of a given value or range. However, those skilled in the art will understand that the values ​​or ranges listed throughout the illustrations are merely examples and may decrease as integrated circuits shrink. The numerical values ​​disclosed herein are approximate, and unless explicitly stated otherwise, terms such as “approximately,” “probably,” “around,” or “substantially” can be inferred.

[0173] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning, unless expressly defined herein.

[0174] Gate-all-around (GAA) field-effect transistor (FET) structures can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have, for example, smaller spacing than a single, direct photolithography process. For example, in some implementations, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Using a self-alignment process, a spacer layer is formed alongside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacer layer can be used to pattern the gate-all-around FET structure.

[0175] Throughout the development of integrated circuits (ICs), there has been a continuous trend towards increasing functional density—the number of interconnect components per unit wafer area—while simultaneously reducing geometric dimensions, representing the smallest components or lines that can be created using manufacturing processes. To improve the functional density of IC structures, a method has been proposed using complementary field-effect transistors (CFETs), where p-type and n-type CFETs are vertically stacked. Various embodiments disclosed herein provide improved static random access memory (SRAM) bit cell configurations, focusing on read-enhanced and dual-port versions, both utilizing a three-layer architecture with 8 transistors (8T), maintaining the same physical footprint as a standard 6T high-density SRAM bit cell (e.g., 4 transistors). Read-enhanced SRAM bit cells (see...) Figure 2A and Figure 3A Two pairs of switching transistors can be included at the top layer to improve read operations by increasing transistor strength without increasing the bit cell area. Dual-port static random access memory (SRAM) bit cells (see...) Figure 2B and Figure 3B It can contain two pairs of switching transistors, each controlled by a separate word line, allowing independent access to memory cells and supporting simultaneous read / write operations. Furthermore, the enhanced read / dual-port static random access memory (SRAM) bit cell can have the same pull-down transistors and pull-up transistors configuration as the 6T SRAM bit cell.

[0176] See Figure 1 . Figure 1 The layout of a static random access memory array 5 according to some embodiments of the present disclosure is illustrated, including a sensing amplifier 6 and a word line driver 7. Figure 1The static random access memory (SRAM) array 5 includes multiple SRAM bits. A sense amplifier 6 is strategically placed on one side of the SRAM array 5 to facilitate fast and sensitive detection of stored data status by amplifying signal differences between bit lines. A word line driver 7 can be placed on the other side of the SRAM array 5 to activate word lines for accessing stored data in the corresponding bit. The SRAM bits can be placed at least at the four corners of the SRAM array 5 at positions 1, 2, 3, and 4. Each position provides a unique proximity to the sense amplifier 6 and word line driver 7, affecting the performance of the bit. In some embodiments, the SRAM bit at position 1 may be close to the sense amplifier 6 and word line driver 7, potentially providing the fastest access and response times. The SRAM bit at position 2 may be close to the sense amplifier 6 but far from the word line driver 7, potentially experiencing slower access due to longer word line drive times. The static random access memory (SRAM) bit cell at location 3 may be close to word line driver 7 but far from sense amplifier 6, which could affect the speed and accuracy of data sensing. The SRAM bit cell at location 4 may be far from both sense amplifier 6 and word line driver 7, potentially resulting in the slowest access and sensing speeds. Due to the varying distances of the bit cells from sense amplifier 6 and word line driver 7, performance within the SRAM array 5 may be inconsistent. Bit cells closer to these components may perform better than those farther away.

[0177] Therefore, in order to address performance differences and improve the overall functionality of the static random access memory array 5, various embodiments disclosed herein provide circuit diagrams and structures as shown in the following figures (i.e., Figure 2A and Figure 2B These improvements aim to stabilize and accelerate operation, regardless of the specific location of the bit cells in the static random access memory array 5, by adjusting the circuit layout, enhancing connectivity, and / or integrating additional components, in order to standardize the performance of different bit cell locations in the static random access memory array 5.

[0178] See Figure 2A and Figure 2B . Figure 2A and Figure 2B Circuit diagrams according to some embodiments of this disclosure are illustrated. Specifically, Figure 2A and Figure 2B Two configurations of static random access memory (SRAM) bits are illustrated, such as enhanced read SRAM bit 10a and dual-port SRAM bit 10b. Although Figure 2B The illustration shows the relationship with Figure 2AThis disclosure describes different configurations of static random access memory (SRAM) bit units 10a and 10b, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0179] like Figure 2A As shown, the enhanced read static random access memory bit cell 10a may contain two pairs of pass-gate transistors PG. L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2 This enables and disables access to memory elements. Furthermore, enhanced read static random access memory (SRAM) bit cells can contain a pair of pull-down transistors (PDs). L and pull-down transistor PD R During write operations, the bit cell is driven to a logic low state. Furthermore, enhanced read-enabled static random access memory bit cells can contain a pair of pull-up transistors (PUs). L and pull-up transistor PU R This drives the cell to a logic high state, ensuring the stability of the stored data. Therefore, the transistor ratio (e.g., pull-down:pull-up:switch) can be 1:1:2. All switching transistors PG L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2 It can be connected to the common word line WL, simplifying control but enhancing read operations by providing stronger or faster access. Switching transistor PG L1 and switching transistor PG L2 The source / drain nodes can be connected to the common data line (i.e., the bit line BL), while the switching transistor PG... R1 and switching transistor PG R2 The source / drain nodes can be connected to a common complementary bit line (BLB). In some implementations, the complementary bit line (BLB) may be referred to alternately as a bit line or bit bar.

[0180] The term "read-enhanced" refers to improvements made to the static random access memory (SRAM) bit cell 10a to enhance its read performance, increasing read speed and reliability, making it suitable for high-performance applications requiring fast data access. Additional switching transistor PG L2 and switching transistor PG R2 A stronger and faster path can be provided to read data from the storage node, thus reducing access time because bit lines can charge or discharge more quickly. Furthermore, by adding a switching transistor PG... L2 and switching transistor PG R2 The number of static random access memory bit cells 10a can drive bit lines BL and / or bit lines BLB with stronger driving capability, thereby improving signal integrity and reducing the possibility of errors caused by voltage fluctuations or noise.

[0181] like Figure 2B As shown, similar to the enhanced read static random access memory (SRAM) bit cell 10a, the dual-port SRAM bit cell 10b may include two pairs of switching transistors PG. L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2 Each enhanced read static random access memory bit cell 10a may also include a pair of pull-down transistors PD. L and pull-down transistor PD R and a pair of pull-up transistors PU L and pull-up transistor PU R This mimics the configuration of the enhanced read bit unit 10a. The difference between the enhanced read static random access memory bit unit 10a and the dual-port static random access memory bit unit 10b lies in the fact that each pair of switching transistors PG in the dual-port static random access memory bit unit 10b... L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2 Connecting to different word lines WL1 and WL2 allows independent access to different portions of the static random access memory (SRAM) bit cell 10b. The transistor ratio (e.g., pull-down:pull-up: first port switch: second port switch) can be 1:1:1:1. Switch transistor PG L1 and switching transistor PG L2 The source / drain nodes can be connected to a separate data line (i.e., the switching transistor PG). L1 Bit line BL1 and switching transistor PG L2 (Bio line BL2), switching transistor PG R1and switching transistor PG R2 The source / drain nodes can be similarly connected to a separate data line (i.e., the switching transistor PG). R1 Bit line BLB1 and switching transistor PG R2 (Bib line BLB2). In some implementations, complementary bit lines BLB1 / BLB2 may be referred to alternately as bit lines.

[0182] The term "dual-port" refers to the Static Random Access Memory (SRAM) unit 10b supporting two independent access ports, allowing it to handle two separate access operations (e.g., read / write) simultaneously. This is suitable for systems requiring high throughput and flexible memory management. In the SRAM unit 10b, each pair of switching transistors can be controlled by separate word lines WL1 and WL2, allowing independent operation on each port without interference, suitable for applications requiring high data bandwidth and parallel processing. Furthermore, the ability to perform two operations simultaneously (e.g., read from one port while write to another) increases the throughput of the memory system. Therefore, additional switching transistors (e.g., switching transistor PG) are used. L2 and switching transistor PG R2 The enhanced read and dual-port static random access memory (SRAM) bits 10a and 10b can improve their respective capabilities (e.g., improve the speed and stability of reads from SRAM bit 10a, and the concurrency and throughput of dual-port SRAM bit 10b). These improvements address performance challenges in computing environments, making them indispensable for applications requiring robust, high-speed memory solutions.

[0183] Back Figure 2A and Figure 2B The enhanced read and dual-port static random access memory (SRAM) bit units 10a and 10b each use eight transistors (8T). The SRAM bit unit 10b can have additional functionality in write port form; therefore, the SRAM bit unit 10b can be referred to as a dual-port 8T SRAM bit unit. Figure 2A In the middle, a pair of switching transistors PG L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2 A pair of data lines, referred to as bit lines BL and BLB, can be coupled to inversely correlated storage nodes QB and Q. Bit lines BL and BLB can form a pair of complementary data lines. In some implementations, Figure 2A These paired data lines shown can be coupled to a differential sense amplifier (see...). Figure 1 It can sense and amplify differential voltage. This amplified sense output signal can then be output as data to other logic circuits in the component.

[0184] exist Figure 2B In the middle, a pair of switching transistors PG L1 and switching transistor PG R1 A pair of data lines, referred to as bit lines BL1 and BLB1, can be coupled to inverting correlated memory nodes QB and Q, while a pair of switching transistors PG... L2 and PG R2 A pair of data lines, referred to as bit lines BL2 and BLB2, can be coupled to inversely correlated memory nodes QB and Q. Bit lines BL1 and BLB1 can form a pair of complementary data lines, while bit lines BL2 and BLB2 can form a pair of complementary data lines. In some implementations, Figure 2B These paired data lines shown can be coupled to differential sense amplifier 6 (see...) Figure 1 It can sense and amplify differential voltage. This amplified sense output signal can then be output as data to other logic circuits in the component.

[0185] The supply voltage of the voltage source line VDD can range from 0.6 volts to 3.0 volts or higher, depending on the technology node, as shown in the diagram. The pull-up transistor PU of the enhanced read / dual-port static random access memory (SRAM) bit cell 10a / SRAM bit cell 10b is also shown. L and pull-up transistor PU R The positive power supply can be coupled to one of the memory nodes based on the state of static random access memory (SRAM) bits 10a / 10b. The diagram also shows the second supply voltage, grounded via ground line VSS, which is typically placed at ground. Two pull-down transistors PD are also shown. L and pull-down transistor PD R A negative voltage or the ground voltage of the ground wire VSS can be coupled to one or the other of the memory nodes labeled QB and Q, depending on the state of static random access memory (SRAM) bits 10a / 10b. SRAM bits 10a / 10b can be a latch that will retain its data state indefinitely, provided the supply voltage is high enough for the circuit to function correctly.

[0186] Composed of transistor PU R Transistor PU L Transistor PD R Transistor PD LTransistor PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L2 The two inverters formed can be "cross-coupled" and can operate continuously to enhance the stored charge on memory nodes QB and Q. The two memory nodes QB and Q can be inverted relative to each other as shown in the figure. When Figure 2A When the static random access memory (SRAM) bit cell 10a shown is written to, the complementary write data signal can be placed on the bit line pair (i.e., bit line BL and bit line BLB). The positive control signal on the word line WL can be coupled to the switching transistor PG. R1 Switching transistor PG R2 Switching transistor PG L1 and switching transistor PG L2 The gate of the transistor. In some embodiments, the word line WL can be a dedicated write word line in the static random access memory bit cell 10a. L Transistor PD R Transistor PU L Transistor PD R It can be designed to overwrite stored data on bit lines BL and BLB, thereby writing to or programming static random access memory (SRAM) bit cell 10a. When SRAM bit cell 10a is read, a positive voltage is applied to word line WL, switching transistor PG. R1 Transistor PG R2 Transistor PG L1 and transistor PG L2 Bit lines BL and BLB are allowed to couple to and receive data from storage nodes QB and Q.

[0187] when Figure 2B When the static random access memory (SRAM) bit cell 10b shown is written to, the complementary write data signal can be placed on the first bit line pair (i.e., bit line BL1 and bit line BLB1) and / or the second bit line pair (i.e., bit line BL2 and bit line BLB2). The first positive control signal on word line WL1 can be coupled to the switching transistor PG. R1 and switching transistor PG L1 The gate and / or the second positive control signal on word line WL2 can be coupled to the switching transistor PG. R2 and switching transistor PG L2 The gate of the transistor. In some embodiments, word lines WL1 and WL2 may be dedicated write word lines in the static random access memory bit cell 10b. L Transistor PD RTransistor PU L Transistor PD R It can be designed to overwrite stored data on bit lines BL1, BL2, BLB1, and BLB2, thereby writing to or programming static random access memory (SRAM) bit cell 10b. When SRAM bit cell 10b is read, a positive voltage is applied to word line WL1 and / or word line WL2, switching transistor PG. R1 Switching transistor PG R2 Switching transistor PG L1 and switching transistor PG L2 Bit lines BL1, BL2, BLB1, and BLB2 are allowed to couple to and receive data from storage nodes QB and Q. Unlike dynamic memory cells, if the supply voltage of the voltage source line VDD is kept at a sufficiently high level, static random access memory (SRAM) bit cells 10a / 10b will not lose their storage state during reading, and therefore no "write-back" operation is required after reading.

[0188] In some implementations, transistor PD R Transistor PD L PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L2 It can be a first conductivity type, transistor PU R and transistor PU L It can be of a second conductivity type, the opposite of the first conductivity type. As an example and not a limitation, the transistor PD... R Transistor PD L Transistor PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L1 It can be an n-type transistor (e.g., an N-type metal-oxide-semiconductor (NMOS) transistor), while the transistor PU R and transistor PU L It can be a p-type transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). In some embodiments, the transistor PD R Transistor PD L Transistor PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L1 It can be a p-type transistor (e.g., a PMOS transistor), while PU R and PU LIt can be an n-type transistor (e.g., an NMOS transistor).

[0189] See Figure 3A , Figure 4A , Figures 5 to 7 , Figure 8A , Figure 9A and Figure 10A . Figure 3A A perspective view of the semiconductor structure of a static random access memory bit cell 10a according to some embodiments of the present disclosure is shown, such as... Figure 2A As shown. Figure 4B The layout of the top-level semiconductor structure according to some embodiments of this disclosure is illustrated. Figures 5 to 7 , Figure 8A , Figure 9A and Figure 10A It depicts the from Figure 3A The cross-sectional views are obtained from reference sections A1-A1', A2-A2', A3-A3', A4-A4', A5-A5', and A6-A6'. In some embodiments, the semiconductor structure may include an underlying transistor PU. R and underlying transistor PU L (See Figure 3A and Figure 6 ), middle-layer transistor PD R and middle layer transistor PD L (See Figure 3A and Figure 7 ), and the top-level transistor PG R1 Top-level transistor PG R2 Top-level transistor PG L1 and top-level transistor PG L2 (See Figure 3A and Figure 8A In other words, transistor PU. R and PU L It can be located at the first layer height, transistor PD R and transistor PD L It can be located at a second layer height higher than the first layer height, transistor PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L2 It can be located at a third floor height, which is higher than the second floor height.

[0190] In some embodiments, the transistor PD on the substrate 100 L The occupied area (see) Figure 55A and Figure 55B It can be used with transistors on substrate 100. LThe occupied area overlaps vertically, while the transistor PD R The occupied area can be the same as that of the transistor PU on the substrate 100. R The occupied area overlaps vertically. Transistor PG on substrate 100 L1 The occupied area can be the same as that of the transistor PD on the substrate 100. L The occupied area overlaps vertically, while the transistor PG on the substrate 100 R2 The occupied area can be the same as that of the transistor PD on the substrate 100. R The occupied area overlaps vertically. On the other hand, transistor PD L Channel layer 202 (see Figure 7 It can be used with transistors on substrate 100. L Channel layer 102 (see Figure 6 Vertically overlapped, while transistor PD R The channel layer 202 can be perpendicularly overlapped with the channel layer 102 of the transistor PUR. Transistor PG L1 Channel layer 302 (see Figure 8A It can be used with transistor PD L The channel layers 202 are vertically overlapped, while the transistor PG R2 The channel layer 302 can be connected to the transistor PD. R The channel layers 202 are vertically overlapped. In some embodiments, the transistor PU R and transistor PU L Transistor PD R Transistor PD L Transistor PG R1 Transistor PG R2 Transistor PG L1 and transistor PG L2 It can be positioned in more or less than three layers.

[0191] like Figure 3A and Figure 6 As shown, transistor PU R and transistor PU L Each may include a channel layer 102, a gate structure G1 enclosing the channel layer 102, and source / drain regions 108 located on both sides of the gate structure G1 and connected to the channel layer 102 (see Figure 3A Transistor PD R and transistor PD L Each may include a channel layer 202 and a gate structure G2 that encloses the channel layer 202 (see Figure 3A And the source / drain regions 208 located on both sides of the gate structure G2 and connected to the channel layer 202. Transistor PG R1 Transistor PG R2 Transistor PGL1 and transistor PG L2 Each may include a channel layer 302 and a gate structure G3 that surrounds the channel layer 302 (see Figure 3A The gate structure G1, gate structure G2, and / or gate structure G3 are located on both sides of the gate structure G3 and connected to the channel layer 302. In some embodiments, the transistors in the static random access memory bit cell 10a may include various channel geometries, such as nanosheets, Fin Field-Effect Transistors (FinFETs), nanowires, and TreeFETs. In some embodiments, channel layer 102, channel layer 202, and / or channel layer 302 may be alternately referred to as channel pattern, channel region, channel line, semiconductor layer, or semiconductor nanostructure. In some embodiments, source / drain region 108, source / drain region 208, and / or source / drain region 308 may be alternately referred to as source / drain pattern, epitaxial pattern, source / drain structure, or epitaxial structure. In some embodiments, gate structure G1, gate structure G2, and / or gate structure G3 may be alternately referred to as gate, gate pattern, gate strip, gate layer, functional gate, metal layer, or metal strip.

[0192] about Figure 3A , Figure 5 and Figure 6 The underlying transistor PU shown R and transistor PU L Transistor PU L One source / drain region 108 can be electrically coupled to the underlying voltage source line VDD via contact 103a. Transistor PU L Another source / drain region 108 can be electrically coupled to transistor PU via contact 103b. R The gate structure G1. Similarly, one source / drain region 108 of transistor PUR is electrically coupled to the underlying voltage source line VDD via contact 103c. Transistor PU R Another source / drain region 108 can be electrically coupled to transistor PU through contact 103d. L The gate structure G1.

[0193] about Figure 3A and Figure 7 The middle layer transistor PD shown R and transistor PD L Transistor PD L One source / drain region 208 is electrically coupled to the underlying ground wire VSS-1 via contact 203a. (Transistor PD) L Another source / drain region 208 is connected via contact 203b (see...) Figure 3A Electrically coupled to transistor PU LThe bottom source / drain region 208 is electrically coupled to the transistor PG through the bottom source / drain contact 109. L1 and transistor PG L2 The shared top-level source / drain region 308, and through contact 303a (see Figure 3A Electrical connection. In addition, transistor PD L The gate structure G2 is connected via contact 203c (see Figure 6 and Figure 7 Electrically coupled to the underlying transistor PU L The gate structure G1. Similarly, the transistor PD R One source / drain region 208 is electrically coupled to the underlying ground wire VSS-2 via contact 203d. (Transistor PD) R Another source / drain region 208 is connected via contact 203e (see...) Figure 3A Electrically coupled to the underlying transistor PU R The source / drain region 208 is electrically coupled to the transistor PG through the bottom source / drain contact 109. L2 and PG R2 The shared top-level source / drain region is 308. Furthermore, the transistor PD... R The gate structure G2 is electrically coupled to the underlying transistor PU through contact 203f. L The gate structure G1.

[0194] In some embodiments, the voltage source line VDD and / or ground lines VSS-1 / VSS-2 can be alternately referred to as back-side power lines or embedded metallic power lines. In some embodiments, the voltage source line VDD, ground lines VSS-1 and VSS-2 can be collectively referred to as a backside power delivery network (BSPDN). In some embodiments, by integrating the backside power delivery network and complementary field-effect transistor (CFPT) technology, the implementation of multi-port CFPT static random access memory (SRAM) can reduce routing complexity. This approach not only simplifies the internal architecture of the SRAM cell 10a but also improves overall circuit efficiency and reliability. In some embodiments, the voltage source line VDD and ground lines VSS-1 and VSS-2 can be fabricated and positioned above the front of the SRAM cell 10a as back end ofline (BEOL).

[0195] about Figure 3A , Figure 4A , Figure 8A , Figure 9A and Figure 10A The top-level transistor PG shown L1 Transistor PG L2Transistor PG R1 and transistor PG R2 transistor PG L1 and transistor PG L2 The non-common source / drain regions 308 are electrically coupled to the upper-layer bit line BL through contacts 403a and 403b, respectively. Transistor PG L1 and transistor PG L2 The gate structure G3 is electrically coupled to the upper word line WL through contacts 403c and 403d. Similarly, transistor PG... R1 and transistor PG R2 The non-common source / drain regions 308 are electrically coupled to the upper-layer bit line BLB via contacts 403e and 403f, respectively. Transistor PG R1 and transistor PG R2 The gate structure G3 is electrically coupled to the upper word line WL through contacts 403g and 403h.

[0196] See Figure 3B , Figure 3C , Figure 4B , Figures 5 to 7 , Figure 8B , Figure 9B and Figure 10B . Figure 3B A perspective view of the semiconductor structure of a static random access memory bit cell 10b according to some embodiments of the present disclosure is shown, such as... Figure 2B As shown. Figure 3C Some embodiments according to this disclosure are illustrated. Figure 3B A magnified view of the central region R1. Figure 4B The layout of the top-level semiconductor structure according to some embodiments of this disclosure is illustrated. Figures 5 to 7 , Figure 8B , Figure 9B and Figure 10B It depicts the from Figure 3B The cross-sectional views obtained from reference sections B1-B1', B2-B2', B3-B3', B4-B4', B5-B5', and B6-B6'. Although Figure 3B The illustration shows the relationship with Figure 3A The present disclosure describes different configurations of static random access memory (SRAM) bit units 10a and 10b, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0197] Specifically, static random access memory (SRAM) bit cells 10a and 10b have the same three-layer transistor layout and power supply connections, but differ in their data access and control methods. The pull-up transistor PU of SRAM bit cell 10b... R and pull-up transistor PU L Located at the bottom layer, these transistors are connected to the voltage source line VDD, responsible for setting the memory node to a high state. Pull-down transistor PD R and pull-down transistor PD L Located in the middle layer and connected to ground lines VSS-1 and VSS-2, these transistors pull the storage node low. Switching transistor PG R1 Switching transistor PG R2 Switching transistor PG L1 and switching transistor PG L2 Located at the top layer, these transistors control access to memory nodes QB and Q, and play a role in read and write operations.

[0198] Unlike static random access memory (SRAM) bit cell 10a, where the switching transistors are connected to a pair of common bit lines (e.g., bit line BL and bit line BLB), SRAM bit cell 10b may have a dual-port configuration. SRAM bit cell 10b may have a pair of switching transistors PG. L1 and switching transistor PG L2 Connected to a separate bit line, switching transistor PG L1 Connect to bit line BL1, switch transistor PG L2 Connected to bit line BL2. This allows for individual control and access to different portions of the static random access memory (SRAM) bit cell 10a, facilitating independent operation or enhancing parallel processing capabilities. The SRAM bit cell 10b may also have a second pair of switching transistors PG. R1 and switching transistor PG R2 Connected to a separate bit line, switching transistor PG L2 Connect to bit line BLB1, switch transistor PG R2 Connected to bit line BLB2, it reflects the function of the first pair but on complementary bit lines (e.g., bit lines BLB1 and BLB2).

[0199] In addition, each pair of switching transistors PG L1 Switching transistor PG L2 Switching transistor PG R1 and switching transistor PG R2Unlike static random access memory (SRAM) bit cell 10a, where all switching transistors are connected to a single word line WL, SRAM bit cell 10b can connect to different word lines WL1 and WL2. This configuration in SRAM bit cell 10b allows each pair of transistors to operate independently, supporting dual-port functionality, which improves the flexibility and efficiency of the SRAM in multi-threaded environments. SRAM bit cell 10b's ability to connect each pair of switching transistors to separate word and bit lines effectively doubles the access paths into the cell, enhancing its ability to perform read / write operations simultaneously or handle two independent processes.

[0200] about Figure 3B , Figure 4B , Figure 8B , Figure 9B and Figure 10B The top-level transistor PG shown L1 Top-level transistor PG L2 Top-level transistor PG R1 and top-level transistor PG R2 transistor PG L1 The non-shared source / drain region 308 is connected via contact 404a (see...) Figure 8B and Figure 9B Electrically coupled to the upper-level bit line BL1, transistor PG L2 The non-common source / drain region 308 is electrically coupled to the upper bit line BL2 via contact 404b. Transistor PG L1 The gate structure G3 is electrically coupled to the upper word line WL1 via contact 404c, and the transistor PG L2 The gate structure G3 is electrically coupled to the upper word line WL2 via contact 404d. Similarly, transistor PG... R1 The non-shared source / drain region 308 is connected to contact 404e (see...) Figure 8B and Figure 9B Electrically coupled to the upper-level bit line BLB1, transistor PG R2 The non-common source / drain region 308 is electrically coupled to the upper-layer bit line BLB2 via contact 404f. R1 The gate structure G3 is electrically coupled to the upper word line WL1 via contact 404g, and the transistor PG R2 The gate structure G3 is electrically coupled to the upper word line WL2 via contact 404h. In some embodiments, bit lines BL1, BL2, BLB1, and BLB2 can be formed on the first metal layer M1, which is higher than the transistor PG. L1 Transistor PG L2 Transistor PG R1 and transistor PG R2Word lines WL1 and WL2 can be formed on a second metal layer M2, which is higher than the first metal layer M1.

[0201] In some implementations, the fabrication processes for enhanced read and dual-port static random access memory (SRAM) bit cells 10a and 10b can be methodologically standardized, utilizing a sequential (epitaxical 3D) process to construct a three-layer high-density (HD) SRAM architecture. This sequential process flow can extend to the fabrication of the top-layer transistors. This standardized approach ensures efficiency and consistency in integrated circuit structure production in the early stages of manufacturing, and then branches off in the final stages to meet the specific requirements of the top-layer transistors in each SRAM bit cell design.

[0202] See Figure 11A and Figure 11B . Figure 11A and Figure 11B The diagram illustrates four different locations within the static random access memory array (e.g., Figure 1 Two types of static random access memory bits (e.g., positions 1, 2, 3, and 4) are shown. Figure 2A The diagram shows a comparative analysis of the read times of a 6T static random access memory (SRAM) bit cell and an 8T bit cell (10a). The 6T SRAM bit cell can include a three-layer configuration: a top layer with a pair of switching transistors, a middle layer with a pair of pull-down transistors, and a bottom layer with a pair of pull-up transistors. The transistor ratio (e.g., pull-down:pull-up:switching) can be 1:1:1. These figures reveal the impact of voltage differences on bit lines BL and BLB, and the associated SRAM bit cell read times. Furthermore, Figure 11A The data is plotted under the condition that the voltage difference between bit line BL and bit line BLB is approximately 100mV. Figure 11B The data is plotted under the condition that the voltage difference between bit line BL and bit line BLB is approximately 30mV. Figure 11A and Figure 11B In the diagram, datasets C1 and C3 represent the read time of 6TB static random access memory (SRAM) bits, while datasets C2 and C4 represent... Figure 2A The read time of the 8T static random access memory bit cell 10a shown.

[0203] like Figure 11AAs shown, when the voltage difference is approximately 100mV, the 8T static random access memory (SRAM) bit cell 10a exhibits faster read times than the 6T bit cell at all locations. Specifically, at location 1, the read time of the 8T bit cell is 3-10% faster than the 6T bit cell, such as 3, 4, 5, 5.3, 6, 7, 8, 9, or 10%. At location 4, the read time of the 8T bit cell is 3-10% faster than the 6T bit cell, such as 5, 6, 7, 7.6, 8, 9, 10, 11, 12, 13, 14, or 15%.

[0204] like Figure 11B As shown, even with a reduced voltage difference of 30mV, the read time of the 8T static random access memory (SRAM) bit cell 10a at the corresponding location is still faster than that of the 6T bit cell. Specifically, at location 1, the read time of the 8T bit cell is 2-8% faster than that of the 6T bit cell, such as 2, 3, 3.6, 4, 5, 5.3, 6, 7, or 8%. At location 4, the read time of the 8T bit cell is 3-10% faster than that of the 6T bit cell, such as 5, 6, 7, 7.6, 8, 9, 10, 10.6, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20%.

[0205] Therefore, the 8T static random access memory (SRAM) bit cell 10a exhibits consistently better read time performance, which can be attributed to the more powerful switching transistors used in the 8T bit cell configuration. The 8T bit cell allows for increased discharge speeds of bit lines BL and BLB, thus facilitating faster read operations. Furthermore, Figure 11A and Figure 11B The illustration shows that the 8T static random access memory (SRAM) bit cell is not only faster but also more efficient in handling larger voltage swings. The variability in improvements across different locations can be represented by the fact that while the 8T SRAM bit cell 10a provides an overall improvement in read time, improvements are made closer to surrounding components (such as the sense amplifier 5 and the word line driver 6, see...). Figure 1 Factors such as )) may affect the degree of improvement.

[0206] Figure 11C and Figure 11D The diagram illustrates four different locations within the static random access memory array (e.g., Figure 1 Two types of static random access memory bits (e.g., positions 1, 2, 3, and 4) are shown. Figure 2A The comparison analysis of the read energy delay product (EDP) for 6T and 8T bit cells (10a) is shown. These figures reveal the impact of voltage difference on bit lines BL and BLB, as well as the related read energy delay product of static random access memory (SRAM) bit cells. Furthermore, Figure 11CThe data is plotted under the condition that the voltage difference between bit line BL and bit line BLB is approximately 100mV. Figure 11D The data is plotted under the condition that the voltage difference between bit line BL and bit line BLB is approximately 30mV. Figure 11A and Figure 11B In the dataset, datasets C5 and C7 represent the read energy latency product of 6T static random access memory bits, while datasets C6 and C8 represent... Figure 2A The read energy delay product of the 8T static random access memory bit cell 10a shown.

[0207] like Figure 11C As shown, when the voltage difference is approximately 100mV, the 8T static random access memory bit cell 10a exhibits a higher read energy delay product at all locations than the 6T bit cell. Figure 11D As shown, even with a reduced voltage difference of 30mV, the read energy delay product at the corresponding location for an 8T static random access memory (SRAM) bit cell 10a is still higher than that for a 6T bit cell. When the voltage difference between the bit lines decreases from 100mV to 30mV, the reduction in the energy delay product for the 8T SRAM bit cell 10a is greater than that for the 6T bit cell. This indicates that the 8T SRAM bit cell 10a is more sensitive to changes in voltage difference, possibly due to its enhanced switching and discharging mechanisms. For example, the energy delay product of a 6T SRAM bit cell can be reduced by approximately 40-60%, such as approximately 40, 45, 47, 50, 55, or 60%. The energy delay product of the 8T SRAM bit cell 10a is reduced even more, ranging from 70-90%, such as approximately 70, 75, 77, 80, 85, or 90%. In some implementations, at lower voltage differentials (e.g., 30mV), the energy delay product of an 8T static random access memory (SRAM) bit cell 10a is only about 10-15% higher than that of a 6T SRAM bit cell, such as about 10, 11, 12, 13, 14, or 15%. This closer performance under reduced voltage differential conditions suggests that the 8T SRAM bit cell 10a may be more efficient or comparable under lower bit line stress. In some implementations, the calculation of the energy delay product includes factors such as word line activation, bit line discharge, and recharging to the supply voltage.

[0208] See Figures 12 to 55B . Figures 12 to 55B Schematic diagrams illustrating intermediate stages in the formation of a semiconductor structure according to some embodiments of this disclosure are provided. Specifically, Figure 12 , Figure 26 , Figure 27A , Figure 40A , Figure 41A , Figure 54A and Figure 55A A three-dimensional diagram illustrating a semiconductor structure formed according to some implementation methods is shown. Figure 13A , Figures 14 to 25 , Figure 27B , Figure 28A , Figures 29 to 39 , Figure 40B , Figure 41B , Figures 42B to 53 , Figure 54B and Figure 55B A cross-sectional view obtained from a reference section C1-C1' during the formation of a semiconductor structure, according to some embodiments, is illustrated. Figure 13B , Figure 28B , Figure 42A A top view illustrating a semiconductor structure formed according to some embodiments is shown. It should be understood that, in Figures 12 to 55B Other operations may be provided before, during, and after the process shown, and some of the operations described below may be replaced or omitted to implement other embodiments of the method. The order of operations / processes may be interchanged.

[0209] See Figures 12 to 13B .like Figure 12As shown, an epitaxial stack is formed on substrate 100. In some embodiments, substrate 100 may include silicon (Si). Alternatively, substrate 100 may include germanium (Ge), silicon-germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP; or combinations thereof) or other suitable semiconductor materials. In some embodiments, substrate 100 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Additionally, substrate 100 may include a buried dielectric layer, such as a buried oxide (BOX) layer, which can be formed by separation by implantation of oxygen (SIMOX), wafer bonding, selective epitaxial growth (SEG), or other suitable methods. Substrate 100 may include buried metal. The embedded metal may include a voltage source line VDD and ground lines VSS-1 and VSS-2. In some embodiments, the embedded metal may include power vias, back contacts, self-aligned front and rear vias, etc. In some embodiments, the voltage source line VDD, ground lines VSS-1 and VSS-2 may be, for example, but not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, tantalum nitride, aluminum titanium, aluminum titanium nitride, other suitable materials or combinations thereof, and may be formed by any suitable process. Ground lines VSS-1 and VSS-2, as well as the voltage source line VDD, may be formed at the same height level.

[0210] like Figure 13A and Figure 13BAs shown, the epitaxial stack comprises alternating sacrificial layers 101 of a first composition and channel layers 102 of a second composition. In some embodiments, the sacrificial layer 101 may be made of silicon-germanium (SiGe) and have a different germanium atom concentration than the channel layer 102. In some embodiments, the sacrificial layer 101 may have a higher germanium atom concentration than the channel layer 102. In some embodiments, the channel layer 102 may be made of silicon (Si). For example, but not limited to, the germanium atom concentration of the sacrificial layer 101 may be in the range of about 10% to 90%, such as about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%. However, other embodiments are also possible, including first and second compositions that provide different etch selectivity.

[0211] The use of channel layer 102 to define element channels or pathways will be discussed further below. It should be noted that... Figure 13A The channel layer 102 illustrated herein is for illustrative purposes only and should not be considered as exceeding the limitations specifically described in the claims. It is understood that any number of sacrificial layers 101 can be formed in the epitaxial stack; the specific number depends on the desired number of transistor channel regions. In some embodiments, the number of channel layers 102 can be between about 1 and 101, such as 1, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, or 101. As described in more detail below, the channel layer 102 can be used as a channel region for a subsequently formed semiconductor device, and the thickness is selected based on device performance considerations. For example, but not limited to, the thickness of the channel layer 102 can be in the range of about 0.5 to 50 nm, such as about 0.5, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50 nm. In some embodiments, the length of the channel layer 102 can be in the range of about 5 to 500 nm, such as about 5, 50, 100, 150, 200, 250, 300, 350, 400, 450, or 500 nm. In some embodiments, the channel layer 102 can have a square / rectangular / diamond cross-sectional profile along the longitudinal direction of the gate structure. The sacrificial layer 101 in the channel region may eventually be removed and used to define the vertical distance between adjacent channel regions of subsequently formed multi-gate elements, and the thickness is selected based on device performance considerations. In some embodiments, the thickness of the sacrificial layer 101 can be in the range of about 5 to 100 nm, such as about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 nm.

[0212] For example, the epitaxial growth of the epitaxial stack can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as channel layer 102, may comprise the same material as the substrate 100. In some embodiments, the sacrificial layer 101 and channel layer 102 may comprise materials different from those of the substrate 100. As described above, in at least some examples, the sacrificial layer 101 may comprise an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 102 may comprise an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either the sacrificial layer 101 or the channel layer 102 may comprise other materials, such as germanium, tin, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as SiGe, GeSn, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, III-V, or combinations thereof. In some embodiments, the channel layer 102 may comprise group IV materials such as Si, Ge, Sn, Si 1-x Ge x 、Ge 1-y Sn y Si 1-x-y Ge x Sn y Other suitable materials or combinations thereof. In some embodiments, channel layer 102 may include III-V group materials, oxide semiconductor materials, 2D (two-dimensional) materials, other suitable materials, or combinations thereof. As previously described, the materials of sacrificial layer 101 and channel layer 102 may be selected to provide different oxidation and / or etch selectivity characteristics.

[0213] Subsequently, the epitaxial stack, including channel layer 102 and sacrificial layer 101, can be patterned such that channel layer 102 and sacrificial layer 101, or portions thereof, can be formed as shown in the image. Figure 13BThe nanostructure is shown. Specifically, channel layer 102 can form the nanostructure channel of a nanostructured transistor. The term "nanostructure" as used herein refers to any portion of material having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of this portion. Therefore, the term refers both to elongated material portions with circular and near-circular cross-sections and to beam or strip-shaped material portions, such as cylindrical or near-rectangular cross-sections. For example, a nanostructure is a nanosheet, nanowire, nanoplate, or nanoring based on its geometry. The patterned channel layer 102 and sacrificial layer 101 can be fabricated using appropriate processes, including dual-patterning or multi-patterning processes.

[0214] See Figure 14 The dummy gate layer 104 and the hard mask layer 105 can be formed on the epitaxial stack, such as... Figure 13A and Figure 13B As shown. The portion of the channel layer 102 below the dummy gate layer 104 can be referred to as the channel region. The dummy gate layer 104 can also define the source / drain region 108 (marked in...). Figure 20 (Middle). The dummy gate formation operation forms a dummy gate layer 104 and a hard mask layer 105 over the dummy gate layer 104. The hard mask layer 105 is then patterned, and subsequently the patterned hard mask layer 105 is used as an etch mask to pattern the dummy gate layer 104. The etch process may include wet etching, dry etching, and / or combinations thereof.

[0215] In some embodiments, the dummy gate layer 104 may include polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, or metals. In some embodiments, the dummy gate layer 104 may include metal-containing materials such as TiN, TaN, TaC, Co, Ru, Al, and combinations thereof or multilayer structures. The hard mask layer 105 may be made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbide (SiOC), or similar materials, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. In some embodiments, the dummy gate layer 104 may be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other techniques suitable for depositing conductive materials. In some embodiments, the hard mask layer 105 may be deposited by CVD, PVD, sputtering deposition, or other techniques suitable for depositing conductive materials. In some implementations, the dummy gate layer 104 may be referred to interchangeably as a dummy gate, a dummy gate pattern, a dummy gate strip, an isolation structure, or a dielectric gate.

[0216] See Figure 15 The dummy gate layer 104 is etched laterally or horizontally using a suitable etching technique, resulting in a lateral groove R11 vertically formed between the sacrificial layer 101 and the hard mask layer 105. This operation can be accomplished using a selective etching process. For example, but not limited to, the sacrificial layer 101 can be made of silicon germanium (SiGe), the hard mask layer 105 can be made of a dielectric material, and the dummy gate layer 104 can be made of silicon, allowing selective etching of the dummy gate layer 104. In some embodiments, selective dry etching etches the silicon at a faster rate than etching the silicon germanium (SiGe) and the dielectric material. As a result, the sacrificial layer 101 and the hard mask layer 105 extend laterally beyond the corresponding end faces of the dummy gate layer 104.

[0217] See Figure 16 After the etch-back of the dummy gate layer 104 is completed, a spacer material 106' is deposited on the substrate 100. The spacer material 106' may be a conformal layer located on the uppermost sacrificial layer 101, the dummy gate layer 104, and the hard mask layer 105. The spacer material 106' may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material 106' may include multiple layers, such as a first spacer layer and a second spacer layer formed on the first spacer layer. For example, the spacer material 106' may be formed by depositing a dielectric material on the uppermost sacrificial layer 101, the dummy gate layer 104, and the hard mask layer 105 using a suitable deposition process.

[0218] See Figure 17 The deposited spacer material 106' is then anisotropically etched to expose the uppermost sacrificial layer 101 and the hard mask layer 105. This anisotropic etching process completely removes the spacer material 106' directly located on the hard mask layer 105 and portions of the spacer material 106' not covered by the hard mask layer 105 on the uppermost sacrificial layer 101. The portion of the spacer material 106' located on the sidewall of the etch-back dummy gate layer 104 can remain in the lateral groove R11, forming the gate sidewall spacer layer 106, referred to as the gate spacer layer 106. In some embodiments, the lateral dimension (or thickness) of the sidewall spacer layer 106 can be in the range of about 1 to 25 nm, such as about 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, or 25 nm.

[0219] See Figure 18The patterned channel layer 102 and patterned sacrificial layer 101 beyond the gate spacer layer 106 are etched using, for example, an anisotropic etching process. This process uses a dummy gate layer 104 and gate spacer layer 106 as an etching mask, resulting in the formation of recesses R12 in the channel layer 102 and sacrificial layer 101. After anisotropic etching, the end faces of the patterned channel layer 102 and patterned sacrificial layer 101, as well as the outermost sidewall of the gate spacer layer 106, are substantially coplanar due to the anisotropic etching. In some embodiments, anisotropic etching can be performed by dry chemical etching with a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR), a transformer coupled plasma (TCP), an electron cyclotron resonance (ECR) source, or a similar element. The reaction gas can be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or similar gases), a chlorine-based gas (such as Cl2), hydrogen bromide gas (HBr), oxygen (O2), or a combination thereof.

[0220] See Figure 19 The patterned sacrificial layer 101 is etched laterally or horizontally using a suitable etching technique to form a lateral groove R13. This operation can be accomplished using a selective etching process. For example, but not limited to, the sacrificial layer 101 can be made of silicon germanium (SiGe), while the channel layer 102 can be made of silicon, allowing selective etching of the sacrificial layer 101. In some embodiments, selective dry etching etches silicon germanium (SiGe) at a faster rate than etching silicon. As a result, the patterned channel layer 102 extends laterally beyond the corresponding end face of the patterned sacrificial layer 101.

[0221] Subsequently, an inner spacer 107 is filled into the recess R13. For example, a spacer material layer is formed to fill the recess R13 left by the lateral etch sacrificial layer 101 discussed above. The spacer material layer can be a low-dielectric-constant material, such as SiO2, SiN, SiC, SiON, SiCN, or SiOCN, and can be formed by a suitable deposition method (such as ALD). In some embodiments, the spacer material layer is intrinsic or undoped. The spacer material layer can be formed by CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. After depositing the spacer material layer, an anisotropic etch process can be performed to trim the deposited spacer material layer, leaving a portion of the deposited spacer material layer filling the recess R13 left by the lateral etch sacrificial layer 101. After the trimming process, the remaining portion of the deposited spacer layer in the recess R13 is referred to as the inner spacer 107. The inner spacer 107 is used to isolate the metal gate and source / drain regions in subsequent processing.

[0222] See Figure 20 A source / drain region 108 is formed in a recess R12 and connected to the channel layer 102. The source / drain region 108 can be formed by providing epitaxial material on the substrate 100 through an epitaxial growth process. In the epitaxial growth process, a dummy gate layer 104, a gate spacer layer 106, and an internal spacer layer 107 confine the source / drain region 108 to the substrate 100 and the channel layer 102. In some embodiments, the lattice constant of the source / drain region 108 differs from the lattice constant of the channel layer 102 so that the source / drain region 108 can strain or compress the channel layer 102 to improve the carrier mobility of the semiconductor device and enhance device performance. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the composition of channel layer 102.

[0223] In some embodiments, the source / drain region 108 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain region 108 may be in-situ doped during the epitaxial process by introducing dopant species, including: p-type dopant such as boron or BF2; n-type dopant such as phosphorus or arsenic; and / or other suitable dopant, including combinations thereof. If the source / drain region 108 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain region 108. In some embodiments, the source / drain region 108 may be a p-type transistor and includes SiGeB and / or GeSnB.

[0224] See Figure 21 Source / drain contacts 109 may be formed on source / drain regions 108. In some embodiments, source / drain contacts 109 may include, but are not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, tantalum carbon nitride, titanium aluminum, aluminum titanium nitride, other suitable materials, or combinations thereof. In some embodiments, the formation of source / drain contacts 109 may be performed, for example, by a lift-off process. For example, but not limited to, a mask layer (not shown) may be formed by depositing a photoresist layer on substrate 100 using a suitable process (such as spin coating), which may include post-coating baking of the photoresist layer. In some embodiments, the mask layer may include a positive-type or negative-type photoresist material. The mask layer may be patterned to form openings exposing the source / drain contacts 109. Subsequently, contact material can be deposited on the substrate 100 and formed on the source / drain contacts 109 and the patterned mask layer. The substrate 100 can then be immersed in a bath of a suitable solvent that will react with the patterned mask layer. The patterned mask layer may expand, dissolve, and peel off the contact material formed on the patterned mask layer, with the remaining contact material on the source / drain regions 108 partially forming the source / drain contacts 109.

[0225] See Figure 22An interlayer dielectric (ILD) layer 110 is formed on the substrate 100. In some embodiments, the interlayer dielectric layer 110 comprises an oxide formed of tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 110 may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 110, the substrate 100 may be subjected to high-temperature treatment to anneal the interlayer dielectric layer 110. Subsequently, a planarization process (e.g., CMP) is performed to remove excess interlayer dielectric layer 110 until the hard mask layer 105 is exposed. In some embodiments, the hard mask layer 105 may also serve as an etch stop layer for etching the interlayer dielectric layer 110.

[0226] See Figure 23 A hard masking layer 117 may be formed on the interlayer dielectric layer 110 and the hard masking layer 105. In some embodiments, the hard masking layer 117 may be made of the same material as the interlayer dielectric layer 110, thereby forming a substantially indistinguishable interface between the hard masking layer 117 and the interlayer dielectric layer 110. In some embodiments, the hard masking layer 117 may be made of a different material than the interlayer dielectric layer 110. In some embodiments, the hard masking layer 117 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide oxycarbide (SiOC), tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, other suitable materials, or combinations thereof. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. In some embodiments, the hard mask layer 117 can be formed by any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. Subsequently, the hard mask layer 117 is patterned and then used to etch the dummy gate layer 104 (see...). Figure 22The hard mask layer 105 and the interlayer dielectric layer 110 are included. The hard mask layer 117 can be patterned by photolithography processes, including photoresist (or resist) coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes, and / or combinations thereof. Etching processes include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching).

[0227] After forming the patterned hard mask layer 117, the dummy gate layer 104 can be etched through the patterned hard mask layer 117 (see...). Figure 22 A hard mask layer 105 and an interlayer dielectric layer 110 are formed to create an opening O11. The opening O11 exposes the sidewalls of the epitaxial stack, allowing the channel layer 102 and the sacrificial layer 101 to be exposed. The etching process may include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). In some embodiments, the opening O11 may have a rectangular profile extending along the Y direction from a top view. After the opening O11 is formed, the patterned mask can be removed using appropriate techniques such as wet cleaning, ashing, or similar techniques.

[0228] Sacrificial layer 101 (see) Figure 23 The sacrificial layer 101 is removed in one or more etching processes, allowing a recess R14 to be formed to inherit the shape of a lower sacrificial layer 101. The recess R14 can expose the bottom surface of the channel layer 102, and the opening O11 can expose the top surface of the channel layer 102. In some embodiments, the sacrificial layer 101 can be removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a selective etching reactive gas that selectively etches the sacrificial layer 101 at a faster rate than the substrate 100, the interlayer dielectric layer 110, and the channel layer 102.

[0229] See Figure 24The interfacial layer 111 and the high-dielectric-constant dielectric layer 113 may be conformally formed on the hard mask layer 117 and in the opening O11 and the groove R14. In some embodiments, the interfacial layer 111 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some embodiments, the interfacial layer 111 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. In some embodiments, the high dielectric constant dielectric layer 113 may include a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicate (LaSiO), aluminum silicate (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof. In some embodiments, the high dielectric constant dielectric layer 113 can be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof.

[0230] Subsequently, a gate electrode layer 115 may be deposited on the high-dielectric-constant dielectric layer 113. The gate electrode layer 115 may include a work function metal layer and / or a fill metal formed around the work function metal layer. The work function metal layer and / or the fill metal may include metal, metal alloy, or metal silicide. For an n-type fin field-effect transistor, the work function metal layer may include one or more n-type work function metals (N metals). The n-type work function metal may include, but is not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type fin field-effect transistor, the work function metal layer may include one or more p-type work function metals (P metals). p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the filler metal may include, but is not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, tantalum carbon nitride, titanium aluminum, titanium aluminum nitride, or other suitable materials.

[0231] See Figure 25 A planarization process (e.g., CMP) is performed to remove excess gate electrode layer 115, high-k dielectric layer 113, interface layer 111, and hard mask layers 105 and 117 located above gate spacer layer 106. Gate spacer layer 106 can also serve as an etch stop layer for etching gate electrode layer 115, high-k dielectric layer 113, interface layer 111, and hard mask layers 105 and 117. Therefore, a (metallic) gate structure G1 comprising gate electrode layer 115, high-k dielectric layer 113, and interface layer 111 can be formed in recess R14 to surround channel layer 102 suspended in recess R14. In some embodiments, gate structure G1 can be the final gate of gate-all-around field-effect transistor (GAA FET). Therefore, the semiconductor structure can include transistor PU. R and transistor PU L (See Figure 3A and Figure 25 Transistor PU R and transistor PU L Each may include a channel layer 102, a gate structure G1 surrounding the channel layer 102, and source / drain regions 108 connected to the channel layer 102 and located on both sides of the gate structure G1. In some embodiments, transistor PU Rand transistor PU L They can be interchangeably referred to as underlying transistors.

[0232] See Figure 26 Contact 203a1 can be formed to penetrate the interlayer dielectric layer 110 and connect the transistor PD. L The first source / drain region 208 (see Figure 3A Connect to the lower ground line VSS-1. Contact 203d1 can be formed to pass through the interlayer dielectric layer 110 and connect the transistor PD. R The first source / drain region 208 (see Figure 3A Connected to the lower grounding wire VSS-2. In some embodiments, contacts 203a1 and 203d1 may include, but are not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, carbon tantalum nitride, titanium aluminum, aluminum titanium nitride, other suitable materials or combinations thereof, and their formation can be carried out by any suitable process.

[0233] See Figure 27A and Figure 27B In transistor PU R and transistor PU L A middle-end-of-line (MEOL) layer 121 can be formed on top. The MEOL layer 121 may include an inter-metal dielectric layer and conductive interconnects to house the transistor PU. R and transistor PU L Connected to upper-layer features (e.g., transistor PG) R1 Transistor PG L2 Transistor PG R1 Transistor PG L2 Transistor PD R and transistor PD L In some embodiments, the intermetallic dielectric layer may include, for example, an oxide formed of tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0234] In some embodiments, the conductive interconnects formed in the intermetallic dielectric layer may include contacts 203a2, 203d2, 203b, 203e, 203c, and 203f. Contact 203a2 may be formed on contact 203a1, and contact 203d2 may be formed on contact 203d1. In some embodiments, contacts 203a1 and 203a2 may be collectively referred to as... Figure 3AThe contacts 203a, 203d1, and 203d2 shown can be collectively referred to as Figure 3A Contact 203d is shown. Contact 203b can be formed on transistor PU. L On the source / drain contact 109, contact 203e can be formed on the transistor PU. R On the source / drain contact 109. Contact 203c (see...) Figure 6 It can be formed on the lower-layer transistor PU L On the gate structure G1, contact 203f (see Figure 6 It can be formed on the lower-layer transistor PU R On the gate structure G1. In some embodiments, the conductive interconnects may be made of tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, carbon tantalum nitride, titanium aluminum, titanium aluminum nitride, or other suitable materials.

[0235] See Figure 28A and Figure 28B An epitaxial stack is formed on the intermediate circuit layer 121. The epitaxial stack comprises an alternating sacrificial layer 201 of a first composition and a channel layer 202 of a second composition. The first and second compositions may be different. In some embodiments, the sacrificial layer 201 may be made of silicon germanium (SiGe) and have a germanium atom concentration different from that of the channel layer 202. In some embodiments, the channel layer 201 may be made of silicon (Si). In some embodiments, the germanium atom concentration of the sacrificial layer 201 may be higher than that of the channel layer 202. For example, but not limited to, the germanium atom concentration of the sacrificial layer 201 may be in the range of about 10% to 90%, such as about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%. However, other embodiments are also possible, including providing different etch selectivity between the first and second compositions.

[0236] The use of channel layer 202 to define element channels or pathways will be discussed further below. It should be noted that... Figure 28AThe channel layer 202 illustrated herein is for illustrative purposes only and should not be construed as exceeding the limitations specifically described in the claims. It is understood that any number of sacrificial layers can be formed in the epitaxial stack; the specific number depends on the desired number of transistor channel regions. In some embodiments, the number of channel layers 202 can be between about 1 and 100, such as 1, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, or 101. As described in more detail below, channel layer 202 can be used as a channel region for subsequently formed semiconductor devices, and the thickness is selected based on device performance considerations. For example, but not limited to, the thickness of channel layer 202 can be in the range of about 0.5 to 50 nm, such as about 0.5, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50 nm. In some embodiments, the length of the channel layer 202 can be in the range of about 5 to 500 nm, such as about 5, 50, 100, 150, 200, 250, 300, 350, 400, 450, or 500 nm. In some embodiments, the channel layer 202 can have a square / rectangular / diamond cross-sectional profile along the longitudinal direction of the gate structure. The sacrificial layer 201 in the channel region may eventually be removed and used to define the vertical distance between adjacent channel regions of subsequently formed multi-gate elements, and its thickness is selected based on device performance considerations. In some embodiments, the thickness of the sacrificial layer 201 can be in the range of about 5 to 100 nm, such as about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 nm.

[0237] For example, the epitaxial growth of the epitaxial stack can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the sacrificial layer 201 and the channel layer 202 may comprise materials different from those of the substrate 100. As described above, in at least some examples, the sacrificial layer 201 may comprise an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 202 may comprise an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either the sacrificial layer 201 or the channel layer 202 may comprise other materials, such as germanium, tin, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as SiGe, GeSn, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, III-V, or combinations thereof. As previously stated, the materials of the sacrificial layer 201 and the channel layer 202 may be selected to provide different oxidation and / or etch selectivity characteristics.

[0238] Subsequently, the epitaxial stack, including the channel layer 202 and the sacrificial layer 201, can be patterned such that the channel layer 202 and the sacrificial layer 201, or portions thereof, can be formed as shown in the image. Figure 28B The nanostructure shown is illustrated. Specifically, channel layer 202 can form the nanostructure channel of a nanostructured transistor. The term "nanostructure" as used herein refers to any portion of material having a nanoscale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of this portion. Therefore, the term refers both to elongated material portions with circular and near-circular cross-sections, and to beam or strip-shaped material portions, such as cylindrical or near-rectangular cross-sections. For example, a nanostructure is a nanosheet, nanowire, nanoplate, or nanoring based on its geometry. The patterned channel layer 202 and sacrificial layer 201 can be fabricated using appropriate processes, including dual-patterning or multi-patterning processes.

[0239] See Figure 29 A dummy gate layer 204 and a hard mask layer 205 are formed on the epitaxial stack. The portion of the channel layer 202 below the dummy gate layer 204 can be referred to as the channel region. The dummy gate layer 204 can also define the source / drain region 208 (see...). Figure 35 The dummy gate formation operation forms a dummy gate layer 204 and a hard mask layer 205 on the dummy gate layer 204. The hard mask layer 205 is then patterned, and the patterned hard mask layer 205 is used as an etching mask to pattern the dummy gate layer 204. The etching process may include wet etching, dry etching, and / or combinations thereof.

[0240] In some embodiments, the dummy gate layer 204 may include polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, or metals. In some embodiments, the dummy gate layer 204 may include a metal-containing material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum (Al), and combinations thereof or multilayer structures. The hard mask layer 205 may be made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbide oxycarbide (SiOC), or similar materials, and may have a single-layer structure or a multilayer structure containing multiple dielectric layers. In some embodiments, the dummy gate layer 204 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering deposition, or other techniques suitable for depositing conductive materials. In some embodiments, the hard mask layer 205 may be deposited by CVD, PVD, sputtering deposition, or other techniques suitable for depositing conductive materials. In some implementations, the dummy gate layer 204 may be interchangeably referred to as a dummy gate, dummy gate pattern, dummy gate strip, isolation structure, or dielectric gate.

[0241] See Figure 30 The dummy gate layer 204 is laterally or horizontally recessed using a suitable etching technique to form a lateral groove R21 between the sacrificial layer 201 and the hard mask layer 205. This operation can be performed using a selective etching process. For example, but not limited to, the sacrificial layer 201 can be made of silicon germanium (SiGe), the hard mask layer 205 can be made of a dielectric material, and the dummy gate layer 204 can be made of silicon to allow selective etching of the dummy gate layer 204. In some embodiments, selective dry etching etches silicon at a faster rate than etching silicon germanium (SiGe) and the dielectric material. Therefore, the sacrificial layer 201 and the hard mask layer 205 extend laterally beyond the opposite end faces of the dummy gate layer 204.

[0242] See Figure 31 After the dummy gate layer 204 is recessed, a spacer material 206' is deposited on the intermediate line layer 121. The spacer material 206' may be a conformal layer located on the uppermost sacrificial layer 201, the dummy gate layer 204, and the hard mask layer 205. The spacer material 206' may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide oxide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material 206' comprises multiple layers, such as a second spacer layer formed on a first spacer layer. For example, the spacer material 206' can be formed by depositing a dielectric material on the uppermost sacrificial layer 201, the dummy gate layer 204, and the hard mask layer 205 using a suitable deposition process.

[0243] See Figure 32 The deposited spacer material 206' is then anisotropically etched to expose the uppermost sacrificial layer 201 and the hard mask layer 205. This anisotropic etching process completely removes portions of the spacer material 206' located directly on the hard mask layer 205 and the uppermost sacrificial layer 201 not covered by the hard mask layer 205. Portions of the spacer material 206' on the sidewall of the dummy gate layer 204 recess can remain in the lateral recess R21, forming the gate sidewall spacer layer 206, i.e., the gate spacer layer 206. In some embodiments, the lateral dimension (or thickness) of the sidewall spacer layer 206 can be in the range of about 1 to 25 nanometers, such as about 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, or 25 nanometers.

[0244] See Figure 33Using, for example, anisotropic etching, the exposed portions of the patterned channel layer 202 and the patterned sacrificial layer 201 extending beyond the gate spacer layer 206 are etched to form recesses R22 in the channel layer 202 and the sacrificial layer 201. After anisotropic etching, the end faces of the patterned channel layer 202 and the patterned sacrificial layer 201 are substantially flush with the outermost wall of the gate spacer layer 206 due to the anisotropic etching. In some embodiments, anisotropic etching can be performed by dry chemical etching using a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, or a similar device, and the reactive gas can be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), a chlorine-based gas (such as Cl2), a hydrobromide gas (HBr), oxygen (O2), the like, or combinations thereof.

[0245] See Figure 34 By using a suitable etching technique, the patterned sacrificial layer 201 is recessed laterally or horizontally to form a lateral groove R23. This operation can be performed using a selective etching process. For example, but not limited to, the sacrificial layer 201 can be made of silicon germanium (SiGe), and the channel layer 202 can be made of silicon to allow selective etching of the sacrificial layer 201. In some embodiments, selective dry etching etches silicon germanium (SiGe) at a faster rate than etching silicon. Therefore, the patterned channel layer 202 extends laterally beyond the opposite end face of the patterned sacrificial layer 201.

[0246] Subsequently, the internal spacer layers 207 are filled in the grooves R23. For example, a spacer material layer is formed to fill the grooves R23 left by the lateral etch sacrificial layer 201. The spacer material layer can be a low-k dielectric material, such as SiO2, SiN, SiC, SiON, SiCN, or SiOCN, and can be formed by a suitable deposition method, such as atomic layer deposition (ALD). In some embodiments, the spacer material layer is intrinsic or undoped. The spacer material layer can be formed using CVD (including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD)), PVD, ALD, or other suitable processes. After depositing the spacer material layer, an anisotropic etching process can be performed to trim the deposited spacer material layer, so that the portion of the deposited spacer material layer filling the grooves R23 left by the lateral etch sacrificial layer 201 is retained. After the trimming process, the retained portion of the deposited spacer material in the grooves R23 is referred to as the internal spacer layer 207. The internal spacer layer 207 is used to isolate the metal gate from the source / drain regions formed in subsequent processing.

[0247] See Figure 35Source / drain regions 208 are formed in recess R22 and connected to channel layer 202. Source / drain regions 208 can be formed by performing an epitaxial growth process, which provides epitaxial material on intermediate line layer 121. In the epitaxial growth process, a dummy gate layer 204, a gate spacer layer 206, and an internal spacer layer 207 confine the source / drain regions 208 to intermediate line layer 121 and channel layer 202. In some embodiments, the lattice constant of the source / drain regions 208 differs from the lattice constant of the channel layer 202, thus the channel layer 202 can be strained or stressed by the source / drain regions 208 to improve carrier mobility and enhance device performance. Epitaxial processes include CVD deposition techniques (such as PECVD, vapor phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the composition of channel layer 202.

[0248] In some embodiments, the source / drain region 208 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain region 208 may be in-situ doped during the epitaxial process by introducing dopants, including p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain region 208 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain region 208. In some embodiments, the source / drain region 208 may be an n-type transistor and contain SiP.

[0249] See Figure 36Source / drain contacts 209 may be formed on source / drain regions 208. In some embodiments, source / drain contacts 209 may include, but are not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, carbon tantalum nitride, titanium aluminum, aluminum titanium nitride, other suitable materials, or combinations thereof. In some embodiments, the formation of source / drain contacts 209 may be performed, for example, by a stripping process. For example, but not limited to, a mask layer (not shown) may be formed by depositing a photoresist layer on intermediate circuit layer 121 using a suitable process, such as spin coating, which may include baking the photoresist layer after coating. In some embodiments, the mask layer may include a photoresist material, including positive or negative photoresist materials. The mask layer may be patterned to form openings exposing the source / drain contacts 209. Subsequently, contact material can be deposited on the intermediate circuit layer 121 and formed on the source / drain contacts 209 and the patterned mask layer. The substrate 100 can then be immersed in a container of a suitable solvent that reacts with the patterned mask layer. The patterned mask layer may expand, dissolve, and peel off the contact material formed on the patterned mask layer, while the contact material on the source / drain regions 208 remains partially retained to form the source / drain contacts 209.

[0250] See Figure 37 An interlayer dielectric layer 210 is formed on the intermediate circuit layer 121. In some embodiments, the interlayer dielectric layer 210 comprises materials such as oxides formed from tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 210 can be deposited by plasma-enhanced chemical vapor deposition (PECVD) or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 210, the substrate 100 may undergo a high-temperature annealing process to anneal the interlayer dielectric layer 210. Subsequently, a planarization process (e.g., CMP) is performed to remove excessive layers of the interlayer dielectric layer 210 above the hard mask layer 205 until the hard mask layer 205 is exposed. In some embodiments, the hard mask layer 205 may also act as an etch stop layer for the interlayer dielectric layer 210.

[0251] See Figure 38A hard masking layer 217 may be formed on the interlayer dielectric layer 210 and the hard masking layer 205. In some embodiments, the hard masking layer 217 may be made of the same material as the interlayer dielectric layer 210, thus forming a substantially indistinguishable interface between the hard masking layer 217 and the interlayer dielectric layer 210. In some embodiments, the hard masking layer 217 may be made of a different material than the interlayer dielectric layer 210. In some embodiments, the hard masking layer 217 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide oxycarbide (SiOC), tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, other suitable materials, or combinations thereof. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicon glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. In some embodiments, the hard mask layer 217 can be formed using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. Subsequently, the hard mask layer 217 is patterned and then used to etch the dummy gate layer 204 (see...). Figure 37 The hard mask layer 205 and the interlayer dielectric layer 210 are included. The hard mask layer 217 can be patterned by photolithography processes including photoresist (or photoresist) coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes and / or combinations thereof. Etching processes include dry etching, wet etching and / or other etching methods (e.g., reactive ion etching).

[0252] After forming the patterned hard mask layer 217, the dummy gate layer 204 can be etched through the patterned hard mask layer 217 (see...). Figure 37 A hard mask layer 205 and an interlayer dielectric layer 210 are formed to create an opening O21. The opening O21 exposes one side of the epitaxial stack, allowing the channel layer 202 and the sacrificial layer 201 to be exposed. The etching process may include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). In some embodiments, the opening O21 may have a rectangular outline extending along the Y direction from a top view. After forming the opening O21, the patterned mask can be removed using appropriate techniques, such as wet cleaning, ablation, or similar processes.

[0253] Subsequently, the sacrificial layer 201 is removed by one or more etching processes to form a recess R24, which may inherit the underlying shape of the sacrificial layer 201. The recess R24 may expose the bottom surface of the channel layer 202, while the opening O21 may expose the top surface of the channel layer 202. In some embodiments, the sacrificial layer 201 may be removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial layer 201 at a faster rate than the channel layer 202.

[0254] See Figure 39 Interface layer 211 and high-dielectric-constant dielectric layer 213 may be conformally formed on hard mask layer 217 and in opening O21 and groove R24. In some embodiments, interface layer 211 may include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some embodiments, interface layer 211 may be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. In some embodiments, the high dielectric constant dielectric layer 213 may include a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxides of nitride (SiON), and combinations thereof. In some implementations, the high dielectric constant dielectric layer 213 can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, or combinations thereof.

[0255] Subsequently, gate electrode layer 215 may be deposited on high dielectric constant dielectric layer 213. Gate electrode layer 215 may include a work function metal layer and / or fill metal formed around the work function metal layer. The work function metal layer and / or fill metal may include metal, metal alloy, or metal silicide. For n-type fin field-effect transistors, the work function metal layer may include one or more n-type work function metals (N metals). n-type work function metals may include, but are not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and other suitable materials. On the other hand, for p-type fin field-effect transistors, the work function metal layer may include one or more p-type work function metals (P metals). p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and other suitable materials. In some embodiments, the filler metal may include, but is not limited to, tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, tantalum carbon nitride, titanium aluminum, titanium aluminum nitride, or other suitable materials.

[0256] See Figure 40A and Figure 40B A planarization process (e.g., CMP) is performed to remove excess portions of the hard masking layers 205 and 217 above the gate electrode layer 215, the high-k dielectric layer 213, the interface layer 211, and the gate spacer layer 206. The gate spacer layer 206 can also serve as an etch stop layer for the gate electrode layer 215, the high-k dielectric layer 213, the interface layer 211, and the hard masking layers 205 and 217. Therefore, the metal gate structure G2, including the gate electrode layer 215, the high-k dielectric layer 213, and the interface layer 211, can be formed in the recess R24 to surround the channel layer 202 suspended in the recess R24. In some embodiments, the gate structure G2 can be the final gate of a gate-to-ring field-effect transistor. Therefore, the semiconductor structure can include a transistor PD. R and PD L Transistor PD R Located in transistor PU R Above, transistor PD L Located in transistor PU L Above. Transistor PD R and transistor PD LEach may include a channel layer 202, a gate structure G2 surrounding the channel layer 202, and source / drain regions 208 located on opposite sides of the gate structure G2 and connected to the channel layer 202. In some embodiments, the transistor PD R and transistor PD L They can be interchangeably referred to as intermediate layer transistors.

[0257] See Figure 41A and Figure 41B The middle-end-of-line (MEOL) layer 221 can be formed on the transistor PD. R and transistor PD L The upper section, the middle circuit layer 221, may include a dielectric metal material and conductive interconnects to connect the transistor PD. R and transistor PD L Connected to upper-layer features (e.g., transistor PG) R1 Transistor PG L1 Transistor PG R2 Transistor PG L2 In some embodiments, the dielectric material may include, for example, an oxide formed from tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, conductive interconnects formed in the dielectric material may include contacts 303a and 303b. Contact 303a may be formed in a transistor PD. L On the second source / drain region 208, transistor PG is connected. L1 and transistor PG L2 Shared upper source / drain region 308 (see) Figure 3A Contact 303b can be formed on transistor PD. R On the second source / drain region 208, transistor PG is connected. R1 and PG R2 Shared upper source / drain region 308 (see) Figure 3A In some embodiments, the conductive interconnects may be made of tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, carbon tantalum nitride, titanium aluminum, aluminum titanium nitride, or other suitable materials.

[0258] See Figure 42A and Figure 42BAn epitaxial layer is deposited on the middle circuit layer 221. The epitaxial layer stack includes a sacrificial layer 301 of a first composition and a channel layer 302 of a second composition. The first and second compositions can be different. In some embodiments, the sacrificial layer 301 may be made of silicon germanium (SiGe) with a germanium atomic concentration different from that of the channel layer 302. In some embodiments, the channel layer 301 may be made of silicon (Si). In some embodiments, the germanium atomic concentration of the sacrificial layer 301 is higher than that of the channel layer 302. For example, but not limited to, the germanium atomic concentration of the sacrificial layer 301 may be in the range of about 10% to 90%, such as about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%. However, other embodiments are also possible, including those that provide different etch selectivity between the first and second compositions.

[0259] The following section further discusses using channel layer 302 to define component channels. It is important to note that each layer of channel layer 302 is defined according to... Figure 42B The arrangement shown is for illustrative purposes only and is not intended to exceed the specific description in the patent claim. It is understood that any number of sacrificial layers can be formed in the epitaxial stack; the number of layers depends on the desired number of transistor channel regions. In some embodiments, the number of channel layers 302 can be between about 1 and 100, for example, 1, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, or 101. As described in more detail below, the channel layer 302 can serve as a channel region for a subsequently formed semiconductor device, and its thickness is selected based on device performance considerations. For example, but not limited to, the thickness of the channel layer 302 can be in the range of about 0.5 to 50 nm, for example, about 0.5, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50 nm. In some embodiments, the length of the channel layer 302 can be in the range of 5 to 500 nm, for example, about 5, 50, 100, 150, 200, 250, 300, 350, 400, 450, or 500 nm. In some embodiments, the channel layer 302 can have a square / rectangular / diamond cross-sectional profile taken along the longitudinal direction of the gate structure. The sacrificial layer 301 in the channel region can eventually be removed to define the vertical distance between adjacent channel regions of the subsequently formed multi-gate element, and its thickness is selected based on device performance considerations. In some embodiments, the thickness of the sacrificial layer 301 can be in the range of about 5 to 100 nm, for example, about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 nm.

[0260] For example, the epitaxial growth of the epitaxial stack can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the sacrificial layer 301 and the channel layer 302 may comprise materials different from the substrate 100. As described above, in at least some instances, the sacrificial layer 301 may comprise an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 302 may comprise an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either the sacrificial layer 301 or the channel layer 302 may comprise other materials such as germanium, tin, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as SiGe, GeSn, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, III-V, or combinations thereof. As described above, the materials of the sacrificial layer 301 and the channel layer 302 may be selected to provide different oxidation and / or etch selectivity characteristics.

[0261] Subsequently, the epitaxial stack comprising channel layer 302 and sacrificial layer 301 can be patterned such that channel layer 302 and sacrificial layer 301, or portions thereof, can be formed as shown in the image. Figure 42B The nanostructure shown is illustrated. Specifically, channel layer 302 can form the nanostructure channel of a nanostructured transistor. As used herein, the term "nanostructure" refers to any portion of material having nanoscale or even microscale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers both to elongated material portions having circular or substantially circular cross-sections and to material portions having columnar shapes or substantially rectangular cross-sections. For example, a nanostructure is a nanosheet, nanowire, nanoplate, or nanoring according to its geometry. The patterned channel layer 302 and sacrificial layer 301 can be fabricated using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller spacing than that achievable with a single direct photolithography process. For example, in some embodiments, a sacrificial layer can be formed on the intermediate line layer 221 and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed. Etching processes can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0262] See Figure 43A dummy gate layer 304 and a hard mask layer 305 are formed on an epitaxial stack. A portion of the channel layer 302 beneath the dummy gate layer 304 may be referred to as a channel region. The dummy gate formation operation forms the hard mask layer 305 on the dummy gate layer 304. The hard mask layer 305 is then patterned, and the patterned hard mask layer 305 is then used as an etching mask to pattern the dummy gate layer 304. The etching process may include wet etching, dry etching, and / or combinations thereof.

[0263] In some embodiments, the dummy gate layer 304 may include polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, or metal. In some embodiments, the dummy gate layer 304 may include a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or a multilayer structure. The hard mask layer 305 may be made of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbide (SiOC), or similar materials, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. In some embodiments, the dummy gate layer 304 may be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other techniques suitable for depositing conductive materials. In some embodiments, the hard mask layer 305 may be deposited by CVD, PVD, sputtering deposition, or other techniques suitable for depositing conductive materials. In some implementations, the dummy gate layer 305 may be interchangeably referred to as a dummy gate, dummy gate pattern, dummy gate strip, isolation structure, or dielectric gate.

[0264] See Figure 44 A lateral groove R31 is vertically created between the sacrificial layer 301 and the hard mask layer 305 by using a suitable etching technique to laterally or horizontally recess the dummy gate layer 304. This operation can be performed using a selective etching process. For example, but not limited to, the sacrificial layer 301 can be made of silicon germanium (SiGe), the hard mask layer 305 can be made of a dielectric material, and the dummy gate layer 304 can be made of silicon, allowing selective etching of the dummy gate layer 304. In some embodiments, selective dry etching etches Si at a faster rate than etching silicon germanium (SiGe) and the dielectric material. Therefore, the sacrificial layer 301 and the hard mask layer 305 extend laterally across the opposite end faces of the dummy gate layer 304.

[0265] See Figure 45After the dummy gate layer 304 is recessed, a spacer material 306' is deposited on the intermediate line layer 221. The spacer material 306' may be a conformal layer located on the top sacrificial layer 301, the dummy gate layer 304, and the hard mask layer 305. The spacer material 306' may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide oxide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material 306' includes a multilayer structure, such as a second spacer layer formed on the first spacer layer. For example, the spacer material 306' can be formed by depositing a dielectric material on the top sacrificial layer 301, the dummy gate layer 304, and the hard mask layer 305 using a suitable deposition process.

[0266] See Figure 46 The deposited spacer material 306' is then subjected to an anisotropic etching process to expose the top sacrificial layer 301 and the hard mask layer 305. This anisotropic etching process completely removes the spacer material 306' directly on the hard mask layer 305 and the top sacrificial layer 301. A portion of the spacer material 306' on the sidewalls of the recessed dummy gate layer 304 can remain in the lateral groove R31, forming a gate sidewall spacer 306, referred to as the gate spacer 306. In some embodiments, the lateral dimension (or thickness) of the sidewall spacer 306 can be in the range of about 1 to 25 nm, for example, about 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, or 25 nm.

[0267] See Figure 47 By using, for example, anisotropic etching, the exposed portions of the patterned channel layer 302 and the patterned sacrificial layer 301 extending beyond the gate spacer 306 are etched, thereby forming a recess R32 in the channel layer 302 and the sacrificial layer 301. After anisotropic etching, the end faces of the patterned channel layer 302 and the patterned sacrificial layer 301 and their respective outer walls of the gate spacer 306 are substantially coplanar due to the anisotropic etching. In some embodiments, anisotropic etching can be performed using dry chemical etching with a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, or a similar device, and the reactive gas can be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), a chlorine-based gas (such as Cl2), a bromine hydrogen gas (HBr), oxygen (O2), the like, or combinations thereof.

[0268] See Figure 48Lateral recesses R33 are created by patterning the sacrificial layer 301 laterally or horizontally using appropriate etching techniques. This operation can be performed using a selective etching process. For example, but not limited to, the sacrificial layer 301 can be made of silicon germanium (SiGe), and the channel layer 302 can be made of silicon, allowing selective etching of the sacrificial layer 301. In some embodiments, selective dry etching etches silicon germanium (SiGe) at a faster rate than etching Si. Therefore, the patterned channel layer 302 extends laterally beyond the opposite end face of the patterned sacrificial layer 301.

[0269] Subsequently, inner spacers 307 are filled into the respective recesses R33. For example, the spacer material layer fills the recesses R33 left after the lateral etch sacrificial layer 301 described above. The spacer material layer can be a low-k dielectric material, such as SiO2, SiN, SiC, SiON, SiCN, or SiOCN, and can be formed by a suitable deposition method (such as ALD). In some embodiments, the spacer material layer is undoped. The spacer material layer can be formed using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. After depositing the spacer material layer, an anisotropic etching process can be performed to trim the deposited spacer material layer, such that a portion of the deposited spacer material layer filling the recesses R33 left after the lateral etch sacrificial layer 301 is retained. After the trimming process, the retained portion of the deposited spacer material is referred to as the inner spacer 307 in the recesses R33. The inner spacer 307 serves to isolate the metal gate and source / drain regions formed in subsequent processing.

[0270] See Figure 49 Source / drain regions 308 are formed in recesses R32 and connected to channel layer 302. Source / drain regions 308 can be provided with epitaxial material on intermediate line layer 221 by performing an epitaxial growth process. In the epitaxial growth process, a dummy gate layer 304, gate spacer 306, and inner spacer 307 confine source / drain regions 308 within intermediate line layer 221 and channel layer 302. In some embodiments, the lattice constant of source / drain regions 308 differs from the lattice constant of channel layer 302, allowing channel layer 302 to be strained or stressed by source / drain regions 308 to improve carrier mobility and enhance device performance. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the composition of channel layer 302.

[0271] In some embodiments, the source / drain region 308 may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium phosphide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), silicon phosphide (SiP), or other suitable materials. In the epitaxial process, in-situ doping can be performed by introducing dopants, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain region 308 is not in-situ doped, it is doped by performing an implantation process (i.e., a bonding implantation process). In some embodiments, the source / drain region 308 may be in an n-type transistor and include silicon phosphide (SiP).

[0272] See Figure 50 Source / drain contacts 309 may be formed on source / drain regions 308. In some embodiments, source / drain contacts 309 may include, but are not limited to, tungsten (W), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide, cobalt silicide, silver (Ag), gold (Au), tungsten nitride (WN), ruthenium oxide (RuO), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable materials, or combinations thereof. In some embodiments, the formation of source / drain contacts 309 may be performed, for example, by a stripping process. For example, but not limited to, a mask layer (not shown) can be formed by depositing a photoresist layer on the intermediate circuit layer 221 using appropriate processes, such as spin coating, which may include post-coating baking of the photoresist layer. In some embodiments, the mask layer may include a photoresist material, including positive or negative photoresist materials. The mask layer may be patterned to form openings exposing the source / drain contacts 309. Subsequently, contact material may be deposited on the intermediate circuit layer 221 and formed on the source / drain contacts 309 and the patterned mask layer. Subsequently, the substrate 100 is immersed in a container of a suitable solvent that will react with the patterned mask layer. The patterned mask layer may expand, dissolve, and strip the contact material formed on the patterned mask layer, leaving portions of the contact material on the source / drain regions 308 to form the source / drain contacts 309.

[0273] See Figure 51An interlayer dielectric layer 310 is formed on the intermediate circuit layer 221. In some embodiments, the interlayer dielectric layer 310 comprises, for example, an oxide formed from tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 310 can be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 310, the substrate 100 can undergo a high-temperature budget process to anneal the interlayer dielectric layer 310. Subsequently, a planarization process (e.g., CMP) is performed to remove excess interlayer dielectric layer 310 above the hard mask layer 305 until the hard mask layer 305 is exposed. In some embodiments, the hard mask layer 305 can also be used as an etch stop layer for etching the interlayer dielectric layer 310.

[0274] See Figure 52 A hard masking layer 317 may be formed on the interlayer dielectric layer 310 and the hard masking layer 305. In some embodiments, the hard masking layer 317 may be made of the same material as the interlayer dielectric layer 310, thus forming a substantially indistinguishable interface between the hard masking layer 317 and the interlayer dielectric layer 310. In some embodiments, the hard masking layer 317 may be made of a different material than the interlayer dielectric layer 310. In some embodiments, the hard masking layer 317 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide oxycarbide (SiOC), tetraethoxysilane (TEOS), silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, other suitable materials, or combinations thereof. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicon glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutane (BCB), or polyimide. In some embodiments, the hard mask layer 317 can be formed using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. Subsequently, the hard mask layer 317 can be patterned and then used to etch the dummy gate layer 304 (see...). Figure 51 The hard mask layer 305 and the interlayer dielectric layer 310 are included. The hard mask layer 317 can be patterned by photolithography processes, including photoresist (or resist) coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes, and / or combinations thereof. Etching processes include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching).

[0275] After forming the patterned hard mask layer 317, the dummy gate layer 304 can be etched through the patterned hard mask layer 317 (see...). Figure 51 A hard mask layer 305 and an interlayer dielectric layer 310 are formed to create an opening O31. The opening O31 exposes the sidewalls of the epitaxial stack, allowing the channel layer 302 and the sacrificial layer 301 to be exposed. The etching process may include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). In some embodiments, the opening O31 may have a rectangular outline extending along the Y direction from a top view. After the opening O31 is formed, the patterned mask can be removed using appropriate techniques, such as wet cleaning, ashing, or similar processes.

[0276] Subsequently, the sacrificial layer 301 is removed in one or more etching processes to form a groove R34 that inherits the shape of the lower sacrificial layer 301. The groove R34 can expose the bottom surface of the channel layer 302, and the opening O31 can expose the top surface of the channel layer 302. In some embodiments, the sacrificial layer 301 can be removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial layer 301, with an etching rate faster than that of the channel layer 302.

[0277] See Figure 53An interface layer 311 and a high-dielectric-constant dielectric layer 313 may be conformally formed on the hard mask layer 317 and in the opening O31 and the groove R34. In some embodiments, the interface layer 311 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some embodiments, the interface layer 311 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. In some embodiments, the high dielectric constant dielectric layer 313 may include a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), nitride oxide (SiON), and combinations thereof. In some implementations, the high dielectric constant dielectric layer 313 can be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, or combinations thereof.

[0278] Subsequently, a gate electrode layer 315 can be deposited on the high-dielectric-constant dielectric layer 313. The gate electrode layer 315 may include a work function metal layer and / or a fill metal formed around the work function metal layer. The work function metal layer and / or the fill metal may include metals, metal alloys, or metal silicides. For an n-type fin field-effect transistor, the work function metal layer may include one or more n-type work function metals (N metals). The n-type work function metals may include, but are not limited to, titanium aluminum (TiAl), aluminum titanium nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and other suitable materials. On the other hand, for a p-type fin field-effect transistor, the work function metal layer may include one or more p-type work function metals (P metals). p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and other suitable materials. In some embodiments, the filler metal may include, but is not limited to, tungsten (W), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide, cobalt silicide, silver (Ag), gold (Au), tungsten nitride (WN), ruthenium oxide (RuO), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or other suitable materials.

[0279] See Figure 54A and Figure 54B A planarization process (e.g., CMP) is performed to remove excess portions of the gate electrode layer 315, high-k dielectric layer 313, interface layer 311, and hard mask layers 305 and 317 above the gate spacer 306. The gate spacer 106 can also serve as an etch stop layer for etching the gate electrode layer 315, high-k dielectric layer 313, interface layer 311, and hard mask layers 305 and 317. Therefore, the metal gate structure G3, including the gate electrode layer 315, high-k dielectric layer 313, and interface layer 311, can be formed in the recess R34 to surround the channel layer 302 suspended in the recess R34. In some embodiments, the gate structure G3 may be the final gate of a GAA FET. Therefore, the semiconductor structure may include a transistor PG. R1 PG L1 PG R2 PG L2 Transistor PG L1 Located in transistor PDL Above, transistor PG R2 Located in transistor PD R Above. Transistor PG R1 Transistor PG L1 Transistor PG R2 Transistor PG L2 Each may include a channel layer 302, a gate structure G3 surrounding the channel layer 302, and source / drain regions 308 on both sides of the gate structure G3 and connected to the channel layer 302. In some embodiments, transistor PG R1 Transistor PG L1 Transistor PG R2 Transistor PG L2 They can be interchangeably referred to as top-level transistors.

[0280] See Figure 55A and Figure 55B The interconnect structure 322 can be formed on the transistor PG. R1 Transistor PG L1 Transistor PG R2 Transistor PG L2 Above. In some embodiments, the interconnect structure 322 can be interchangeably referred to as a back-end-of-line (BEOL) structure. The interconnect structure 322 may include an inter-metal dielectric layer 323 and conductive interconnects, including bit lines BL and BLB and a word line WL in the inter-metal dielectric layer 323. In some embodiments, bit lines BL and BLB may be formed in a first metal layer M1 at the same height. In some embodiments, the word line WL may be formed in a second metal layer M2 at a height higher than bit lines BL and BLB. The conductive interconnects of the interconnect structure may also include contacts 403a, 403b, 403c, 403d, 403e, 403f, 403g, and 403h. Contacts 403a and 403b may be formed on transistor PG. L1 and transistor PG L2 On the non-common source / drain region 308, and electrically coupled to the bit line BL above. Contacts 403e and 403f can be formed on transistor PG. R1 and transistor PG R2 On the non-common source / drain region 308, and electrically coupled to the bit line BLB above. Contacts 403c, 403d, 403g, and 403h can be formed on transistor PG. R1 Transistor PG L1 Transistor PG R2 Transistor PGL2 It is placed on the gate structure G3 and electrically coupled to the word line WL above it.

[0281] In some embodiments, the intermetallic dielectric layer 323 may comprise, for example, an oxide formed from tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, bit lines BL and BLB, word lines WL, and contacts 403c, 403d, 403g, and 403h may be made of tungsten, platinum, aluminum, ruthenium, molybdenum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, silver, gold, tungsten nitride, ruthenium oxide, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminum nitride, titanium aluminum nitride, or other suitable materials.

[0282] Therefore, based on the above discussion, it can be seen that this disclosure provides advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor are all embodiments required to provide a specific advantage. Various embodiments of this disclosure provide an improved static random access memory (SRAM) bit cell configuration, focusing on read-enhanced and dual-port versions, both using a three-layer architecture and eight transistors (8T), maintaining the same physical layout (e.g., four-transistor layout) as a standard 6T high-density SRAM bit cell. Read-enhanced SRAM bit cell (see...) Figure 3A Two pairs of switching transistors can be included in the top-level structure to increase the transistor strength of read operations without increasing the area of ​​the bit cell. Dual-port static random access memory bit cell (see...) Figure 3B It can contain two pairs of switching transistors, each controlled by a separate word line, allowing independent access to memory cells and supporting operations such as simultaneous read / write. Furthermore, the read-enhanced / dual-port static random access memory (SRAM) bit cell can have the same transistor configuration as the 6T SRAM bit cell, using pull-down and pull-up transistors.

[0283] In some embodiments, the method of manufacturing a semiconductor structure includes forming a first bottom-layer pull-up transistor and a second bottom-layer pull-up transistor on a substrate, wherein the first bottom-layer pull-up transistor and the second bottom-layer pull-up transistor are included in a memory cell; forming a first middle-layer pull-down transistor and a second middle-layer pull-down transistor above the first bottom-layer pull-up transistor and the second bottom-layer pull-up transistor, wherein the first middle-layer pull-down transistor and the second middle-layer pull-down transistor are included in the memory cell; and forming a first top-layer switching transistor, a second top-layer switching transistor, a third top-layer switching transistor, and a fourth top-layer switching transistor above the first middle-layer pull-down transistor and the second middle-layer pull-down transistor, wherein the first top-layer switching transistor, the second top-layer switching transistor, the third top-layer switching transistor, and the fourth top-layer switching transistor are included in the memory cell. In some embodiments, the projection area of ​​the memory cell on the substrate includes up to four transistors located at the same level. In some embodiments, the projection area of ​​the first middle-layer pull-down transistor on the substrate overlaps with the projection area of ​​the first bottom-layer pull-up transistor on the substrate, and the projection area of ​​the second middle-layer pull-down transistor on the substrate overlaps with the projection area of ​​the second bottom-layer pull-up transistor on the substrate. In some embodiments, the projection area of ​​the first top-layer switching transistor on the substrate overlaps with the projection area of ​​the first middle-layer pull-down transistor on the substrate, and the projection area of ​​the fourth top-layer switching transistor on the substrate overlaps with the projection area of ​​the second middle-layer pull-down transistor on the substrate. In some embodiments, the method of manufacturing the semiconductor structure further includes forming word lines above the first, second, third, and fourth top-layer switching transistors, wherein multiple gates of the first, second, third, and fourth top-layer switching transistors are electrically coupled to the word lines. In some embodiments, the method of manufacturing the semiconductor structure further includes forming bit lines and bit lines above the word lines, wherein multiple source / drain nodes of the first and second top-layer switching transistors are electrically coupled to the bit lines, and multiple source / drain nodes of the third and fourth top-layer switching transistors are electrically coupled to the bit lines. In some embodiments, the method of manufacturing a semiconductor structure further includes forming a first word line and a second word line above a first top-level switching transistor, a second top-level switching transistor, a third top-level switching transistor, and a fourth top-level switching transistor, wherein a plurality of gates of the first top-level switching transistor and the second top-level switching transistor are electrically coupled to the first word line, and a plurality of gates of the third top-level switching transistor and the fourth top-level switching transistor are electrically coupled to the second word line.In some embodiments, the method of manufacturing a semiconductor structure further includes: forming a first bit line, a second bit line, a first bit line, and a second bit line above the first word line and the second word line, wherein a source / drain node of a first top-level switching transistor is electrically coupled to the first bit line, a source / drain node of a second top-level switching transistor is electrically coupled to the first bit line, a source / drain node of a third top-level switching transistor is electrically coupled to the second bit line, and a source / drain node of a fourth top-level switching transistor is electrically coupled to the second bit line. In some embodiments, the method of manufacturing a semiconductor structure further includes: forming a back-side voltage source line on a substrate before forming a first bottom-level pull-up transistor and a second bottom-level pull-up transistor, wherein a source / drain node of the first bottom-level pull-up transistor and a source / drain node of the second bottom-level pull-up transistor are electrically coupled to the back-side voltage source line. In some embodiments, the method of manufacturing a semiconductor structure further includes: forming a first back-side ground line and a second back-side ground line on a substrate before forming a first bottom-layer pull-up transistor and a second bottom-layer pull-up transistor, wherein a source / drain electrical node of the first middle-layer pull-down transistor is coupled to the first back-side ground line, and a source / drain node of the second middle-layer pull-down transistor is electrically coupled to the second back-side ground line.

[0284] In some embodiments, a method of manufacturing a semiconductor structure includes forming a first semiconductor nanostructure at a first height above a substrate, wherein the first semiconductor nanostructure is included in a static random access memory (SRAM) cell; forming a plurality of first epitaxial structures on opposite sides of the first semiconductor nanostructure; forming a first gate structure surrounding the first semiconductor nanostructure; forming a second, third, fourth, and fifth semiconductor nanostructure at a second height on the substrate, wherein the second, third, fourth, and fifth semiconductor nanostructures are included in the SRAM cell; forming a plurality of second epitaxial structures on opposite sides of the second semiconductor nanostructure, a plurality of third epitaxial structures on opposite sides of the third semiconductor nanostructure, a plurality of fourth epitaxial structures on opposite sides of the fourth semiconductor nanostructure, and a plurality of fifth epitaxial structures on opposite sides of the fifth semiconductor nanostructure; and forming a second gate structure surrounding the second semiconductor nanostructure, a third gate structure surrounding the third semiconductor nanostructure, a fourth gate structure surrounding the fourth semiconductor nanostructure, and a fifth gate structure surrounding the fifth semiconductor nanostructure. In some embodiments, the second height is higher than the first height. In some embodiments, a first semiconductor nanostructure, a plurality of first epitaxial structures, and a first gate structure collectively form a pull-up transistor or a pull-down transistor for a static random access memory (SRAM) cell. In some embodiments, a second semiconductor nanostructure, a plurality of second epitaxial structures, and a second gate structure form a first switching transistor; a third semiconductor nanostructure, a plurality of third epitaxial structures, and a third gate structure form a second switching transistor; a fourth semiconductor nanostructure, a plurality of fourth epitaxial structures, and a fourth gate structure form a third switching transistor; and a fifth semiconductor nanostructure, a plurality of fifth epitaxial structures, and a fifth gate structure form a fourth switching transistor. In some embodiments, a sixth semiconductor nanostructure is formed at a third height on a substrate, wherein the sixth semiconductor nanostructure is included in the SRAM cell; a plurality of sixth epitaxial structures are formed on opposite sides of the sixth semiconductor nanostructure; and a sixth gate structure is formed surrounding the sixth semiconductor nanostructure.

[0285] In some embodiments, the semiconductor structure includes a plurality of back-side power lines and memory cells. The plurality of back-side power lines are located on a semiconductor substrate. The memory cells are located above the plurality of back-side power lines. The memory cells include a first pull-up transistor and a second pull-up transistor at a first height, a first pull-down transistor and a second pull-down transistor at a second height different from the first height, and a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor at a third height different from the first and second heights. In some embodiments, the semiconductor structure further includes word lines. The word lines are located at a fourth height above the semiconductor substrate. A plurality of gates of the first, second, third, and fourth switching transistors are electrically coupled to the word lines. In some embodiments, the semiconductor structure further includes bit lines and bit lines. The bit lines are located at a fifth height above the semiconductor substrate. The bit lines are located at a fifth height above the semiconductor substrate, wherein a plurality of source / drain nodes of the first and second switching transistors are electrically coupled to the bit lines, while a plurality of source / drain nodes of the third and fourth switching transistors are electrically coupled to the bit lines. In some embodiments, the semiconductor structure further includes a first word line and a second word line. The first word line is located at a fourth height above the semiconductor substrate. The second word line is located at a fourth height above the semiconductor substrate. Multiple gates of a first switching transistor and a second switching transistor are electrically coupled to the first word line, while multiple gates of a third switching transistor and a fourth switching transistor are electrically coupled to the second word line. In some embodiments, the semiconductor structure further includes a first bit line and a second bit line. The first bit line is located at a fifth height above the semiconductor substrate. The second bit line is located at a fifth height above the semiconductor substrate. A source / drain node of the first switching transistor is electrically coupled to the first bit line, while a source / drain node of the third switching transistor is electrically coupled to the second bit line.

[0286] In some embodiments, the semiconductor structure includes a substrate, a first bottom-layer pull-up transistor, a second bottom-layer pull-up transistor, a first middle-layer pull-down transistor, a second middle-layer pull-down transistor, a first top-layer switching transistor, a second top-layer switching transistor, a third top-layer switching transistor, and a fourth top-layer switching transistor. The first and second bottom-layer pull-up transistors are located above the substrate, and are included within a memory cell. The first and second middle-layer pull-down transistors are located above the first and second bottom-layer pull-up transistors, and are included within a memory cell. The first, second, third, and fourth top-layer switching transistors are located above the first and second middle-layer pull-down transistors, and are included within a memory cell.

[0287] In some embodiments, the semiconductor structure further includes word lines. The word lines are located above a first top-level switching transistor, a second top-level switching transistor, a third top-level switching transistor, and a fourth top-level switching transistor, wherein multiple gates of the first top-level switching transistor, the second top-level switching transistor, the third top-level switching transistor, and the fourth top-level switching transistor are electrically coupled to the word lines.

[0288] In some embodiments, the semiconductor structure includes a substrate, a first semiconductor nanostructure, a plurality of first epitaxial structures, a first gate structure, a second semiconductor nanostructure, a third semiconductor nanostructure, a fourth semiconductor nanostructure, a fifth semiconductor nanostructure, a plurality of second epitaxial structures, a plurality of third epitaxial structures, a plurality of fourth epitaxial structures, a plurality of fifth epitaxial structures, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure. The first semiconductor nanostructure is located at a first height above the substrate, wherein the first semiconductor nanostructure is included in a static random access memory (SRAM) cell. The plurality of first epitaxial structures are located on opposite sides of the first semiconductor nanostructure. The first gate structure surrounds the first semiconductor nanostructure. The second, third, fourth, and fifth semiconductor nanostructures are located at a second height above the substrate, wherein the second, third, fourth, and fifth semiconductor nanostructures are included in the SRAM cell. The plurality of second epitaxial structures are located on opposite sides of the second semiconductor nanostructure. The plurality of third epitaxial structures are located on opposite sides of the third semiconductor nanostructure. The plurality of fourth epitaxial structures are located on opposite sides of the fourth semiconductor nanostructure. Multiple fifth epitaxial structures are located on opposite sides of the fifth semiconductor nanostructure. A second gate structure surrounds the second semiconductor nanostructure. A third gate structure surrounds the third semiconductor nanostructure. A fourth gate structure surrounds the fourth semiconductor nanostructure. A fifth gate structure surrounds the fifth semiconductor nanostructure.

[0289] In some embodiments, a first semiconductor nanostructure, a plurality of first epitaxial structures, and a first gate structure together form a pull-up transistor or a pull-down transistor of a static random access memory cell.

[0290] In some embodiments, a second semiconductor nanostructure, a plurality of second epitaxial structures, and a second gate structure form a first switching transistor; a third semiconductor nanostructure, a plurality of third epitaxial structures, and a third gate structure form a second switching transistor; a fourth semiconductor nanostructure, a plurality of fourth epitaxial structures, and a fourth gate structure form a third switching transistor; and a fifth semiconductor nanostructure, a plurality of fifth epitaxial structures, and a fifth gate structure form a fourth switching transistor.

[0291] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Multiple back-side power lines are located on a semiconductor substrate; as well as A memory cell is located above the plurality of back-side power lines, wherein the memory cell includes a first pull-up transistor and a second pull-up transistor at a first height, a first pull-down transistor and a second pull-down transistor at a second height different from the first height, and a first switching transistor, a second switching transistor, a third switching transistor and a fourth switching transistor at a third height different from the first height and the second height.

2. The semiconductor structure as described in claim 1, characterized in that, Further includes: A word line is located at a fourth height above the semiconductor substrate, wherein the gates of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are electrically coupled to the word line.

3. The semiconductor structure as described in claim 2, characterized in that, Further includes: A single-element line, located at a fifth height above the semiconductor substrate; as well as A bit line is located at the fifth height above the semiconductor substrate, wherein the multiple source / drain nodes of the first switching transistor and the second switching transistor are electrically coupled to the bit line, and the multiple source / drain nodes of the third switching transistor and the fourth switching transistor are electrically coupled to the bit line.

4. The semiconductor structure as described in claim 1, characterized in that, Further includes: A first word line, located at a fourth height above the semiconductor substrate; as well as A second word line is located at the fourth height above the semiconductor substrate, wherein the gates of the first switching transistor and the plurality of gates of the second switching transistor are electrically coupled to the first word line, and the gates of the third switching transistor and the plurality of gates of the fourth switching transistor are electrically coupled to the second word line.

5. The semiconductor structure as described in claim 4, characterized in that, Further includes: A first element line, located at a fifth height above the semiconductor substrate; as well as A second bit line is located at the fifth height above the semiconductor substrate, wherein a source / drain node of the first switching transistor is electrically coupled to the first bit line, and a source / drain node of the third switching transistor is electrically coupled to the second bit line.

6. A semiconductor structure, characterized in that, include: One substrate; A first bottom-layer pull-up transistor and a second bottom-layer pull-up transistor are located above the substrate, wherein the first bottom-layer pull-up transistor and the second bottom-layer pull-up transistor are included in a memory cell; A first middle-layer pull-down transistor and a second middle-layer pull-down transistor are located above the first bottom-layer pull-up transistor and the second bottom-layer pull-up transistor, wherein the first middle-layer pull-down transistor and the second middle-layer pull-down transistor are included in the memory cell; and A first top-level switching transistor, a second top-level switching transistor, a third top-level switching transistor, and a fourth top-level switching transistor are located above the first middle-level pull-down transistor and the second middle-level pull-down transistor, wherein the first top-level switching transistor, the second top-level switching transistor, the third top-level switching transistor, and the fourth top-level switching transistor are included in the memory cell.

7. The semiconductor structure as described in claim 6, characterized in that, Further includes: A word line is located above the first top-level switching transistor, the second top-level switching transistor, the third top-level switching transistor, and the fourth top-level switching transistor, wherein multiple gates of the first top-level switching transistor, the second top-level switching transistor, the third top-level switching transistor, and the fourth top-level switching transistor are electrically coupled to the word line.

8. A semiconductor structure, characterized in that, include: One substrate; A first semiconductor nanostructure is located at a first height above the substrate, wherein the first semiconductor nanostructure is contained in a static random access memory cell; Multiple first epitaxial structures are located on opposite sides of the first semiconductor nanostructure; A first gate structure surrounds the first semiconductor nanostructure; A second semiconductor nanostructure, a third semiconductor nanostructure, a fourth semiconductor nanostructure, and a fifth semiconductor nanostructure are located at a second height above the substrate, wherein the second semiconductor nanostructure, the third semiconductor nanostructure, the fourth semiconductor nanostructure, and the fifth semiconductor nanostructure are included in the static random access memory cell. Multiple second epitaxial structures are located on opposite sides of the second semiconductor nanostructure; Multiple third epitaxial structures are located on opposite sides of the third semiconductor nanostructure; Multiple fourth epitaxial structures are located on opposite sides of the fourth semiconductor nanostructure; Multiple fifth epitaxial structures are located on opposite sides of the fifth semiconductor nanostructure; A second gate structure surrounds the second semiconductor nanostructure; A third gate structure surrounds the third semiconductor nanostructure; A fourth gate structure surrounds the fourth semiconductor nanostructure; as well as A fifth gate structure surrounds the fifth semiconductor nanostructure.

9. The semiconductor structure as described in claim 8, characterized in that, The first semiconductor nanostructure, the plurality of first epitaxial structures, and the first gate structure together form a pull-up transistor or a pull-down transistor of the static random access memory unit.

10. The semiconductor structure as described in claim 8, characterized in that, The second semiconductor nanostructure, the plurality of second epitaxial structures, and the second gate structure form a first switching transistor; the third semiconductor nanostructure, the plurality of third epitaxial structures, and the third gate structure form a second switching transistor; the fourth semiconductor nanostructure, the plurality of fourth epitaxial structures, and the fourth gate structure form a third switching transistor; and the fifth semiconductor nanostructure, the plurality of fifth epitaxial structures, and the fifth gate structure form a fourth switching transistor.

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