2T1FC ferroelectric memory cell and memory array
By using a 2T1FC ferroelectric memory cell structure with dedicated memory gate lines and a separate gate structure, the problems of durability and charge retention in ferroelectric memories during high-frequency operation are solved, achieving high reliability and low power consumption storage operation, which is suitable for edge AI devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI SHENMING AOSI SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-07-31
- Publication Date
- 2026-04-24
AI Technical Summary
Existing ferroelectric memories suffer from decreased durability and insufficient charge retention during high-frequency operation, and are susceptible to read/write interference, making it difficult to meet the requirements of non-volatility and in-memory computing.
It adopts a 2T1FC ferroelectric memory cell structure, uses a dedicated memory gate line to prevent spontaneous charge dissipation after writing, enhances data retention capability by separating the memory path and control path and setting an isolated gate structure, and realizes multi-level state control through ferroelectric capacitors.
It improves data retention, reduces accidental flips during read/write cycles, extends device lifespan, supports low-power and high-reliability storage operations, and is suitable for edge AI devices.
Smart Images
Figure CN224165044U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of in-memory computing memory technology, and in particular to a 2T1FC ferroelectric memory cell and memory array. Background Technology
[0002] The evolution of artificial intelligence (AI) and neuromorphic computing has driven the demand for memory systems that not only need to be high-speed and high-density, but also support non-volatile, in-memory computing (CIM). Traditional memory technologies, such as SRAM and DRAM, while fast, suffer from volatility and significant energy consumption. Ferroelectric field-effect transistors (FeFETs) and single-transistor single-capacitor (1T1C) ferroelectric structures have emerged as viable candidates for non-volatile memory.
[0003] However, these architectures often exhibit reduced durability, charge retention issues, and limited resilience to read / write interference during high-frequency operation.
[0004] To achieve superior durability (compared to ferroelectric field-effect transistors (FeFETs)), researchers have proposed a ferroelectric metal field-effect transistor (FeMET) structure for advanced neuromorphic computing / in-memory computing (K. Ni, JASmith, B. Grisafe, T. Rakshit, B. Obradovic, JA Kittl, M. Rodder, and S. Datta, "System-on-a-Chip Logic-Compatible Multi-Bit FeMFET Weighting Cells for Neuromorphic Applications," IEDM 2018-296, pp. 13.2.1-13.2.4). This FeMFET features a floating gate, but the floating gate characteristic of this device can cause leakage current issues during array operation, leading to a decrease in data retention. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a 2T1FC ferroelectric memory cell and memory array that uses a dedicated memory gate line to prevent spontaneous charge dissipation after writing to the 2T1FC ferroelectric memory cell and enhance data retention capability.
[0006] To achieve the above objectives, this application provides a 2T1FC ferroelectric memory cell, comprising:
[0007] A silicon substrate has an active device region on it, on which a storage transistor and a control transistor are formed. The source of the control transistor is connected to the drain of the storage transistor. A storage gate line is formed on the gate stack of the storage transistor, and a ferroelectric capacitor is formed on the storage gate line.
[0008] Furthermore, a first diffusion region, a second diffusion region, and a third diffusion region are formed on the active device region, a gate stack of the control transistor is formed between the first diffusion region and the second diffusion region, and a gate stack of the storage transistor is formed between the second diffusion region and the third diffusion region.
[0009] Furthermore, control lines are formed on the gate stack of the control transistor.
[0010] Furthermore, the first diffusion region forms a bit line through bit line contact.
[0011] Furthermore, the third diffusion region forms an active line through source line contact.
[0012] Furthermore, a storage gate pad is formed on the gate stack of the storage transistor, a storage gate pad is formed above the storage gate pad through a storage gate contact, and the storage gate line is formed on the storage gate pad.
[0013] Furthermore, the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer, and a top electrode; the bottom electrode is connected to the storage gate line through a through-hole pad; and a plate line is formed on the top electrode.
[0014] Furthermore, it also includes a shallow trench isolation region and an oxide located within the shallow trench isolation region; the shallow trench isolation region is arranged around the active device region.
[0015] Furthermore, the gate stack comprises, from bottom to top, a gate oxide layer, a high dielectric constant dielectric layer, and a TiN layer.
[0016] To achieve the above objectives, this application also provides a memory array including the 2T1FC ferroelectric memory cell described above.
[0017] The 2T1FC ferroelectric memory cell provided in this application uses a dedicated memory gate line to prevent spontaneous charge dissipation after writing, thereby enhancing non-volatility.
[0018] The 2T1FC ferroelectric memory cell provided in this application separates the storage path and the control path, reducing accidental flipping during read / write cycles. The set-and-isolate gate structure reduces write current stress and extends device life.
[0019] The 2T1FC ferroelectric memory cell provided in this application can achieve low-voltage writing with strong retention, making it suitable for energy-constrained edge AI devices; it achieves multi-level state control through modulated ferroelectric capacitors, supports analog weight storage and calculation functions, and has low power consumption and high reliability characteristics.
[0020] The 2T1FC ferroelectric memory cell provided in this application integrates a ferroelectric capacitor with two transistors, which greatly reduces the cell size of the ferroelectric memory and increases the storage density.
[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description
[0022] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:
[0023] Figure 1 This is a top view of the 2T1FC ferroelectric memory cell of Embodiment 1 of this application;
[0024] Figure 2 This is a right view of the 2T1FC ferroelectric memory cell of Embodiment 1 of this application;
[0025] Figure 3 This is a schematic diagram of the memory array structure of Embodiment 2 of this application.
[0026] Figure label:
[0027] 10-Silicon substrate, 11-Active device region, 12-Shallow trench isolation region, 13-First diffusion region, 14-Second diffusion region, 15-Third diffusion region, 16-First gate stack, 17-Control line, 18-Second gate stack, 19-Memory gate pad, 20-Bit line contact, 21-Source line contact, 22-Memory gate contact, 23-Bit line, 24-Source line, 25-Memory gate contact pad, 26-Memory gate line, 27-Through-hole pad, 28-Bottom electrode, 29-TIN, 30-Ferroelectric layer, 31-Top electrode, 32-Board line, 40-Ferroelectric capacitor. Detailed Implementation
[0028] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.
[0029] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0030] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0031] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.
[0032] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.
[0033] It should be noted that 2T1FC (two transistors and a single ferroelectric capacitor) in the text refers to two transistors and one ferroelectric capacitor.
[0034] Example 1
[0035] In the embodiments of this application, a 2T1FC ferroelectric memory cell is provided. Figure 1 This is a top view of the 2T1FC ferroelectric memory cell of Embodiment 1 of this application. Figure 2 This is a right view of the 2T1FC ferroelectric memory cell of Embodiment 1 of this application. The following will be combined with... Figure 1 and Figure 2 The 2T1FC ferroelectric memory cell of this application will be described in further detail.
[0036] The 2T1FC ferroelectric memory cell of this application embodiment includes:
[0037] A silicon substrate 10, an active device region 11 disposed on the silicon substrate 10, and the silicon substrate 10 further having a shallow trench isolation region 12 surrounding the active device region 11, the shallow trench isolation region 12 being filled with oxide to isolate the active device region 11.
[0038] A first diffusion region 13, a second diffusion region 14 and a third diffusion region 15 are formed on the active device region 11. A gate stack 16 of a control transistor is formed between the first diffusion region 13 and the second diffusion region 14, and a gate stack 18 of a storage transistor is formed between the second diffusion region 14 and the third diffusion region 15.
[0039] It is understandable that the first diffusion region 13 constitutes the drain of the control transistor, the second diffusion region 14 constitutes the drain of the storage transistor and the source of the control transistor, that is, the source of the control transistor and the drain of the storage transistor share the second diffusion region 14, and the third diffusion region 15 constitutes the source of the storage transistor.
[0040] In this embodiment, the first diffusion region 13, the second diffusion region 14 and the third diffusion region 15 are all N+ diffusion regions (representing highly doped N-type semiconductor regions).
[0041] In this embodiment, the gate stack 16 of the control transistor and the gate stack 18 of the storage transistor each include, from bottom to top, a gate oxide layer, a high dielectric constant (K) dielectric layer and a TiN layer.
[0042] In this embodiment, a control line 17 is formed on the gate stack 16 of the control transistor; a bit line 23 is formed in the first diffusion region 13 through the bit line contact 20; and an active line 24 is formed in the third diffusion region 15 through the source line contact 21.
[0043] In this embodiment, a storage gate pad 19 is formed on the gate stack 18 of the storage transistor, a storage gate pad 25 is formed above the storage gate pad 19 through the storage gate contact 22, and a storage gate line 26 is formed on the storage gate pad 25.
[0044] It should be noted that bit line contact 20, source line contact 21 and memory gate contact 22 are all composed of interlayer dielectric, contact holes formed on the interlayer dielectric, and conductive metal filled in the contact holes.
[0045] In this embodiment, the ferroelectric capacitor 40 is a three-dimensional planar ferroelectric capacitor, including a bottom electrode 28, a ferroelectric layer 30 and a top electrode 31. The bottom electrode 28 is connected to the storage gate line 26 through a through-hole pad 27; a plate line 32 is formed on the top electrode 31.
[0046] In this embodiment, the ferroelectric layer 30 is made of HfZrO2 material, and a TIN is also provided between the ferroelectric layer 30 and the bottom electrode 28 and the top electrode 31.
[0047] The write operation of the 2T1FC ferroelectric memory cell in this embodiment is as follows: a voltage is applied to the plate line 32 of the 2T1FC ferroelectric memory cell, and the control transistor is activated through the control line 17; a differential voltage is applied between the plate line 32 and the memory gate line 26, and polarization is induced in the ferroelectric capacitor 40; the ferroelectric capacitor 40 induces a programmable offset in the threshold voltage of the memory transistor; after the write pulse, the memory gate line 26 is pulled to floating or held at an enhanced voltage to prevent charge leakage and ensure strong polarization stability.
[0048] It is understandable that the differential voltage can be either a first polarization voltage or a second polarization voltage. The first polarization voltage and the second polarization voltage have opposite polarities, causing the ferroelectric capacitor 40 to be polarized in different directions, thereby enabling the writing of logic 0 or logic 1.
[0049] The read operation of the 2T1FC ferroelectric memory cell in this embodiment is as follows: the control transistor is activated via control line 17.
[0050] Bit line 23, precharged to the reference voltage, senses the on-state of the memory transistor; memory gate line 26 is pulled to the floating state;
[0051] Based on the remaining polarization state of the ferroelectric capacitor 40, the conduction path of the storage transistor changes, transforming into a readable logic state; due to the isolated access path, the read operation does not interfere with the polarization state.
[0052] Understandably, during reading, the logic state of the 2T1FC ferroelectric memory cell is determined based on the drain-to-source current of the storage transistor, i.e., the drain current (Ids): a high drain current (on state) indicates that the polarization configuration of the ferroelectric capacitor 40 results in a low effective threshold voltage; a low drain current (off state) indicates that the reverse polarization configuration of the ferroelectric capacitor 40 results in a high threshold voltage. High drain current means that when the gate voltage exceeds the threshold voltage, the channel is fully open, and the drain-to-source current reaches its saturation value. Low drain current means that when the gate voltage is below the threshold voltage, the channel does not form a conductive path, and the drain-to-source current drops to an extremely low value.
[0053] Example 2
[0054] In the embodiments of this application, a memory array is also provided, including a plurality of 2T1FC ferroelectric memory cells as described in Embodiment 1, wherein the plurality of 2T1FC ferroelectric memory cells perform in-memory computation operations in parallel.
[0055] Figure 3 This is a schematic diagram of the memory array structure of Embodiment 2 of this application, as shown below. Figure 3 As shown, the memory array of this application embodiment includes a plurality of 2T1FC ferroelectric memory cells as described above. Each 2T1FC ferroelectric memory cell is arranged in an array. The 2T1FC ferroelectric memory cells in the same row are configured with the same control line 17 and the same memory gate line 26. The 2T1FC ferroelectric memory cells in the same column are configured with the same bit line 23, the same board line 32 and the same source line 24, thereby realizing write and read operations on the selected 2T1FC ferroelectric memory cells.
[0056] In this embodiment, the memory array accesses selected rows by accepting multi-step voltage access to avoid interference with partially selected and unselected cells. Interference with unselected or partially selected cells is avoided by accepting appropriate Vpp and Vdd (voltages on the bit lines and source lines).
[0057] Example 3
[0058] In the embodiments of this application, an AI chip is also provided, including a memory array as described in Embodiment 2. AI chips employing this memory array significantly improve area efficiency and signal tolerance.
[0059] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A 2T1FC ferroelectric memory cell, characterized in that, include: A silicon substrate has an active device region on it, on which a storage transistor and a control transistor are formed. The source of the control transistor is connected to the drain of the storage transistor. A storage gate line is formed on the gate stack of the storage transistor, and a ferroelectric capacitor is formed on the storage gate line.
2. The 2T1FC ferroelectric memory cell according to claim 1, characterized in that, A first diffusion region, a second diffusion region, and a third diffusion region are formed on the active device region. A gate stack of the control transistor is formed between the first diffusion region and the second diffusion region, and a gate stack of the storage transistor is formed between the second diffusion region and the third diffusion region.
3. The 2T1FC ferroelectric memory unit according to claim 2, characterized in that, Control lines are formed on the gate stack of the control transistor.
4. The 2T1FC ferroelectric memory unit according to claim 2, characterized in that, The first diffusion region has a bit line formed through bit line contact.
5. The 2T1FC ferroelectric memory unit according to claim 2, characterized in that, The third diffusion region forms an active line through source line contact.
6. The 2T1FC ferroelectric memory cell according to claim 1, characterized in that, A storage gate pad is formed on the gate stack of the storage transistor, and a storage gate pad is formed above the storage gate pad through a storage gate contact. The storage gate line is formed on the storage gate pad.
7. The 2T1FC ferroelectric memory cell according to claim 1, characterized in that, The ferroelectric capacitor includes a bottom electrode, a ferroelectric layer, and a top electrode; the bottom electrode is connected to the storage gate line through a through-hole pad; and a plate line is formed on the top electrode.
8. The 2T1FC ferroelectric memory cell according to claim 1, characterized in that, It also includes a shallow trench isolation region and oxides located within the shallow trench isolation region; the shallow trench isolation region is arranged around the active device region.
9. The 2T1FC ferroelectric memory cell according to claim 1, characterized in that, The gate stack, from bottom to top, comprises: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN layer.
10. A memory array, characterized in that, It includes the 2T1FC ferroelectric memory cell as described in any one of claims 1-9.