Semiconductor die and stacked semiconductor device

Abstract

A semiconductor die and a stacked semiconductor device are provided. The semiconductor die includes a back-end dielectric layer; a bonding dielectric layer over the back end dielectric layer; the semiconductor die includes top conductive structures of different sizes, and bonding vias are formed only on the larger top conductive structures. Formation of the bond vias on the larger top conductive structure results in a smaller vertical dimension of the bond vias in the semiconductor die, which reduces the amount of narrowing occurring in the width of the bond vias. This results in a larger amount of surface area contact between the bottom of the bond via and the underlying top conductive structure, enabling low contact resistance between the bond via and the underlying top conductive structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor die and a stacked semiconductor device. Background Technology

[0002] In the semiconductor industry, bonding is a technique used to form stacked semiconductor devices and three-dimensional integrated circuits. Some examples of bonding include wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding, among others. Utility Model Content

[0003] In some embodiments disclosed herein, a semiconductor die includes a back-end dielectric layer, a bonding dielectric layer, a metallization layer, a bonding via, and a bonding pad. The bonding dielectric layer is on top of the back-end dielectric layer. The metallization layer is in the back-end dielectric layer and includes a first top conductive structure and a second top conductive structure. The first top conductive structure has a first width, wherein the entire first top surface of the first top conductive structure is in solid contact with the back-end dielectric layer. The second top conductive structure has a second width greater than the first width. The bonding via is in solid contact with the second top surface of the second top conductive structure. The bonding pad is in solid contact with the bonding via.

[0004] In some embodiments disclosed herein, a stacked semiconductor device includes a first semiconductor die and a second semiconductor die, wherein the second semiconductor die is bonded to the first semiconductor die such that the first semiconductor die and the second semiconductor die are vertically disposed in the semiconductor device. The first semiconductor die includes a first back-end dielectric layer, a first bonding dielectric layer, a first metallization layer, a first bonding via, and a first bonding pad. The first bonding dielectric layer is above the first back-end dielectric layer. The first metallization layer is in the first back-end dielectric layer and includes a first top conductive structure and a second top conductive structure. The first top conductive structure has a first width, wherein the entire first top surface of the first top conductive structure is in solid contact with the first back-end dielectric layer. The second top conductive structure has a second width greater than the first width. The first bonding via is in solid contact with the second top surface of the second top conductive structure. The first bonding pad is in solid contact with the first bonding via. The second semiconductor die includes a second back-end dielectric layer, a second bonding dielectric layer, a second metallization layer, a second bonding via, and a second bonding pad. The second bonding dielectric layer is below the second back-end dielectric layer. The second metallization layer is in the second back-end dielectric layer and includes a third top conductive structure. The second bonding via is in solid contact with the third top surface of the third top conductive structure. The second bonding pad is in solid contact with the second bonding via. The first bonding pad of the first semiconductor die and the second bonding pad of the second semiconductor die are bonded by metal-to-metal bonding. The first bonding dielectric layer of the first semiconductor die and the second bonding dielectric layer of the second semiconductor die are bonded by dielectric-to-dielectric bonding.

[0005] In some embodiments disclosed herein, a stacked semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first back-end dielectric layer, a first bonding dielectric layer, a first metallization layer, a first bonding via, and a first bonding pad. The first bonding dielectric layer is above the first back-end dielectric layer. The first metallization layer, within the first back-end dielectric layer, includes a first top conductive structure. The first bonding via is in solid contact with a first top surface of the first top conductive structure. The first bonding pad is in solid contact with the first bonding via. The second semiconductor die is bonded to the first semiconductor die and includes a second back-end dielectric layer, a second bonding dielectric layer, a second metallization layer, a second bonding via, and a second bonding pad. The second bonding dielectric layer is below the second back-end dielectric layer. The second metallization layer, within the second back-end dielectric layer, includes a second top conductive structure and a third top conductive structure. The second top conductive structure has a second width, wherein the entire second top surface of the second top conductive structure is in solid contact with the second back-end dielectric layer. The third top conductive structure has a third width greater than the second width, wherein the second thickness of the second top conductive structure is less than the third thickness of the third top conductive structure. The second bonding via is in solid contact with the third top surface of the third top conductive structure. The second bonding pad is in solid contact with the second bonding via. Attached Figure Description

[0006] The state revealed here is in conjunction with the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic diagram of an example of the semiconductor device described herein;

[0008] Figures 2A to 2C This is a schematic diagram of the semiconductor device described in this article;

[0009] Figures 3A to 3O This is a schematic diagram illustrating an example embodiment of forming the semiconductor die described herein;

[0010] Figure 4A and Figure 4B This is a schematic diagram illustrating an example embodiment of the semiconductor device described herein;

[0011] Figure 5 This is a schematic diagram of an example of the semiconductor device described herein;

[0012] Figure 6 This is a schematic diagram of an example of the semiconductor device described herein;

[0013] Figure 7 This is a schematic diagram of an example of the semiconductor device described herein;

[0014] Figure 8 This is a flowchart of an example process associated with forming the semiconductor device described herein.

[0015] [Symbol Explanation]

[0016] 100: Semiconductor devices

[0017] 102, 104: Semiconductor wafers

[0018] 106, 108: Conductor grains

[0019] 110: Joint Interface

[0020] 112, 114: Device layer

[0021] 116, 118: Interconnection layer

[0022] 200: Examples

[0023] 202:Substrate

[0024] 204: Integrated Circuit Devices

[0025] 206: Dielectric layer

[0026] 208: Contact

[0027] 210: Back-end dielectric layer

[0028] 212:ESL

[0029] 214: Conductive Structure

[0030] 216: Interconnection Structure

[0031] 218: Top Interconnect Structure

[0032] 220: Barrier Layer

[0033] 222: Adhesive layer

[0034] 224: Back-end dielectric layer

[0035] 226: Top metallization layer

[0036] 228: Top conductive structure

[0037] 230: Top conductive structure

[0038] 232: Connecting through hole

[0039] 234: Joint gasket

[0040] 236: Bonding Dielectric Layer

[0041] 238:Substrate

[0042] 240: Integrated circuit device

[0043] 242: Dielectric layer

[0044] 244: Contact

[0045] 246: Back-end dielectric layer

[0046] 248:ESL

[0047] 250: Conductive structure

[0048] 252: Interconnection Structure

[0049] 254: Top Interconnect Structure

[0050] 256: Barrier Layer

[0051] 258: Adhesive layer

[0052] 260: Back-end dielectric layer

[0053] 262: Top metallization layer

[0054] 264, 266: Top conductive structure

[0055] 268: Connecting through hole

[0056] 270: Joint gasket

[0057] 272: Bonding Dielectric Layer

[0058] 274, 276: Connection Structure

[0059] 300: Implementation Examples

[0060] 302, 304: Groove

[0061] 306, 308: Conformal layers

[0062] 310: Patterned masking layer

[0063] 312: Groove

[0064] 314: Fourth Groove

[0065] 400: Implementation Example

[0066] 500: Examples

[0067] 502, 504: Connection Structure

[0068] 600: Instance

[0069] 700: Instance

[0070] 702: Connecting through hole

[0071] 704: Joint gasket

[0072] 800: Process

[0073] 810,880: Square

[0074] D1~D9: Dimensions

[0075] x: direction

[0076] z: Direction Detailed Implementation

[0077] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0079] Bonding pads and bonding vias are widely used to bond semiconductor dies to form three-dimensional semiconductor devices. Bonding of a first semiconductor die to a second semiconductor die can be achieved by bonding bonding pads on the first semiconductor die to bonding pads on the second semiconductor die to form a metal-to-metal bond, and by bonding dielectric layers surrounding the bonding pads on the first and second semiconductor dies to form a dielectric-to-dielectric bond. Bonding vias in the semiconductor die can be coupled to underlying metallization layers that are used to route signals and / or power within the semiconductor die and / or between semiconductor dies bonded to another semiconductor die.

[0080] Some semiconductor dies have top conductive structures of different sizes within the same metallization layer for different functions (e.g., larger top conductive structures for routing higher power signals and smaller top conductive structures for routing lower power signals). Different sized top conductive structures within the same metallization layer below a bonding via in a semiconductor die can result in different vertical dimensions (e.g., different lengths) of the bonding via in the semiconductor die. Because the bonding via is formed in a groove in the dielectric layer, a bonding via formed above a shorter top conductive structure will ultimately be longer in the vertical dimension within the semiconductor die than a bonding via formed above a taller top conductive structure.

[0081] The longer the via in a semiconductor device, the more likely it is to experience (more substantially) increased contact resistance. This increased contact resistance stems from the narrowing of the via width from its top to its bottom. This narrowing occurs because the via is formed in a groove etched into the dielectric layer and conforms to the groove's profile. The deeper the groove is etched into the dielectric layer, the greater the narrowing occurs from the top to the bottom of the groove. This is because the etchant used to form the groove remains in contact with the dielectric layer for a longer duration at the top of the groove than at the bottom. This results in a tapered profile where the top width of the groove is greater than the bottom width, thus narrowing the width of the via formed within the groove. The smaller width at the bottom of the via results in a smaller surface area contact between the via and the underlying conductive structure, leading to increased contact resistance between the via and the underlying conductive structure.

[0082] In some embodiments described herein, the semiconductor die includes top conductive structures of varying sizes, with bonding vias and associated bonding pads formed only on the larger top conductive structure. Forming bonding vias on the larger top conductive structure results in a smaller vertical dimension (e.g., a shorter length) of the bonding via in the semiconductor die, which reduces the amount of narrowing that occurs in the width of the bonding via. Specifically, the larger top conductive structure in the semiconductor die may be taller than the smaller top conductive structure in the semiconductor die, thus reducing the vertical distance the bonding via spans within the semiconductor die, which further reduces the amount of narrowing that occurs in the width of the bonding via. This results in a larger surface area contact between the bottom of the bonding via and the underlying top conductive structure (e.g., the larger top conductive structure), enabling a low contact resistance between the bonding via and the underlying top conductive structure.

[0083] Figure 1 This is a schematic diagram of the semiconductor device 100 described herein. (As shown...) Figure 1As shown, semiconductor device 100 is formed by bonding semiconductor wafer 102 and semiconductor wafer 104. For example, a bonding tool can be used to perform a bonding operation to bond semiconductor wafer 102 and semiconductor wafer 104 by forming a metal-to-metal bond and / or a dielectric-to-dielectric bond between semiconductor wafer 102 and semiconductor wafer 104. In the bonding operation, semiconductor dies 106 on semiconductor wafer 102 are bonded to associated semiconductor dies 108 on semiconductor wafer 104 to form semiconductor device 100 (e.g., a stacked semiconductor device). The semiconductor device 100 is then diced and packaged. Other processing steps may be performed to form semiconductor device 100.

[0084] Semiconductor die 106 and semiconductor die 108 may be bonded at bonding interface 110. Semiconductor device 100 includes stacked semiconductor devices, wherein semiconductor die 106 and semiconductor die 108 are stacked or vertically arranged in the z-direction within semiconductor device 100. Semiconductor die 106 may include system-on-chip (SoC) dies, such as logic dies, central processing unit (CPU) dies, graphics processing unit (GPU) dies, digital signal processing (DSP) dies, application-specific integrated circuit (ASIC) dies, and / or another type of SoC die. Alternatively, semiconductor die 106 may include memory dies, input / output (I / O) dies, pixel sensor dies, and / or another type of semiconductor die. The memory die may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, NAND flash dies, high bandwidth memory (HBM) dies, and / or another type of memory die. Semiconductor die 108 may include the same type of semiconductor die as semiconductor die 106, or may include different types of semiconductor dies.

[0085] like Figure 1As further shown, semiconductor die 106 may include device layer 112, and semiconductor die 108 may include device layer 114. Device layer 112 and device layer 114 may respectively include integrated circuit devices in semiconductor die 106 and semiconductor die 108. Integrated circuit devices may include transistors, pixel sensors, capacitors, resistors, other active circuit devices and / or other passive circuit devices, and other examples.

[0086] Semiconductor die 106 may include an interconnect layer 116 above device layer 112. Semiconductor die 108 may include an interconnect layer 118 below device layer 114. Interconnect layer 116 and interconnect layer 118 may each include conductive structures that interconnect integrated circuit devices in device layer 112 and device layer 114, respectively. Alternatively, interconnect layer 116 and interconnect layer 118 may each include conductive structures that electrically connect semiconductor die 106 and semiconductor die 108.

[0087] The bonding interface 110 may be located between interconnect layers 116 and 118, and may include portions of each of interconnect layers 116 and 118. The bonding interface 110 may include conductive structures in interconnect layers 116 and 118 bonded together by metal-to-metal bonding, and / or dielectric layers in interconnect layers 116 and 118 bonded together by dielectric-to-dielectric bonding.

[0088] As mentioned above, Figure 1 Provided as an example. Other instances may differ from those provided. Figure 1 As stated above.

[0089] Figures 2A to 2C This is a schematic diagram of example 200 of the semiconductor device 100 described herein. Figure 2A The diagram shows a cross-sectional view of semiconductor device 100, detailing semiconductor die 106 and semiconductor die 108. Specifically, Figure 2A Further details of device layers 112 and 114, interconnect layers 116 and 118, and interface 110 are shown.

[0090] like Figure 2A As shown, the device layer 112 of the semiconductor die 106 includes a substrate 202. The substrate 202 may correspond to a portion of the semiconductor wafer 102 on which the semiconductor die 106 is formed. The substrate 202 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. The substrate 202 may extend in the semiconductor die 106 in the x-direction and / or the y-direction.

[0091] The device layer 112 of the semiconductor die 106 includes integrated circuit devices 204 in and / or on the substrate 202. The integrated circuit devices 204 include transistors (e.g., planar transistors, fin field-effect transistors (finFETs), gate all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of passive and / or active integrated circuit devices.

[0092] A dielectric layer 206, comprising a device layer 112, is included above substrate 202. Dielectric layer 206 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. In some embodiments, a portion of integrated circuit device 204 is included in dielectric layer 206. For example, the gate structure of a transistor in integrated circuit device 204 may be included in dielectric layer 206, and the source / drain regions and channel regions of the transistor may be included in substrate 202. Alternatively, contacts 208 for integrated circuit device 204 may be included in dielectric layer 206. Contacts 208 may include sockets, vias, pads, and / or other types of electrical contacts. In some embodiments, integrated circuit device 204 includes one or more source / drain contacts and one or more gate contacts. Contacts 208 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti), and other examples. In some implementations, one or more liner layers are included between the contact 208 and the dielectric layer 206 to facilitate adhesion between the contact 208 and the dielectric layer 206. The liner layer may include tantalum nitride (TaN), titanium nitride (TiN), and / or another suitable liner layer.

[0093] The dielectric layer 206 includes a dielectric material that allows for selective etching or non-etching of various portions of the substrate 202 and / or the integrated circuit device 204, and / or the integrated circuit device 204 in the electrical isolation layer 112. The dielectric layer 206 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x (and / or another oxide material), and / or another type of dielectric material. The dielectric layer 206 may extend in the semiconductor die 106 in the x-direction and / or y-direction.

[0094] An interconnect layer 116 includes semiconductor dies 106 on the substrate 202 and the integrated circuit device 204. In some embodiments, one or more integrated circuit devices 204 are included in the interconnect layer 116 (e.g., back-end memory devices, back-end resistors, back-end capacitors, radio frequency (RF) switches, optical modulators, waveguides). The interconnect layer 116 includes a plurality of dielectric layers disposed in a direction generally perpendicular to the substrate 202 (e.g., the z-direction). The dielectric layers may include back-end dielectric layers 210 (e.g., ILD layers, intermetallic dielectric (IMD) layers) and ESL 212 disposed alternately in the z-direction. Each of the back-end dielectric layers 210 may include an oxide (e.g., silicon oxide (SiO2)). x The dielectric material may be silicon nitride (Si) and / or another oxide material, undoped silicate glass (USG), borosilicate glass (BSG), fluorine-containing silicate glass (FSG), and / or another suitable dielectric material. In some embodiments, the back-end dielectric layer 210 comprises an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. ESL 212 may each comprise silicon nitride (Si) x N y The dielectric material may be silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the back-end dielectric layer 210 and ESL 212 comprise different dielectric materials to provide etch selectivity, enabling the formation of various structures in the interconnect layer 116. The back-end dielectric layer 210 and ESL 212 may each extend in the semiconductor die 106 in the x-direction and / or the y-direction.

[0095] Interconnect layer 116 includes a plurality of conductive interconnects in back-end dielectric layer 210 and ESL 212. The conductive interconnects are electrically coupled and / or physically coupled to one or more of the integrated circuit devices 204 in device layer 112 and / or interconnect layer 116. The conductive interconnects correspond to circuit routes that enable signals and / or power to be provided to and / or from the integrated circuit devices 204. The conductive interconnects may include combinations of conductive structures 214 (e.g., trenches, conductive lines) interconnected via interconnect structures 216 (e.g., vias). The conductive structures 214 and interconnect structures 216 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials.

[0096] like Figure 2A As shown, the conductive interconnects in interconnect layer 116 can be arranged vertically (e.g., in the z-direction) to facilitate the routing of electrical signals and / or power between device layers 112, between integrated circuit devices 204 via interconnect layer 116, and / or between integrated circuit devices 204 and semiconductor die 108. The conductive interconnects can be configured with alternating layers of metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer may include one or more conductive structures 214 laterally arranged in the xy-plane within interconnect layer 116, and each via layer may include one or more interconnect structures 216 laterally arranged in the xy-plane within interconnect layer 116. As an example, a metal-0 (M0) layer (including one or more conductive structures 214) may be located at the bottom of interconnect layer 116 and coupled to a contact 208 in integrated circuit device 204 in device layer 112; a via-1 (V1) layer (including one or more interconnect structures 216) may be located above and coupled to the M0 layer in interconnect layer 116; a metal-1 (M1) layer may be located above and coupled to the V1 layer in interconnect structure 216; a via-2 (V2) layer may be located above and coupled to the M1 layer in interconnect layer 116; a metal-2 (M2) layer may be located above and coupled to the V2 layer in interconnect layer 116, and so on. In some embodiments, interconnect layer 116 includes nine (9) stacked metallization layers (e.g., M0 to M8). In some embodiments, interconnect layer 116 includes another number of stacked metallization layers.

[0097] Interconnect layer 116 includes a top via layer and a top metallization layer. The top via layer is the topmost via layer in interconnect layer 116 and is the via closest to the bonding interface 110. Similarly, the top metallization layer is the topmost metallization layer in interconnect layer 116 and is the metallization layer closest to the bonding interface 110. The top via layer includes a top interconnect structure 218 (top via) in the back-end dielectric layer 210 and / or ESL 212. The top interconnect structure 218 may include a copper (Cu) structure and / or another type of metal structure. A barrier layer 220 is included between the top interconnect structure 218 and the back-end dielectric layer 210 and / or ESL 212 to prevent or minimize the diffusion of material (e.g., copper atoms) of the top interconnect structure 218 into the surrounding back-end dielectric layer 210 and / or surrounding ESL 212. Examples of barrier layer 220 include tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples. In some embodiments, an adhesion layer 222 is included between the top interconnect structure 218 and the barrier layer 220. The adhesion layer 222 may include a material that promotes adhesion between the top interconnect structure 218 and the surrounding rear dielectric layer 210 and / or the surrounding ESL 212. In some embodiments, the adhesion layer 222 includes a copper seed layer. In some embodiments, the adhesion layer 222 includes another type of adhesion material that promotes adhesion of copper to the dielectric material.

[0098] A back-end dielectric layer 224 is included above the back-end dielectric layer 210 and ESL 212 of interconnect layer 116. The back-end dielectric layer 224 may be partially included in the bonding interface 110 between semiconductor die 106 and semiconductor die 108. The back-end dielectric layer 224 may include one or more ELK dielectric materials, such as carbon-doped silicon oxide (C-SiO2). x amorphous fluorinated carbon (aC) x F y Poly(p-xylene), bis(benzocyclobutene) (BCB), polytetrafluoroethylene (PTFE), and / or silicon carbide (SiOC) polymers. In some embodiments, the ELK dielectric material used for the back-end dielectric layer 224 includes porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiO2). x ), and other examples. Alternatively, the back-end dielectric layer 224 may include silicon oxide (SiO2), etc. x Such as SiO2), USG, BSG, and / or another suitable dielectric material.

[0099] A top metallization layer 226 is included in the back-end dielectric layer 224. The top metallization layer 226 is above and electrically coupled to the top via layer in the interconnect layer 116. The top metallization layer 226 includes several types of top conductive structures, including top conductive structure 228 and top conductive structure 230. Top conductive structure 228 is physically smaller (e.g., shorter and narrower) than top conductive structure 230 and is used only for signal and / or power routing (e.g., intra-die routing) in the semiconductor die 106. In other words, top conductive structure 228 is not coupled to the bonding structures in the semiconductor die 106 in the bonding interface 110. As a result, the entire top surface of top conductive structure 228 is in direct physical contact with and covered by the back-end dielectric layer 224.

[0100] The top conductive structure 230 is physically larger (e.g., taller and wider) than the top conductive structure 228 and serves not only for signal and / or power routing (e.g., inter-die routing) between semiconductor dies 106 and 108, but also to support bonding structures in semiconductor die 106. Each of the top conductive structures 230 is coupled to a bonding via 232 in the rear dielectric layer 224. Therefore, at least a portion of the top surface of each of the top conductive structures 230 is in direct physical contact with the associated bonding via 232 located in the bonding interface 110. In some embodiments, another portion of the top surface of each of the top conductive structures 230 (e.g., the portion surrounding the portion in direct physical contact with the bonding via 232) is in direct physical contact with the rear dielectric layer 224.

[0101] In some embodiments, signals and / or power can be routed between top conductive structures 228. In some embodiments, signals and / or power can be routed between top conductive structures 230. In some embodiments, signals and / or power in the top metallization layer 226 can be directly routed via a direct connection between top conductive structures 228 and top conductive structures 230. In some embodiments, signals and / or power can be indirectly routed between top conductive structures 228 and top conductive structures 230 via one or more top conductive structures 214, via one or more interconnect structures 216, and / or via one or more top interconnect structures 218.

[0102] Each of the bonding vias 232 includes a via structure that extends in the z-direction. Each of the bonding vias 232 may be physically and electrically coupled to an associated top conductive structure 230. Coupled with the top conductive structure 230 (e.g., rather than the top conductive structure 228) the bonding vias 232, resulting in shorter bonding vias 232 (e.g., shorter in the z-direction), which reduces the contact resistance between the bonding vias 232 and the top metallization layer 226.

[0103] A bonding pad 234 is included on the bonding via 232, such that the bonding pad 234 is physically and electrically coupled to the bonding via 232. Each bonding pad 234 may have a z-direction dimension smaller than the x-direction dimension and / or y-direction dimension. The bonding via 232 and the bonding pad 234 may each comprise tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive metals.

[0104] A bonding pad 234 is included in the bonding dielectric layer 236 above and / or on the back-end dielectric layer 224. The bonding dielectric layer 236 may be included in the bonding interface 110 and may include silicon oxynitride (SiON) and / or another suitable bonding dielectric material.

[0105] like Figure 2A As further shown, semiconductor die 108 may include a combination and / or configuration of structures and / or layers similar to those of semiconductor die 106. For example, semiconductor die 108 may include a combination of substrate 238, integrated circuit device 240, dielectric layer 242, and contact 244 in device layer 114 of semiconductor die 108 (similar to device layer 112 of semiconductor die 106). As another example, semiconductor die 108 may include a combination of back-end dielectric layer 246, ESL 248, conductive structure 250, and interconnect structure 252 in interconnect layer 118 of semiconductor die 108 (similar to interconnect layer 116 of semiconductor die 106). These layers and / or structures may have a reverse z-direction configuration relative to semiconductor die 106, which allows semiconductor die 106 and semiconductor die 108 to be bonded at bonding interface 110, such that interconnect layer 116 and interconnect layer 118 face each other.

[0106] Furthermore, interconnect layer 118 includes a top via layer and a top metallization layer. The top via layer is the topmost via layer in interconnect layer 118 and is the via closest to the bonding interface 110. Similarly, the top metallization layer is the topmost metallization layer in interconnect layer 118 and is the metallization layer closest to the bonding interface 110. The top via layer includes a top interconnect structure 254 (top via) in the back-end dielectric layer 246 and / or ESL 248. The top interconnect structure 254 may include a copper (Cu) structure and / or another type of metal structure. A barrier layer 256 and / or an adhesion layer 258 may be included between the top interconnect structure 254 and the back-end dielectric layer 246 and / or ESL 248, and / or between the top interconnect structure 254 and the barrier layer 256.

[0107] A back-end dielectric layer 260 may be included above (or below) the back-end dielectric layer 246 and ESL 248 after the interconnect layer 118. The back-end dielectric layer 260 may be partially included in the bonding interface 110 between the semiconductor die 106 and the semiconductor die 108. The back-end dielectric layer 260 may include a material similar to that of the back-end dielectric layer 224, and / or may include a different material.

[0108] A top metallization layer 262 is included in the back-end dielectric layer 260. The top metallization layer 262 is below and electrically coupled to the top via layer in the interconnect layer 118. The top metallization layer 262 includes several types of top conductive structures, including top conductive structure 264 and top conductive structure 266. Top conductive structure 264 is physically smaller (e.g., shorter and narrower) than top conductive structure 266 and is used solely for signal and / or power routing (e.g., intra-die routing) within the semiconductor die 108. In other words, top conductive structure 264 is not coupled to the bonding structures in the semiconductor die 108 within the bonding interface 110. As a result, the entire top surface of top conductive structure 264 is in direct physical contact with and covered by the back-end dielectric layer 260.

[0109] The top conductive structure 266 is physically larger (e.g., taller and wider) than the top conductive structure 264 and serves not only for signal and / or power routing (e.g., inter-die routing) between semiconductor dies 106 and 108, but also to support the bonding structure of semiconductor die 108. Each of the top conductive structures 266 is coupled to a bonding via 268 in the rear dielectric layer 260. Therefore, at least a portion of the top surface of each of the top conductive structures 266 is in direct physical contact with the associated bonding via 268 located in the bonding interface 110. In some embodiments, another portion of the top surface of each of the top conductive structures 266 (e.g., the portion surrounding the portion in direct physical contact with the bonding via 268) is in direct physical contact with the top metallization layer 262.

[0110] In some embodiments, signals and / or power can be routed between top conductive structures 264. In some embodiments, signals and / or power can be routed between top conductive structures 266. In some embodiments, signals and / or power in the top metallization layer 262 can be directly routed via a direct connection between top conductive structures 264 and top conductive structures 266. In some embodiments, signals and / or power can be indirectly routed between top conductive structures 264 and top conductive structures 266 via one or more top conductive structures 250, via one or more interconnect structures 252, and / or via one or more top interconnect structures 254.

[0111] Each of the bonding vias 268 includes a via structure that extends in the z-direction. Each of the bonding vias 268 may be physically and electrically coupled to an associated top conductive structure 266. Coupled with the top conductive structure 266 (e.g., rather than the top conductive structure 264) the bonding vias 268, resulting in shorter bonding vias 268 (e.g., shorter in the z-direction), which reduces the contact resistance between the bonding vias 268 and the top metallization layer 262.

[0112] A bonding pad 270 is included on the bonding via 268, such that the bonding pad 270 is physically and electrically coupled to the bonding via 268. Each bonding pad 270 may have a z-direction dimension smaller than the x-direction dimension and / or y-direction dimension. The bonding via 268 and the bonding pad 270 may each comprise tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive metals.

[0113] A bonding pad 270 is included in the bonding dielectric layer 272 on and / or below the rear dielectric layer 260. The bonding dielectric layer 272 may be included in the bonding interface 110 and may include silicon oxynitride (SiON) and / or another suitable bonding dielectric material.

[0114] At the bonding interface 110, bonding pads 234 in semiconductor die 106 and bonding pads 270 in semiconductor die 108 are directly bonded via metal-to-metal bonding. Furthermore, bonding dielectric layer 236 of semiconductor die 106 and bonding dielectric layer 272 of semiconductor die 108 are directly bonded via dielectric-to-dielectric bonding. Bonding vias 232 and 268, and bonding pads 234 and 270 are located between top conductive structure 230 and top conductive structure 266. For example, bonding vias 232, 234, 270, and 268 are located between top conductive structure 230 and top conductive structure 266.

[0115] As described above, the top conductive structures 228 and 264 are separated from the bonding pads or bonding vias. Therefore, portions of the rear dielectric layer 224, the bonding dielectric layer 236, the rear dielectric layer 260, and the bonding dielectric layer 272 are directly included between the top conductive structures 228 and 264. For example, a portion of the bonding dielectric layer 236, a portion of the rear dielectric layer 260, and a portion of the bonding dielectric layer 272 are each directly included between the top conductive structures 228 and 264 (e.g., without intermediate bonding pads or bonding vias).

[0116] Figure 2BThe illustration shows one or more instance dimensions within semiconductor die 106. (Combined with...) Figure 2B The instance dimensions of the semiconductor die 106 illustrated and described may be additionally and / or alternatively applied to the semiconductor die 108.

[0117] like Figure 2B As shown, dimension D1 includes the cross-sectional width of the top conductive structure 228 (e.g., width in the x-direction, width in the y-direction). Dimension D1 may additionally and / or alternatively include the cross-sectional width of the top conductive structure 264. In some implementations, dimension D1 is in the range of approximately 1.2 micrometers to approximately 3 micrometers. If the cross-sectional width of the top conductive structure 228 is too large (e.g., greater than approximately 3 micrometers), insufficient spacing may be provided between adjacent top conductive structures 228, resulting in increased signal noise and / or increased parasitic capacitance, among other instances. If the cross-sectional width of the top conductive structure 228 is too small (e.g., less than approximately 1.2 micrometers), the final height of the top conductive structure 228 may be too small, resulting in increased resistance of the top conductive structure 228. If the cross-sectional width of the top conductive structure 228 is in the range of approximately 1.2 micrometers to approximately 3 micrometers, sufficient spacing of the top conductive structures 228 can be achieved, while sufficient height of the top conductive structures 228 can be achieved, thereby achieving low resistance of the top conductive structure 228. However, other ranges and values ​​of dimension D1 are also within the scope of this disclosure. In some implementations, dimension D1 ranges from approximately 1 micrometer to approximately 3.5 micrometers.

[0118] Another example, dimension D2 includes the cross-sectional width of the top conductive structure 230 (e.g., width in the x-direction, width in the y-direction). Dimension D2 may additionally and / or alternatively include the cross-sectional width of the top conductive structure 266. In some implementations, dimension D2 ranges from approximately 3 micrometers to approximately 32 micrometers. If the cross-sectional width of the top conductive structure 230 is too large (e.g., greater than approximately 32 micrometers), insufficient spacing may be provided between adjacent top conductive structures 230, resulting in increased signal noise and / or increased parasitic capacitance, among other things. If the cross-sectional width of the top conductive structure 230 is too small (e.g., less than approximately 3 micrometers), the final height of the top conductive structure 230 may be too small, which may result in an increased z-direction length of the bonding via 232. This may result in increased contact resistance of the bonding via 232. If the cross-sectional width of the top conductive structure 230 is in the range of approximately 3 micrometers to approximately 32 micrometers, sufficient spacing and sufficient height of the top conductive structure 230 can be achieved, thereby achieving low contact resistance of the bonding via 232. However, other ranges and values ​​of dimension D2 are also within the scope of this disclosure. In some embodiments, dimension D2 is in the range of approximately 2.5 micrometers to approximately 37 micrometers.

[0119] As described above, the width of the top conductive structure 230 is greater than the width of the top conductive structure 228. Similarly, the width of the top conductive structure 266 is greater than the width of the top conductive structure 264. Therefore, dimension D2 is greater than dimension D1. In some embodiments, the ratio of dimension D2 to dimension D1 ranges from approximately 2.5:1 to approximately 10.66:1. However, other ranges of the ratio of dimension D2 to dimension D1 are also within the scope of this disclosure.

[0120] Another example, dimension D3, includes the z-direction height (or thickness) of the top conductive structure 228. The z-direction height (or thickness) of the top conductive structure 228 is from the bottom of the top conductive structure 228 (which may be in a straight line with the top of the ESL 212 at the top of the top interconnect structure 218 below the top conductive structure 228) to the top of the top conductive structure 228 (the highest part of the curve of the top surface of the top conductive structure 228). In other words, the z-direction height (or thickness) of the top conductive structure 228 is from the beginning of the cone shape of the underlying top interconnect structure 218 to the top of the curvature of the top conductive structure 228. Dimension D3 may additionally and / or alternatively include the z-direction height (or thickness) of the top conductive structure 264. Another example, dimension D4, includes the z-direction height (or thickness) of the top conductive structure 230. Dimension D4 may additionally and / or alternatively include the z-direction height (or thickness) of the top conductive structure 266. As mentioned above, the height of the top conductive structure 230 is greater than the height of the top conductive structure 228. Similarly, the height of the top conductive structure 266 is greater than the height of the top conductive structure 264. Therefore, dimension D4 is greater than dimension D3, resulting in... Figure 2B The height difference corresponding to dimension D5 is shown. In some implementations, dimension D5 ranges from approximately 1.6 micrometers to approximately 2.4 micrometers. However, other ranges of dimension D5 are also within the scope of this disclosure. The height difference between top conductive structure 228 and top conductive structure 230 causes the top surface of top conductive structure 230 to be positioned closer to the bonding dielectric layer 236 than the top surface of top conductive structure 228. Similarly, the height difference between top conductive structure 264 and top conductive structure 266 causes the top surface of top conductive structure 266 to be positioned closer to the bonding dielectric layer 272 than the top surface of top conductive structure 264.

[0121] Another example, dimension D6 includes the distance (or spacing) between adjacent top conductive structures 228. Dimension D6 may additionally and / or alternatively include the distance (or spacing) between adjacent top conductive structures 264. Another example, dimension D7 includes the distance (or spacing) between adjacent top conductive structures 230. Dimension D7 may additionally and / or alternatively include the distance (or spacing) between adjacent top conductive structures 266. Because the width of the top conductive structures 228 is small, dimension D6 may be larger than dimension D7. However, in some embodiments, dimension D6 and dimension D7 may be approximately equal, and in other embodiments, dimension D7 may be larger than dimension D6.

[0122] Figure 2C The illustration shows a top view example of a semiconductor die 106 in the xy plane. As shown in the top view example, two or more top conductive structures 228 may be electrically connected to a connection structure 274. The connection structure 274 may be included in the top metallization layer 226 and allows signals and / or power to be routed between the two or more top conductive structures 228. Alternatively, the connection structure 276 may be included between the top conductive structures 228 and 230, allowing signals and / or power to be routed between the top conductive structures 228 and 230. Furthermore, the connection structure 276 allows signals and / or power to be routed between the top conductive structure 228 and the semiconductor die 108 via the top conductive structure 230.

[0123] In the semiconductor device 100, the top conductive structure 228 and the top conductive structure 230 can be arranged in the x-direction and each can extend in the y-direction. The connection structure 274 and the connection structure 276 can each extend in the x-direction in the semiconductor device 100.

[0124] As mentioned above, Figures 2A to 2C Provided as an example. Other instances may differ from those provided. Figures 2A to 2C As stated above.

[0125] Figures 3A to 3O This is a schematic diagram of an example embodiment 300 forming the semiconductor die 106 described herein. In some embodiments, one or more semiconductor processing tools may be used to perform the bonding. Figures 3A to 3O One or more of the semiconductor processing operations described herein, such as deposition tools, exposure tools, developer tools, etching tools, ion implantation tools, and / or wafer / die transport tools, and other examples. In some embodiments, one or more of the operations and / or techniques described in Example Embodiment 300 of forming semiconductor die 106 may also be performed or used to form semiconductor die 108.

[0126] Transfer to Figure 3AA substrate 202 may be provided. The substrate 202 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer (e.g., semiconductor wafer 102). Semiconductor dies 106 may be formed on the substrate 202 together with a plurality of other semiconductor dies 106.

[0127] like Figure 3B As shown, an integrated circuit device 204 may be formed in and / or on a substrate 202 in the device layer 112 of a semiconductor die 106. One or more semiconductor processing tools may be used to form one or more portions of the integrated circuit device 204. For example, a deposition tool may be used to perform various deposition operations to deposit layers in the integrated circuit device 204, and / or deposit a photoresist layer for etching portions of the substrate 202 and / or the deposited layers. As another example, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developer tool may be used to develop the pattern in the photoresist layer. As another example, an etching tool may be used to etch portions of the substrate 202 and / or the deposited layers to form the integrated circuit device 204. As another example, a planarization tool may be used to planarize portions of the integrated circuit device 204. As another example, an ion implantation tool may be used to implant ions into the substrate 202 to dope portions of the substrate 202 with one or more types of dopants (e.g., p-type dopants, n-type dopants).

[0128] like Figure 3C As shown, a dielectric layer 206 is deposited on and / or on the substrate 202 and the integrated circuit device 204 using a deposition tool. A patterned masking layer (e.g., a patterned photoresist layer, a patterned hard mask layer) can be formed on the dielectric layer 206 using a deposition tool, an exposure tool, and a development tool. Recesses can be formed in the dielectric layer 206 using an etching tool, and contacts 208 can be formed in the recesses using a deposition tool, such that the contacts 208 are physically coupled and / or electrically coupled to the integrated circuit device 204.

[0129] like Figure 3D As shown, a first portion of interconnect layer 116 is formed on device layer 112. The first portion of interconnect layer 116 may include a plurality of alternating layers forming back-end dielectric layer 210 and ESL 212, and alternating layers forming conductive structure 214 and interconnect structure 216.

[0130] The first portion of interconnect layer 116 can be fabricated as a series of sequential layers. For example, ESL 212 and back-end dielectric layer 210 can be deposited using deposition tools, each employing physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or another deposition technique. In some embodiments, planarization tools are used to planarize ESL 212 and / or back-end dielectric layer 210. Recesses can be formed in and / or through ESL 212 and back-end dielectric layer 210, and interconnect structures 216 and conductive structures 214 can be deposited in each of the recesses using deposition tools. The previous set of operations can be repeated for each subsequent layer in the first portion of interconnect layer 116. In some embodiments, a dual damascene process is used to form the layers in the first portion of interconnect layer 116.

[0131] like Figure 3E As shown, grooves 302 and 304 are formed in and / or through the back-end dielectric layer 210 and the underlying ESL 212. The top surface of one or more of the topmost conductive structures 214 in the interconnect layer 116 is exposed via one or more of the grooves 302. A photoresist layer can be formed on the topmost back-end dielectric layer 210 using a deposition tool. The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the topmost back-end dielectric layer 210 and the underlying ESL 212 to form grooves 302 and 304. In some embodiments, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0132] like Figure 3F As shown, deposition tools can be used to deposit conformal layers 306 and 308 in grooves 302 and 304. Conformal layers 306 and 308 can also be deposited on the top surface of the topmost rear dielectric layer 210. Conformal layers 306 and 308 can then be etched to form a barrier layer 220 and / or an adhesion layer 222. Conformal layers 306 and 308 can be conformally deposited using conformal deposition techniques such as ALD. Alternatively, CVD techniques and / or another suitable deposition technique can be used to deposit conformal layers 306 and 308.

[0133] like Figure 3GAs shown, a patterned masking layer 310 is formed above the topmost rear dielectric layer 210, thereby forming openings through the patterned masking layer 310 above the grooves 302 and 304. This essentially increases the depth of the grooves 302 and 304 without further etching into the interconnect layer 116. A photoresist layer can be formed above the topmost rear dielectric layer 210 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern, thereby forming the patterned masking layer 310.

[0134] like Figure 3G As further shown, the width of the groove 302 at the height of the patterned masking layer 310 (corresponding to dimension D8) is greater than the width of the groove 302 at the height of the topmost rear dielectric layer 210. In other words, the opening of the patterned masking layer 310 passing through the groove 302 extends laterally outward beyond the opening of the groove 302 in the topmost rear dielectric layer 210. This creates a dual damascene groove, where the portion of the groove 302 in the topmost rear dielectric layer 210 is the via portion of the dual damascene groove, and the portion of the groove 302 in the patterned masking layer 310 is the trench portion of the dual damascene groove. This allows the top interconnect structure 218 and the associated top conductive structure 228 to be formed in the groove 302 using the same deposition operation (or the same set of deposition operations).

[0135] Similarly, the width of the groove 304 at the height of the patterned masking layer 310 (corresponding to dimension D9) is greater than the width of the groove 304 at the height of the topmost rear dielectric layer 210. In other words, the opening of the patterned masking layer 310 passing through the groove 304 extends laterally outward beyond the opening of the groove 304 in the topmost rear dielectric layer 210. This creates a double-dotted groove, where the portion of the groove 304 in the topmost rear dielectric layer 210 is the via portion of the double-dotted groove, and the portion of the groove 304 in the patterned masking layer 310 is the trench portion of the double-dotted groove. This allows the top interconnect structure 218 and the associated top conductive structure 230 to be formed in the groove 304 using the same deposition operation (or the same set of deposition operations). Dimension D9 is greater than dimension D8, which allows the top conductive structure 230 to be formed with a larger cross-sectional width than the top conductive structure 228.

[0136] like Figure 3HAs shown, a deposition tool can be used to deposit a top interconnect structure 218 and a top conductive structure 228 on the top interconnect structure 218 in a groove 302. Furthermore, a deposition tool can be used to deposit the top interconnect structure 218 and a top conductive structure 230 on the top interconnect structure 218 in a groove 304. CVD, PVD, ALD, electroplating, and / or another suitable deposition technique can be used to deposit the top interconnect structure 218, the top conductive structure 228, and the top conductive structure 230. The top interconnect structure 218 can be deposited on a conformal layer 308, which may be an adhesion layer or a seed layer.

[0137] Since a patterned masking layer 310 is used to form the top conductive structures 228 and 230, the planarization operation of the top conductive structures 228 and 230 is omitted. This allows the top conductive structures 228 and 230 to be formed at different heights, such that the height of the top conductive structure 230 is greater than the height of the top conductive structure 228. As a result, the top conductive structures 228 and 230 have non-planar (e.g., rounded or curved) top surfaces. Furthermore, forming the top conductive structures 228 and 230 means forming the top conductive structures 228 and 230 (and the associated top interconnect structure 218) before forming the back-end dielectric layer 224. Because the top conductive structures 228 and 230 have different widths, top conductive structures 228 and 230 may have different heights. The greater width of the top conductive structure 230 provides a larger area in the groove 304 than in the groove 302, where material is to be picked up by a deposition process (e.g., electroplating or electrochemical plating). This causes material from the deposition process to accumulate in the groove 304 at a faster rate than in the groove 302, resulting in the top conductive structure 230 growing at a faster rate in height / thickness than the top conductive structure 228.

[0138] like Figure 3I As shown, after forming the top conductive structures 228 and 230 and the associated top interconnect structure 218, the patterned masking layer 310 is removed. The patterned masking layer 310 can be removed using an etching tool. An etchant with a low etching rate (or no etching of copper) for copper or the material of the top conductive structures 228 and 230 can be used to remove the patterned masking layer 310. In some implementations, over-etching may occur during the etching of the patterned masking layer 310, causing portions of the conformal layers 306 and 308 that are not below the top interconnect structure 218 to also be removed. This results in the formation of a separate barrier layer 220 (e.g., formed from the conformal layer 306) and a separate adhesion layer 222 (e.g., formed from the conformal layer 308) below the top interconnect structure 218.

[0139] like Figure 3J As shown, another ESL 212 is formed, and a rear dielectric layer 224 is formed on the ESL 212 and above the top conductive structures 228 and 230, such that the top conductive structures 228 and 230 are encapsulated within the rear dielectric layer 224. In other words, the top surface of the rear dielectric layer 224 is at a greater z-direction height than the top surfaces of the top conductive structures 228 and 230, such that the top conductive structures 228 and 230 are completely covered by the rear dielectric layer 224. Deposition tools can be used, employing PVD, ALD, CVD, oxidation, and / or another type of deposition technique to deposit the ESL 212 and the rear dielectric layer 224. In some embodiments, a planarization tool is used to planarize the top surface of the rear dielectric layer 224.

[0140] like Figure 3K As shown, a groove 312 is formed in the back-end dielectric layer 224 above the top conductive structure 230. The groove 312 extends through the back-end dielectric layer 224 to the top conductive structure 230, such that the top surface of the top conductive structure 230 is exposed via the groove 312 in the back-end dielectric layer 224. In some embodiments, over-etching may occur to ensure complete etching through the back-end dielectric layer 224 to the top surface of the top conductive structure 230. In these embodiments, some etching may occur within the top surface of the top conductive structure 230.

[0141] A groove 312 can be formed to prepare for forming a bonding via 232 in the groove 312. Since the bonding via 232 is omitted from the top conductive structure 228, the groove 312 is formed while the top conductive structure 228 is still encapsulated and covered by the rear dielectric layer 224.

[0142] In some embodiments, the pattern in the photoresist layer is used to etch the back-end dielectric layer 224 to form the groove 312. In these embodiments, a deposition tool can be used to form the photoresist layer on the back-end dielectric layer 224. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the back-end dielectric layer 224 based on the pattern to remove portions of the back-end dielectric layer 224 above the top conductive structure 230 (but not above the top conductive structure 228). In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the back-end dielectric layer 224.

[0143] like Figure 3L As shown, a bonding via 232 is formed on the top conductive structure 230. The bonding via 232 is formed in the groove 312 through the rear dielectric layer 224. The bonding via 232 can be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, after depositing the bonding via 232, a planarization tool is used to planarize the bonding via 232 such that the top surface of the bonding via 232 is substantially coplanar with the top surface of the rear dielectric layer 224.

[0144] like Figure 3M As shown, a bonding dielectric layer 236 is formed on the back-end dielectric layer 224 and the bonding via 232. The bonding dielectric layer 236 can be deposited using deposition tools, employing CVD, PVD, ALD, oxidation, and / or another suitable deposition technique. In some embodiments, the bonding dielectric layer 236 is planarized using a planarization tool after deposition.

[0145] like Figure 3N As shown, a groove 314 is formed in the bonding dielectric layer 236 above the bonding via 232. The groove 314 extends through the bonding dielectric layer 236 to the bonding via 232, such that the top surface of the bonding via 232 is exposed via the groove 314 in the bonding dielectric layer 236.

[0146] In some embodiments, a pattern in the photoresist layer is used to etch the bonding dielectric layer 236 to form a groove 314. In these embodiments, a deposition tool can be used to form the photoresist layer on the bonding dielectric layer 236. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the bonding dielectric layer 236 based on the pattern to remove portions of the bonding dielectric layer 236 above the bonding via 232 to form the groove 314. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the bonding dielectric layer 236.

[0147] like Figure 3OAs shown, a bonding pad 234 is formed on the bonding via 232. The bonding pad 234 is formed in the groove 314 through the bonding dielectric layer 236. The bonding pad 234 can be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, after depositing the bonding pad 234, a planarization tool is used to planarize the bonding pad 234 such that the top surface of the bonding pad 234 is substantially coplanar with the top surface of the bonding dielectric layer 236.

[0148] As mentioned above, Figures 3A to 3O Provided as an example. Other instances may differ from those provided. Figures 3A to 3O As stated above.

[0149] Figure 4A and Figure 4B This is a schematic diagram of an example embodiment 400 of forming the semiconductor device 100 described herein. Specifically, example embodiment 400 includes an example of bonding semiconductor die 106 and semiconductor die 108 to form the semiconductor device 100.

[0150] like Figure 4A and Figure 4B As shown, a bonding operation is performed to bond semiconductor dies 106 and 108 at bonding interface 110, such that semiconductor dies 106 and 108 are vertically arranged or stacked in the z-direction within semiconductor device 100. Semiconductor dies 106 and 108 can be vertically arranged or stacked in a wafer-on-wafer (WoW) configuration, a wafer-on-die configuration, a die-on-die configuration, and / or another direct bonding configuration. A bonding tool can be used to perform the bonding operation to bond semiconductor dies 106 and 108 at bonding interface 110. The bonding operation may include a direct physical connection between semiconductor dies 106 and 108 via bonding pads 234 of semiconductor die 106 and bonding pads 270 of semiconductor die 108, and a direct physical connection between bonding dielectric layers 236 of semiconductor die 106 and bonding dielectric layers 272 of semiconductor die 108, thereby forming a direct bond between semiconductor dies 106 and 108.

[0151] The bonding of bonding pads 234 and 270 results in an electrical connection between the top conductive structure 230 of semiconductor die 106 and the top conductive structure 266 of semiconductor die 108 via bonding pads 234 and 270, and vias 232 and 268. Since there are no bonding pads or vias on the top conductive structures 228 and 264, the rear dielectric layer 224 and 260, and the bonding dielectric layer 236 and 272 are included between the top conductive structures 228 and 264.

[0152] In some implementations, semiconductor die 106 and semiconductor die 108 are joined in a bonding operation to form portions of semiconductor wafer 102 and semiconductor wafer 104. Therefore, the self-bonded semiconductor wafer 102 and semiconductor wafer 104 can be die-cut or diced and packaged.

[0153] As mentioned above, Figure 4A and Figure 4B Provided as an example. Other instances may differ from those provided. Figure 4A and Figure 4B As stated above.

[0154] Figure 5 This is a schematic diagram of example 500 of the semiconductor device 100 described herein. Figure 5 The figure shows a cross-sectional view of the semiconductor device 100. Figure 5 As shown, example 500 of semiconductor device 100 is similar to a combination of Figure 2A Example 200 of the semiconductor device illustrated and described herein. However, example 500 of the semiconductor device 100 includes one or more connection structures 502 (e.g., not connection structure 276, or as a supplement thereof) in the interconnect layer 116 of the semiconductor die 106. The connection structure 502 may correspond to the top interconnect structure 218 and one or more conductive structures 214 below the top conductive structure 228 and the top conductive structure 230. The connection structure 502 may electrically connect the top conductive structure 228 and the top conductive structure 230 via one or more conductive structures 214, one or more interconnect structures 216, and / or one or more top interconnect structures 218. This allows signals and / or power to be routed between the top conductive structure 228 and the top conductive structure 230. Furthermore, the connection structure 502 allows signals and / or power to be routed between the top conductive structure 228 and the semiconductor die 108 via the top conductive structure 230.

[0155] Alternatively, example 500 of semiconductor device 100 includes one or more connection structures 504 (e.g., not connection structure 276, or as a supplement thereof) in the interconnect layer 118 of semiconductor die 108. Connection structure 504 may correspond to top interconnect structure 254 and one or more conductive structures 250 above top conductive structure 264 and top conductive structure 266. Connection structure 504 may electrically connect top conductive structure 264 and top conductive structure 266 via one or more conductive structures 250, one or more interconnect structures 252, and / or one or more top interconnect structures 254. This enables signal and / or power routing between top conductive structure 264 and top conductive structure 266. Furthermore, connection structure 504 enables signal and / or power routing between top conductive structure 264 and semiconductor die 106 via top conductive structure 266.

[0156] As mentioned above, Figure 5 Provided as an example. Other instances may differ from those provided. Figure 5 As stated above.

[0157] Figure 6 This is a schematic diagram of example 600 of the semiconductor device 100 described herein. Figure 6 The figure shows a cross-sectional view of the semiconductor device 100. Figure 6 As shown, example 600 of semiconductor device 100 is similar to a combination of Figure 2A Example 200 of the semiconductor device illustrated and described. However, example 600 of the semiconductor device 100 includes conductive structures 214 and interconnect structures 216 in the interconnect layer 116 of the semiconductor die 106, which electrically connect one or more top conductive structures 230 to one or more integrated circuit devices 204 in the device layer 112 of the semiconductor die 106. This enables signals and / or power to be routed between the integrated circuit device 204 and the semiconductor die 108 via the top conductive structures 230.

[0158] Alternatively, in another embodiment, example 600 of semiconductor device 100 includes conductive structures 250 and interconnect structures 252 in interconnect layer 118 of semiconductor die 108, which electrically connect one or more top conductive structures 266 to one or more integrated circuit devices 240 in device layer 114 of semiconductor die 108. This enables signals and / or power to be routed between integrated circuit devices 240 and semiconductor die 106 via top conductive structures 266.

[0159] As mentioned above, Figure 6 Provided as an example. Other instances may differ from those provided. Figure 6 As stated above.

[0160] Figure 7 This is a schematic diagram of example 700 of the semiconductor device 100 described herein. Figure 7 The figure shows a cross-sectional view of the semiconductor device 100. Figure 7 As shown, example 700 of semiconductor device 100 is similar to a combination of Figure 2A Example 200 of the semiconductor device illustrated and described. However, example 700 of the semiconductor device 100 includes a bonding via 702 in solid contact with the top conductive structure 264 of the semiconductor die 108, and a bonding pad 704 in solid contact with the bonding via 702. Figure 7 As shown, because the bonding pads and bonding vias are omitted from the top conductive structure 228 in semiconductor die 106, bonding pads 704 and bonding vias 702 are not connected to bonding pads or bonding vias in semiconductor die 106. However, bonding pads 704 and bonding vias 702 may provide an additional metallization layer in semiconductor die 108 for routing signals and / or power within semiconductor die 108.

[0161] As mentioned above, Figure 7 Provided as an example. Other instances may differ from those provided. Figure 7 As stated above.

[0162] Figure 8 This is a flowchart of an example process 800 associated with forming the semiconductor device described herein. In some implementations, one or more semiconductor processing tools are used for execution. Figure 8 One or more process blocks in the process.

[0163] like Figure 8 As shown, process 800 may include forming a first groove and a second groove (block 810) in a first dielectric layer on a substrate of the semiconductor die. For example, as described herein, one or more semiconductor processing tools may be used to form a first groove 302 and a second groove 304 in a first dielectric layer (e.g., a back-end dielectric layer 210) on a substrate 202 of the semiconductor die 106.

[0164] like Figure 8 As further shown, process 800 may include forming a patterned masking layer over the first dielectric layer, such that the first groove and the second groove are exposed via the patterned masking layer (block 820). For example, one or more semiconductor processing tools may be used to form a patterned masking layer 310 over the first dielectric layer (e.g., back-end dielectric layer 210), such that the first groove 302 and the second groove 304 are exposed via the patterned masking layer 310, as described herein. In some embodiments, a first width (e.g., dimension D8) of a first opening in the patterned masking layer 310 over the first groove 302 is smaller than a second width (e.g., dimension D9) of a second opening in the patterned masking layer 310 over the second groove 304.

[0165] like Figure 8As further shown, process 800 may include forming a first top interconnect structure in a first recess through a first opening in the patterned masking layer, and forming a first top conductive structure on the first top interconnect structure (block 830). For example, as described herein, one or more semiconductor processing tools may be used to form a first top interconnect structure 218 in a first recess 302 through a first opening in the patterned masking layer 310, and to form a first top conductive structure 228 on the first top interconnect structure 218.

[0166] like Figure 8 As further shown, process 800 may include forming a second top interconnect structure in a second recess through a second opening in the patterned masking layer, and forming a second top conductive structure on the second top interconnect structure (block 840). For example, as described herein, one or more semiconductor processing tools may be used to form a second top interconnect structure 218 in a second recess 304 through a second opening in the patterned masking layer 310, and to form a second top conductive structure 230 on the second top interconnect structure 218.

[0167] like Figure 8 As further shown, process 800 may include forming a second dielectric layer on the first dielectric layer, such that the second dielectric layer encapsulates the first top conductive structure and the second top conductive structure (block 850). For example, one or more semiconductor processing tools may be used to form a second dielectric layer (e.g., a back-end dielectric layer 224) over the first dielectric layer (e.g., a back-end dielectric layer 210), such that the second dielectric layer encapsulates the first top conductive structure 228 and the second top conductive structure 230, as described herein.

[0168] like Figure 8 As further shown, process 800 may include forming a third recess (block 860) through the second dielectric layer to the second top conductive structure. For example, as described herein, one or more semiconductor processing tools may be used to form a third recess 312 through the second dielectric layer (e.g., back-end dielectric layer 224) to the second top conductive structure 230. In some embodiments, the first top conductive structure remains encapsulated by the second dielectric layer while the third recess 312 is being formed.

[0169] like Figure 8 As further shown, process 800 may include forming a bonding via (block 870) on the second top conductive structure in a third recess in the second dielectric layer while the first top conductive structure is encapsulated by the second dielectric layer. For example, one or more semiconductor processing tools may be used to form a bonding via 232 on the second top conductive structure 230 in a third recess 312 in the second dielectric layer while the first top conductive structure 228 is encapsulated by the second dielectric layer (e.g., back-end dielectric layer 224), as described herein.

[0170] like Figure 8 As further shown, process 800 may include forming a bonding pad (block 880) on a bonding via while the first top conductive structure is encapsulated by a second dielectric layer. For example, one or more semiconductor processing tools may be used to form a bonding pad 234 on a bonding via 232 while the first top conductive structure 228 is encapsulated by a second dielectric layer (e.g., a back-end dielectric layer 224), as described herein.

[0171] Process 800 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0172] In a first embodiment, process 800 includes forming a bonding dielectric layer 236 on a second dielectric layer (e.g., a rear dielectric layer 224) and forming a fourth groove 314 in the bonding dielectric layer 236, wherein forming the bonding pad 234 includes forming the bonding pad 234 on a bonding via 232 in the fourth groove 314 in the bonding dielectric layer 236.

[0173] In the second embodiment, forming the first top conductive structure 228, alone or in combination with the first embodiment, includes forming the first top conductive structure 228 to a first height (e.g., dimension D3), and forming the second top conductive structure 230 includes forming the second top conductive structure 230 to a second height (e.g., dimension D4) greater than the first height.

[0174] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 800 includes removing the patterned masking layer 310 after forming the first top interconnect structure 218, the second top interconnect structure 218, the first top conductive structure 228, and the second top conductive structure 230, and forming a second dielectric layer (e.g., a back-end dielectric layer 224) including forming the second dielectric layer in the region of the semiconductor die previously occupied by the patterned masking layer 310.

[0175] In the fourth embodiment, forming the first top interconnect structure 218, either alone or in combination with one or more of the first to third embodiments, includes forming the first top interconnect structure 218 in the first recess 302 such that the first top interconnect structure rests on a metallization layer (e.g., conductive structure 214) exposed in the first recess 302.

[0176] In the fifth embodiment, forming the second top interconnect structure 218 alone or in combination with one or more of the first to fourth embodiments includes forming the second top interconnect structure 218 in the second recess 304 such that the second top interconnect structure 218 rests on a third dielectric layer (e.g., another back-end dielectric layer 210) below the first dielectric layer (e.g., the back-end dielectric layer 210).

[0177] although Figure 8 The instance block of process 800 is shown, but in some implementations, process 800 includes... Figure 8 The blocks depicted in the diagram can be compared to more blocks, fewer blocks, different blocks, or blocks with different configurations. Alternatively, two or more blocks in process 800 can be executed in parallel.

[0178] In this manner, the semiconductor die includes top conductive structures of varying sizes, and the bonding vias and associated bonding pads are formed only on the larger top conductive structure. Forming the bonding vias on the larger top conductive structure results in a smaller vertical dimension (e.g., a smaller length) of the bonding vias in the semiconductor die, which reduces the amount of narrowing that occurs in the width of the bonding vias. Specifically, the larger top conductive structure in the semiconductor die can be taller than the smaller top conductive structure in the semiconductor die, and thus reduces the vertical distance the bonding vias span in the semiconductor die, further reducing the amount of narrowing that occurs in the width of the bonding vias. This results in a larger surface area contact between the bottom of the bonding via and the underlying top conductive structure (e.g., the larger top conductive structure), thereby enabling a low contact resistance between the bonding via and the underlying upper conductive structure.

[0179] As described in more detail above, some embodiments described herein provide a semiconductor die. The semiconductor die includes a back-end dielectric layer. The semiconductor die includes a bonding dielectric layer over the back-end dielectric layer. The semiconductor die includes a metallization layer in the back-end dielectric layer, the metallization layer including a first top conductive structure having a first width and a second top conductive structure having a second width greater than the first width. A first top surface of the first top conductive structure is in solid contact with the back-end dielectric layer. The semiconductor die includes a bonding via that is in solid contact with the second top surface of the second top conductive structure. The semiconductor die includes a bonding pad that is in solid contact with the bonding via.

[0180] In some implementations, the ratio of the second width to the first width is in the range of 2.5:1 to 10.66:1.

[0181] In some embodiments, the first thickness of the first top conductive structure is less than the second thickness of the second top conductive structure.

[0182] In some embodiments, the semiconductor die further includes a first top interconnect structure, a second top interconnect structure, and a plurality of third top conductive structures. The first top interconnect structure is below and coupled to the first top conductive structure. The second top interconnect structure is below and coupled to the second top conductive structure. The third top conductive structure is below and coupled to the first top interconnect structure, and coupled to an integrated circuit device in the device layer of the semiconductor die.

[0183] In some embodiments, the semiconductor die further includes a plurality of fourth top conductive structures below and coupled to the second top interconnect structure, wherein one or more of the fourth top conductive structures are coupled to one or more of the third top conductive structures.

[0184] In some embodiments, the semiconductor die further includes a plurality of fourth top conductive structures, which are below and coupled to the second top interconnect structure and to another integrated circuit device in the device layer of the semiconductor die.

[0185] In some embodiments, the semiconductor die further includes a connection structure connecting the first top conductive structure and the second top conductive structure.

[0186] As described in more detail above, some embodiments described herein provide a stacked semiconductor device. The stacked semiconductor device includes a first semiconductor die. The first semiconductor die includes a first back-end dielectric layer, a first bonding dielectric layer above the first back-end dielectric layer, and a first metallization layer in the first back-end dielectric layer. The first metallization layer includes a first top conductive structure having a first width and a second top conductive structure having a second width greater than the first width. A first top surface of the first top conductive structure is in solid contact with the first back-end dielectric layer. The first semiconductor die includes a first bonding via that is in solid contact with the second top surface of the second top conductive structure and a first bonding pad that is in solid contact with the first bonding via. The stacked semiconductor device includes a second semiconductor die bonded to the first semiconductor die such that the first semiconductor die and the second semiconductor die are perpendicularly disposed in the stacked semiconductor device. The second semiconductor die includes a second back-end dielectric layer, a second bonding dielectric layer below the second back-end dielectric layer, and a second metallization layer in the second back-end dielectric layer. The second metallization layer includes a third top conductive structure. The second semiconductor die includes a second bonding via that contacts the third top surface of the third top conductive structure and a second bonding pad that contacts the second bonding via. The first bonding pad of the first semiconductor die and the second bonding pad of the second semiconductor die are bonded by metal-to-metal bonding, and the first bonding dielectric layer of the first semiconductor die and the second bonding dielectric layer of the second semiconductor die are bonded by dielectric-to-dielectric bonding.

[0187] In some embodiments, the second semiconductor die further includes a fourth top conductive structure. The third top conductive structure has a third width, and the fourth top conductive structure has a fourth width that is smaller than the third width.

[0188] In some embodiments, multiple portions of each of the first rear-end dielectric layer, the second rear-end dielectric layer, the first bonding dielectric layer, and the second bonding dielectric layer are directly between the first top conductive structure and the fourth top conductive structure, and the first bonding via, the second bonding via, the first bonding pad, and the second bonding pad are directly between the second top conductive structure and the third top conductive structure.

[0189] In some implementations, the entire fourth top surface of the fourth top conductive structure is in contact with the second rear dielectric layer.

[0190] In some embodiments, the second semiconductor die further includes a third bonding via and a third bonding pad. The third bonding via is in solid contact with the fourth top surface of the fourth top conductive structure. The third bonding pad is in solid contact with the third bonding via.

[0191] In some embodiments, multiple portions of each of the first rear dielectric layer and the first bonding dielectric layer are directly between the first top conductive structure and the third bonding pad.

[0192] In some embodiments, the second top surface of the second top conductive structure is closer to the second bonding dielectric layer than the first top surface of the first top conductive structure.

[0193] As described in more detail above, some embodiments described herein provide a method of forming a semiconductor device. The method of forming a semiconductor device includes forming a first trench and a second trench in a first dielectric layer on a substrate of a semiconductor die. The method of forming a semiconductor device includes forming a patterned masking layer on the first dielectric layer such that the first trench and the second trench are exposed via the patterned masking layer, wherein a first width of a first opening in the patterned masking layer on the first trench is smaller than a second width of a second opening in the patterned masking layer on the second trench. The method of forming a semiconductor device includes forming a first top interconnect structure in the first trench through the first opening in the patterned masking layer, and forming a first top conductive structure on the first top interconnect structure. The method of forming a semiconductor device includes forming a second top interconnect structure in a second trench through a second opening in the patterned masking layer, and forming a second top conductive structure on the second top interconnect structure. The method of forming a semiconductor device includes forming a second dielectric layer on the first dielectric layer such that the second dielectric layer encapsulates the first top conductive structure and the second top conductive structure. The method of forming a semiconductor device includes forming a third trench through the second dielectric layer to the second top conductive structure. A method of forming a semiconductor device includes forming a bonding via on a second top conductive structure in a third recess in the second dielectric layer while the first top conductive structure is encapsulated by a second dielectric layer. Another method of forming a semiconductor device includes forming a bonding pad on the bonding via while the first top conductive structure is encapsulated by a second dielectric layer.

[0194] In some embodiments, the method of forming a semiconductor device further includes: forming a bonding dielectric layer on a second dielectric layer; and forming a fourth groove in the bonding dielectric layer. The step of forming a bonding pad includes: forming a bonding pad on a bonding via in the fourth groove of the bonding dielectric layer.

[0195] In some embodiments, the step of forming the first top conductive structure includes forming the first top conductive structure to a first height. The step of forming the second top conductive structure includes forming the second top conductive structure to a second height greater than the first height.

[0196] In some embodiments, the method of forming a semiconductor device further includes removing a patterned masking layer after forming a first top interconnect structure, a second top interconnect structure, a first top conductive structure, and a second top conductive structure. The step of forming a second dielectric layer includes forming the second dielectric layer in a region of the semiconductor die previously occupied by the patterned masking layer.

[0197] In some embodiments, the step of forming the first top interconnect structure includes: forming the first top interconnect structure in a first groove such that the first top interconnect structure rests on a metallization layer exposed in the first groove.

[0198] In some embodiments, the step of forming the second top interconnect structure includes: forming the second top interconnect structure in the second groove such that the second top interconnect structure rests on a third dielectric layer below the first dielectric layer.

[0199] As described in more detail above, some embodiments described herein provide a stacked semiconductor device. A stacked semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first back-end dielectric layer, a first bonding dielectric layer, a first metallization layer, a first bonding via, and a first bonding pad. The first bonding dielectric layer is above the first back-end dielectric layer. The first metallization layer, within the first back-end dielectric layer, includes a first top conductive structure. The first bonding via is in solid contact with a first top surface of the first top conductive structure. The first bonding pad is in solid contact with the first bonding via. The second semiconductor die is bonded to the first semiconductor die and includes a second back-end dielectric layer, a second bonding dielectric layer, a second metallization layer, a second bonding via, and a second bonding pad. The second bonding dielectric layer is below the second back-end dielectric layer. The second metallization layer, within the second back-end dielectric layer, includes a second top conductive structure and a third top conductive structure. The second top conductive structure has a second width, wherein the entire second top surface of the second top conductive structure is in solid contact with the second back-end dielectric layer. The third top conductive structure has a third width greater than the second width, wherein the second thickness of the second top conductive structure is less than the third thickness of the third top conductive structure. The second bonding via is in solid contact with the third top surface of the third top conductive structure. The second bonding pad is in solid contact with the second bonding via.

[0200] In some embodiments, the first semiconductor die further includes a fourth top conductive structure. The first top conductive structure has a first width, and the fourth top conductive structure has a fourth width, which is smaller than the first width.

[0201] In some embodiments, the first semiconductor die further includes a first top interconnect structure. The first top interconnect structure is located below and coupled to the first top conductive structure.

[0202] The terms “approximately” and “substantially” can refer to a given quantity of value that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of a given quantity of value.

[0203] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor die, characterized in that, Include: One back-end dielectric layer; A bonding dielectric layer is placed on top of the rear dielectric layer; A metallization layer, comprising, in the back-end dielectric layer: A first top conductive structure having a first width, Wherein an entire first top surface of the first top conductive structure is in contact with the rear dielectric layer solid; and A second top conductive structure having a second width greater than the first width; A through-hole is in solid contact with a second top surface of the second top conductive structure; and A bonding pad contacts the bonding through-hole body.

2. The semiconductor die as described in claim 1, characterized in that, Further includes: A first top interconnect structure, below and coupled to the first top conductive structure; A second top interconnect structure is located below and coupled to the second top conductive structure; and Multiple third top conductive structures are located below and coupled to the first top interconnect structure, and coupled to an integrated circuit device in a device layer of the semiconductor die.

3. The semiconductor die as described in claim 2, characterized in that, Further includes: Multiple fourth top conductive structures are located below and coupled to the second top interconnect structure. One or more of the plurality of fourth top conductive structures are coupled to one or more of the plurality of third top conductive structures.

4. The semiconductor die as described in claim 2, characterized in that, Further includes: Multiple fourth top conductive structures are located below and coupled to the second top interconnect structure, and coupled to another integrated circuit device in the device layer of the semiconductor die.

5. A stacked semiconductor device, characterized in that, Include: A first semiconductor die, comprising: A first back-end dielectric layer; A first bonding dielectric layer is disposed on the first rear dielectric layer; A first metallization layer, in the first rear dielectric layer, comprising: A first top conductive structure having a first width, Wherein an entire first top surface of the first top conductive structure is in contact with the first rear dielectric layer solid; and A second top conductive structure having a second width greater than the first width; A first bonding through-hole is in solid contact with a second top surface of the second top conductive structure; and A first engagement gasket contacts the first engagement through-hole body; and A second semiconductor die, bonded to the first semiconductor die, such that the first semiconductor die and the second semiconductor die are perpendicularly disposed in the stacked semiconductor device, comprising: A second back-end dielectric layer; A second bonding dielectric layer is located below the second rear dielectric layer; A second metallization layer, wherein a third top conductive structure is included in the second rear dielectric layer; A second bonding through-hole is in solid contact with a third top surface of the third top conductive structure; and A second mating gasket contacts the second mating through-hole body. The first bonding pad of the first semiconductor die and the second bonding pad of the second semiconductor die are bonded by a metal-to-metal bonding process. The first bonding dielectric layer of the first semiconductor die and the second bonding dielectric layer of the second semiconductor die are bonded by a dielectric-to-dielectric bonding.

6. The stacked semiconductor device as claimed in claim 5, characterized in that, The second semiconductor die further includes a fourth top conductive structure; The third top conductive structure has a third width; and The fourth top conductive structure has a fourth width that is smaller than the third width.

7. The stacked semiconductor device as claimed in claim 5 or claim 6, characterized in that, The second top surface of the second top conductive structure is closer to the second bonding dielectric layer than the first top surface of the first top conductive structure.

8. A stacked semiconductor device, characterized in that, Include: A first semiconductor die, comprising: A first back-end dielectric layer; A first bonding dielectric layer is disposed on the first rear dielectric layer; A first metallization layer, wherein the first rear dielectric layer includes a first top conductive structure; A first bonding through-hole, in solid contact with a first top surface of the first top conductive structure; and A first mating gasket contacts the first mating through-hole body; and A second semiconductor die, bonded to the first semiconductor die, comprising: A second back-end dielectric layer; A second bonding dielectric layer is located below the second rear dielectric layer; A second metallization layer, comprising, in the second rear dielectric layer: A second top conductive structure having a second width, wherein an entire second top surface of the second top conductive structure is in contact with the second rear dielectric layer solid; and A third top conductive structure having a third width greater than the second width, wherein the second thickness of the second top conductive structure is less than the third thickness of the third top conductive structure; A second bonding through-hole is in solid contact with a third top surface of the third top conductive structure; and A second bonding pad contacts the second bonding through-hole body.

9. The stacked semiconductor device as claimed in claim 8, characterized in that, The first semiconductor grain further comprises: A fourth top conductive structure, wherein the first top conductive structure has a first width, and the fourth top conductive structure has a fourth width smaller than the first width.

10. The stacked semiconductor device as claimed in claim 8 or claim 9, characterized in that, The first semiconductor grain further comprises: A first top interconnect structure, below and coupled to the first top conductive structure.

Images