Normally-closed gallium nitride power device
By designing normally-off gallium nitride power devices with compatible pin orders and series ferrite beads, the incompatibility between D-mode gallium nitride devices and silicon-based MOSFETs was solved, achieving high-frequency harmonic suppression and drive signal stability, and reducing packaging costs and development cycles.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN FM ELECTRONICS GRP CO LTD
- Filing Date
- 2025-06-04
- Publication Date
- 2026-04-24
AI Technical Summary
Existing D-mode gallium nitride devices are incompatible with traditional silicon-based MOSFETs. The high switching speed requires high anti-interference capability of the driver IC, and existing driver circuits cannot effectively suppress high-frequency harmonics and balance EMI with drive signal integrity.
Design a normally-off gallium nitride power device with a pin order compatible with mainstream SiMOS/SiC devices. By connecting a ferrite bead in series between the gate and gate pin of a low-voltage silicon-based field-effect transistor, high-frequency harmonics are suppressed and EMI and drive signal integrity are balanced. The switching of the gallium nitride switching transistor is controlled by the low-voltage silicon-based field-effect transistor.
It achieves compatibility with traditional silicon-based devices, shortens the development cycle, reduces packaging costs, can operate normally in extremely high dv/dt environments, and does not require additional filtering circuits, maintaining the stability of the drive signal.
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Figure CN224165121U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, specifically to a normally off gallium nitride power device. Background Technology
[0002] In the existing technology, gallium nitride power devices are gradually replacing traditional silicon-based MOSFETs in the fields of adapters and fast charging power supplies due to their high frequency and high efficiency characteristics. D-mode gallium nitride devices launched by many manufacturers in the industry are generally incompatible with traditional silicon-based MOSFETs. Furthermore, although D-mode gallium nitride devices are theoretically compatible with the driving circuits of traditional silicon MOSFETs, their switching speed (dv / dt) is much higher than that of silicon devices, which places higher demands on the anti-interference capability of the driving IC. Utility Model Content
[0003] The purpose of this invention is to provide a normally-off gallium nitride power device to solve the aforementioned problems. This invention achieves the above objective through the following technical solutions.
[0004] This utility model provides a normally-off gallium nitride power device, including: a base island; a gate pin, a drain pin, and a source pin disposed on the same side of the base island, with the drain pin disposed between the gate pin and the source pin; a gallium nitride switch, the drain of which is connected to the drain pin; a transistor, the drain of which is connected to the source of the gallium nitride switch, and the source of which is connected to the gate and source pins of the gallium nitride switch; and a ferrite bead connected between the gate pin and the gate of the transistor.
[0005] In some embodiments, the gallium nitride switch is connected to the base island via leads, and the base island extends out a drain pin.
[0006] In some embodiments, the normally-off gallium nitride power device further includes: a first ceramic sheet, which is laid flat in a first region of the base island and disposed between the gallium nitride switch and the base island; one side of the gate terminal of the gallium nitride switch is connected to the source terminal pin through a lead; the other side of the gate terminal of the gallium nitride switch is attached to the first ceramic sheet; the drain terminal of the gallium nitride switch is connected to the base island through a lead; and the first ceramic sheet is connected to the source terminal pin through a lead.
[0007] In some embodiments, the normally-off gallium nitride power device further includes: a second ceramic sheet, which is laid flat in a second region of the base island and disposed between the transistor and the base island; the first region and the second region are disposed adjacent to each other; the drain terminal of the transistor is attached to the second ceramic sheet; the source terminal of the transistor is connected to the source terminal pin through a lead; and the second ceramic sheet is connected to the source terminal of the gallium nitride switch through a lead.
[0008] In some embodiments, the normally-off gallium nitride power device further includes: a third ceramic sheet, which is laid flat in a third region of the base island, a first bonding region of a magnetic bead is bonded to the third ceramic sheet, and the third ceramic sheet is connected to the gate terminal of a transistor via a lead; a fourth ceramic sheet, which is laid flat in a fourth region of the base island, a second bonding region of a magnetic bead is bonded to the fourth ceramic sheet, and the fourth ceramic sheet is connected to the gate terminal pin via a lead; the first ceramic sheet, the second ceramic sheet, the third ceramic sheet, and the fourth ceramic sheet do not overlap.
[0009] In some embodiments, the second region is located between the first region and the third region.
[0010] In some embodiments, the third region and the fourth region are located on one side of the second region, the gate pin is located on one side of the drain pin, the first region is located on the other side of the second region, and the source pin is located on the other side of the drain pin.
[0011] In some embodiments, the first ceramic sheet, the second ceramic sheet, the third ceramic sheet, and the fourth ceramic sheet are all direct-bonded ceramic sheets with aluminum nitride as the substrate material and copper foil.
[0012] In some embodiments, the transistor is a low-voltage silicon-based field-effect transistor.
[0013] In some embodiments, the gallium nitride switch is a normally open depletion-mode switch.
[0014] Compared to existing technologies, the normally-off gallium nitride power device provided in this embodiment has a pin order that is fully compatible with mainstream SiMOS / SiC devices, eliminating the need to redesign the PCB or packaging framework. This allows for direct replacement of existing MOSFETs, shortening the development cycle and reducing packaging costs. A ferrite bead is connected in series between the gate and gate pin of the low-voltage silicon-based field-effect transistor to suppress high-frequency harmonics, balance EMI and drive signal integrity, eliminate drive signal oscillations caused by cascaded GaN high-speed switching, and avoid additional filtering circuits. At the same time, it can operate normally in extremely high dv / dt environments and requires only a low voltage for control, without the need for external circuitry. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of a normally-off gallium nitride power device provided in this embodiment;
[0017] Figure 2 This is a schematic diagram of the electrical connection of a normally off gallium nitride power device provided in this embodiment. Detailed Implementation
[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.
[0019] The term "coupled" or "connected" in this invention includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through switches, follower circuits, or other circuits or components.
[0020] Please see Figure 1 This utility model provides a normally-off gallium nitride (GaN) power device, comprising: a base island S; a gate pin P_G, a drain pin P_D, and a source pin P_S disposed on the same side of the base island S, with the drain pin P_D disposed between the gate pin P_G and the source pin P_S; a gallium nitride switch M, the drain of which is connected to the drain pin P_D; a transistor N, the drain of which is connected to the source of the gallium nitride switch M, and the source of which is connected to the gate of the gallium nitride switch M and the source pin P_S; and a ferrite bead L, which is connected between the gate pin P_G and the gate of the transistor N.
[0021] In this embodiment, the normally-off gallium nitride power device can be a chip that has undergone wire bonding and packaging, such as... Figure 1 As shown, the drain pin P_D, gate pin P_G, and source pin P_S of the chip are all located on the same side of the chip, and the drain pin P_D is located between the gate pin P_G and the source pin P_S.
[0022] In this embodiment, the drain of the gallium nitride (GaN) switch M is connected to its drain pin P_D, the gate of GaN switch M is connected to its source pin P_S and the source of transistor N, the source of GaN switch M is connected to the drain of transistor N, and the source of transistor N is connected to its source pin P_S. A ferrite bead L is connected between the gate pin P_G and the gate of transistor N. The electrical connections of the GaN switch M, transistor N, and ferrite bead L are as follows: Figure 2 As shown.
[0023] In this embodiment, the gallium nitride switch M, the transistor N, and the ferrite bead L can be regarded as three independent wafers inside the package, which are electrically connected to each other through a conductive medium to realize the circuit function.
[0024] In this embodiment, the gallium nitride (GaN) switch M can be a normally open depletion-mode switch. The transistor N can be a low-voltage silicon-based field-effect transistor (SDFET). Through the cascaded connection between the GaN and the SFET, the switching of the SFET drives the GaN switch (power device) to become a normally closed switch. During the control process, the conventional SFET drive circuit is used to control the GaN switch M to turn on / off at a lower voltage level.
[0025] In this embodiment, the normally-off gallium nitride power device provided in this embodiment is adopted. The pin order of this power device is fully compatible with mainstream SiMOS / SiC devices, and there is no need to redesign the PCB or packaging framework. This allows it to directly replace existing MOSFETs, shorten the development cycle, and reduce packaging costs. A ferrite bead L is connected in series between the gate and gate pin P_G of the low-voltage silicon-based field-effect transistor to suppress high-frequency harmonics, balance EMI and drive signal integrity, eliminate drive signal oscillation caused by cascaded GaN high-speed switching, avoid additional filtering circuits, and can work normally in extremely high dv / dt environments. It only requires a low voltage for control and does not require external circuitry.
[0026] In some embodiments, such as Figure 1 As shown, the gallium nitride switch M can be connected to the base island S via a lead, and the base island S extends the drain pin P_D.
[0027] In some embodiments, such as Figure 1 As shown, the normally-off gallium nitride power device may further include: a first ceramic sheet J1, which is laid flat in a first region of the base island S and disposed between the gallium nitride switch M and the base island S. One side of the gate terminal of the gallium nitride switch M is connected to the source terminal pin P_S through a lead, the other side of the gate terminal of the gallium nitride switch M is attached to the first ceramic sheet J1, the drain terminal of the gallium nitride switch M is connected to the base island S through a lead, and the first ceramic sheet J1 is connected to the source terminal pin P_S through a lead.
[0028] like Figure 1 As shown, the drain terminal of the gallium nitride (GaN) switch M can have multiple drain PADs, which are connected to the base island S via leads. One side of the gate terminal of the GaN switch M is connected to the source pin P_S via a lead, and the other side of the gate terminal of the GaN switch M is attached to the first ceramic plate J1. The first ceramic plate J1 is connected to the source pin P_S via a lead. At this time, the other side of the gate terminal of the GaN switch M is connected to the source pin P_S via the first ceramic plate J1.
[0029] In some embodiments, such as Figure 1 As shown, the normally off gallium nitride power device may further include: a second ceramic sheet J2, which is laid flat in the second region of the base island S and disposed between the transistor N and the base island S. The first region and the second region are disposed adjacent to each other. The drain terminal of the transistor N is attached to the second ceramic sheet J2. The source terminal of the transistor N is connected to the source terminal pin P_S through a lead. The second ceramic sheet J2 is connected to the source terminal of the gallium nitride switch M through a lead.
[0030] like Figure 1 As shown, the source terminal of the gallium nitride switch M can have multiple source PADs, which are connected to the second ceramic plate J2 via leads. Similarly, the source terminal of transistor N can have multiple source PADs, which are connected to the source pin P_S via leads. The drain terminal of transistor N can be located on the back side of the source terminal of transistor N, which is in contact with the second ceramic plate J2.
[0031] In some embodiments, such as Figure 1 As shown, the normally-off gallium nitride power device may further include: a third ceramic sheet J3, which is laid flat in the third region of the base island S, the first bonding region of the magnetic bead L is bonded to the third ceramic sheet J3, and the third ceramic sheet J3 is connected to the gate terminal of the transistor N through a lead; a fourth ceramic sheet J4, which is laid flat in the fourth region of the base island S, the second bonding region of the magnetic bead L is bonded to the fourth ceramic sheet J4, and the fourth ceramic sheet J4 is connected to the gate terminal pin P_G through a lead; the first ceramic sheet J1, the second ceramic sheet J2, the third ceramic sheet J3, and the fourth ceramic sheet J4 do not intersect each other.
[0032] In some embodiments, the second region may be located between the first region and the third region.
[0033] In some embodiments, the third region and the fourth region are located on one side of the second region, the gate pin is located on one side of the drain pin, the first region is located on the other side of the second region, and the source pin is located on the other side of the drain pin.
[0034] In some embodiments, the third region may be parallel to the fourth region, and the third region and the fourth region may be the same size.
[0035] In some embodiments, the first ceramic sheet J1, the second ceramic sheet J2, the third ceramic sheet J3, and the fourth ceramic sheet J4 are all direct-bonded ceramic sheets with aluminum nitride as the substrate material and copper foil.
[0036] In this embodiment, the first ceramic sheet J1, the second ceramic sheet J2, the third ceramic sheet J3, and the fourth ceramic sheet J4 can all be conductive at the bottom and top layers, with the middle layer being insulating.
[0037] In this embodiment, the third ceramic sheet J3 and the fourth ceramic sheet J4 are provided to isolate the magnetic bead L from the driving signal and prevent crosstalk. The transistor N chip is carried by the second ceramic sheet J2 and heats up directly through the bottom copper layer. The gallium nitride switch M chip is carried by the first ceramic sheet J1. The large area of copper plating reduces thermal resistance, achieves electrical isolation and centralized heat dissipation, and reduces temperature rise.
[0038] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.
Claims
1. A normally-off gallium nitride power device, characterized by, include: Base Island; The gate pin, drain pin, and source pin are disposed on the same side of the base island, with the drain pin disposed between the gate pin and the source pin; A gallium nitride switch, the drain terminal of which is connected to the drain pin; A transistor, the drain of which is connected to the source of the gallium nitride switch, and the source of which is connected to the gate of the gallium nitride switch and the source pin. A magnetic bead is connected between the gate pin and the gate of the transistor.
2. The normally-off gallium nitride power device of claim 1, wherein, The gallium nitride switch is connected to the base island via a lead, and the base island extends the drain pin.
3. The normally-off gallium nitride power device of claim 1, wherein, Also includes: A first ceramic sheet is laid flat in a first region of the base island and disposed between the gallium nitride switch and the base island. One side of the gate terminal of the gallium nitride switch is connected to the source terminal pin through a lead, and the other side of the gate terminal of the gallium nitride switch is attached to the first ceramic sheet. The drain terminal of the gallium nitride switch is connected to the base island through a lead, and the first ceramic sheet is connected to the source terminal pin through a lead.
4. The normally-off gallium nitride power device of claim 3, wherein, Also includes: The second ceramic plate is laid flat in the second region of the base island and disposed between the transistor and the base island. The first region and the second region are disposed adjacent to each other. The drain terminal of the transistor is attached to the second ceramic plate. The source terminal of the transistor is connected to the source terminal pin through a lead. The second ceramic plate is connected to the source terminal of the gallium nitride switch through a lead.
5. The normally-off gallium nitride power device of claim 4, wherein, Also includes: The third ceramic sheet is laid flat in the third region of the base island, the first bonding area of the magnetic bead is bonded to the third ceramic sheet, and the third ceramic sheet is connected to the gate terminal of the transistor through a lead wire. A fourth ceramic sheet is laid flat in the fourth region of the base island, and the second bonding area of the magnetic bead is bonded to the fourth ceramic sheet. The fourth ceramic sheet is connected to the gate pin through a lead wire. The first ceramic sheet, the second ceramic sheet, the third ceramic sheet, and the fourth ceramic sheet do not overlap.
6. The normally-off gallium nitride power device of claim 5, wherein, The second region is located between the first region and the third region.
7. The normally-off gallium nitride power device of claim 6, wherein, The third region and the fourth region are located on one side of the second region, the gate pin is located on one side of the drain pin, the first region is located on the other side of the second region, and the source pin is located on the other side of the drain pin.
8. The normally-off gallium nitride power device of claim 5, wherein, The first ceramic sheet, the second ceramic sheet, the third ceramic sheet, and the fourth ceramic sheet are all direct-bonded ceramic sheets with aluminum nitride as the substrate material and copper foil.
9. The normally-off gallium nitride power device of claim 1, wherein, The transistor is a low-voltage silicon-based field-effect transistor.
10. The normally-off gallium nitride power device of claim 1, wherein, The gallium nitride switch is a normally open depletion-type switch.