Anti-interference low-delay conference unit and digital conference system

Abstract

The utility model relates to an anti-interference low-delay conference unit and a digital conference system. The anti-interference low-delay conference unit comprises a network signal transceiving unit, a digital signal processing module, an audio encoding and decoding module and an audio control module, the audio control module is connected with the digital signal processing module through an SPI bus and GPIO, the audio coding and decoding module is connected with the audio control module through an I2C interface, and the digital signal processing module is connected with the digital signal processing module through I2S. The network signal transmit-receive unit is connected with the digital signal processing module through a standard MII bus, and the network signal transmit-receive unit is connected to the digital conference system through a general network cable. The digital signal processing module provided by the utility model can ensure that the transmission delay of digital audio signals among the conference units is very short, thereby ensuring the fluency and clarity of the conference, and effectively improving the conference efficiency.

Description

Technical Field

[0001] This utility model relates to the technical field of digital conference systems, and more specifically, to an anti-interference, low-latency conference unit and a digital conference system. Background Technology

[0002] With the widespread application of digital conferencing systems in various scenarios, the performance requirements for conferencing units are becoming increasingly stringent. Traditional digital conferencing systems suffer from numerous problems in audio signal transmission, such as signal interference, significant transmission delays, and poor sound quality. These issues severely impact the fluency and clarity of meetings, reducing meeting efficiency. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an anti-interference, low-latency conference unit and digital conference system, addressing the problems existing in the prior art.

[0004] The technical solution adopted by this utility model to solve its technical problem is: to construct an anti-interference and low-latency conference unit, including: a network signal transceiver unit, a digital signal processing module, an audio encoding and decoding module, and an audio control module;

[0005] The audio control module is connected to the digital signal processing module via SPI bus and GPIO. The audio codec module is connected to the audio control module via I2C interface. The digital signal processing module is connected to the digital signal processing module via I2S. The network signal transceiver unit is connected to the digital signal processing module via standard MII bus, and the network signal transceiver unit uses a general-purpose network cable to access the digital conferencing system.

[0006] The network signal transceiver unit is used to perform data transmission between the digital signal processing module and the host in the digital conferencing system;

[0007] The digital signal processing module is used to parse the frame signal transmitted through the network signal transceiver unit to obtain audio signals and control signals, and to transmit the acquired digital audio and / or SPI control commands back to the host through the network signal transceiver unit.

[0008] The audio control module is used to perform audio adjustment control according to the control signal, and to send the SPI control command to the digital signal processing module via the SPI bus;

[0009] The audio codec module is used to decode the audio signal to generate an analog signal to drive the speaker.

[0010] In the anti-interference and low-latency conferencing unit of this utility model, the network signal transceiver unit includes: a first network signal transceiver module and a second network signal transceiver module;

[0011] In the chain structure, the first network signal transceiver module is used to perform the uplink data transmission function, and the second network signal transceiver module is used to perform the downlink data transmission function.

[0012] In the ring structure, the first network signal transceiver module and the second network signal transceiver module are redundantly designed.

[0013] In the anti-interference and low-latency conference unit of this utility model, the digital signal processing module includes: a digital signal processor;

[0014] The digital signal processor is connected to the network signal transceiver unit via a standard MII interface and is used to perform frame signal transmission and reception and MAC layer management.

[0015] The digital signal processor is connected to the audio control module via SPI bus and GPIO respectively, and is used to perform status information control and monitoring of the conference unit.

[0016] In the anti-interference and low-latency conference unit of this utility model, the digital signal processor includes: a system master clock circuit and a high-precision audio clock circuit;

[0017] The system master clock circuit is used to synchronize the internal clock of the digital signal processor;

[0018] The high-precision audio clock circuit is used to generate a 48kHz sampling clock through frequency division.

[0019] In the anti-interference and low-latency conference unit of this utility model, the audio control module includes: an audio controller;

[0020] The audio controller is connected to the audio codec module via an I2C interface, and is also connected to the digital signal processing module via an SPI bus and GPIO. The audio controller is used to perform audio equalization adjustment, gain control, and status monitoring.

[0021] In the anti-interference and low-latency conferencing unit of this utility model, the audio codec module includes: an audio codec;

[0022] The audio codec is connected to the digital signal processing module via I2S and MSCLK, and to the audio control module via I2C, for decoding the audio signal to drive the speaker.

[0023] The anti-interference, low-latency conference unit of this utility model also includes: a power supply module;

[0024] The power module provides power to the network signal transceiver unit, the digital signal processing module, the audio codec module, and the audio control module.

[0025] The anti-interference and low-latency conference unit of this utility model further includes: an external device interface module connected to the audio control module;

[0026] The audio control module is connected to external audio devices through the external device interface module.

[0027] This utility model also provides a digital conferencing system, including: a host and at least one of the above-mentioned interference-resistant and low-latency conferencing units; the host communicates with the interference-resistant and low-latency conferencing units through a network signal transceiver unit.

[0028] The digital conferencing system described in this utility model includes multiple anti-interference and low-latency conferencing units;

[0029] Multiple anti-interference, low-latency conference units are connected to the host in a chain-like cascade manner via a general network;

[0030] Alternatively, multiple anti-interference, low-latency conference units can be connected to the host in a ring structure via a general network in a daisy-chain manner.

[0031] The anti-interference, low-latency conference unit and digital conference system of this invention have the following beneficial effects: It includes a network signal transceiver unit, a digital signal processing module, an audio codec module, and an audio control module. The audio control module is connected to the digital signal processing module via SPI bus and GPIO. The audio codec module is connected to the audio control module via I2C interface. The digital signal processing module is connected to the digital signal processing module via I2S. The network signal transceiver unit is connected to the digital signal processing module via a standard MII bus, and the network signal transceiver unit uses a universal network cable to access the digital conference system. The digital signal processing module of this invention ensures extremely short transmission delays of digital audio signals between conference units, guaranteeing the smoothness and clarity of the conference and effectively improving conference efficiency. Attached Figure Description

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0033] Figure 1 This is a schematic block diagram of an embodiment of the anti-interference and low-latency conference unit provided by this utility model;

[0034] Figure 2 This is a schematic diagram of the power supply tree of an embodiment of the power supply module provided by this utility model;

[0035] Figure 3 This is a circuit diagram of an embodiment of the digital signal processing module provided by this utility model;

[0036] Figure 4 This is a circuit diagram of an embodiment of the first network signal transceiver module provided by this utility model;

[0037] Figure 5 This is a circuit diagram of an embodiment of the second network signal transceiver module provided by this utility model;

[0038] Figure 6 This is a circuit diagram of an embodiment of the audio control module provided by this utility model;

[0039] Figure 7 This is a circuit diagram of an embodiment of the audio codec module provided by this utility model;

[0040] Figure 8 This is a circuit diagram of an embodiment of the peripheral circuit of the digital signal processor provided by this utility model;

[0041] Figure 9 This is a topology diagram of an embodiment of the digital conferencing system provided by this utility model;

[0042] Figure 10 This is a topology diagram of another embodiment of the digital conference system provided by this utility model. Detailed Implementation

[0043] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0044] To address issues such as signal interference, transmission delay, and poor audio quality in existing digital conferencing systems, this invention provides an anti-interference, low-latency conferencing unit. This unit integrates a high-performance digital signal processor, an audio codec, uses universal network cable transmission, and incorporates relevant anti-interference circuits to achieve efficient, stable, and high-fidelity audio signal processing and transmission, significantly improving the overall performance of the digital conferencing system.

[0045] refer to Figure 1In a preferred embodiment, the interference-resistant, low-latency conferencing unit includes: a network transceiver unit 10, a digital signal processing module 20, an audio codec module 30, and an audio control module 40. The audio control module 40 is connected to the digital signal processing module 20 via an SPI bus and GPIO. The audio codec module 30 is connected to the audio control module 40 via an I2C interface. The digital signal processing module 20 is connected to the audio codec module 30 via an I2S interface. The network transceiver unit 10 is connected to the digital signal processing module 20 via a standard MII bus, and the network transceiver unit 10 is connected to the digital conferencing system using a standard network cable. The host computer in the digital conferencing system transmits signals to the digital signal processing module 20 through the network transceiver unit 10.

[0046] Specifically, in some embodiments, the network transceiver unit 10 is used to perform data transmission between the digital signal processing module 20 and the host in the digital conferencing system; the digital signal processing module 20 is used to parse the frame signal transmitted through the network transceiver unit 10 to obtain audio signals and control signals, and to package and encapsulate the acquired digital audio and / or SPI control commands and send them back to the host through the network transceiver unit 10; the audio control module 40 is used to perform audio adjustment control according to the control signals, and to send SPI control commands to the digital signal processing module 20 through the SPI bus; the audio codec module 30 is used to decode the audio signal to generate an analog signal to drive the speaker.

[0047] Furthermore, such as Figure 1 As shown, this interference-resistant, low-latency conferencing unit also includes: a power supply module 50 and an external device interface module 60 connected to the audio control module 40. The power supply module 50 provides power to the network signal transceiver unit 10, the digital signal processing module 20, the audio codec module 30, and the audio control module 40. The audio control module 40 is connected to external audio devices via the external device interface module 60.

[0048] Optionally, in some embodiments, the digital signal processing module 20 includes: a digital signal processor U1; the digital signal processor U1 is connected to the network signal transceiver unit 10 via a standard MII interface, and is used to perform frame signal transmission and reception and MAC layer management; the digital signal processor U1 is connected to the audio control module 40 via an SPI bus and GPIO respectively, and is used to perform status information control and monitoring of the conference unit. Further, the digital signal processor U1 includes: a system master clock circuit and a high-precision audio clock circuit; the system master clock circuit is used to synchronize the internal clock of the digital signal processor U1; the high-precision audio clock circuit is used to generate a 48kHz sampling clock through frequency division.

[0049] Specifically, the digital signal processor U1 achieves data interaction between the physical layer and the MAC layer through the MII standard interface. It receives signal frames transmitted from the host via the network transceiver unit 10, verifies and parses the signal frames, and then decodes the extracted I2S audio signal using the audio codec module 30 to obtain an analog signal. The audio codec module 30 then outputs the decoded analog signal to the speaker. The parsed control signal is transmitted to the audio control module 40. Simultaneously, the digital signal processor U1 acquires the analog signal collected by the microphone on the conference unit using 24-bit / 48kHz audio acquisition, and then repackages it into a standard signal frame using the SPI control commands transmitted by the I2S digital audio and audio control modules. This frame is then transmitted back to the host via the network transceiver unit 10. The clock system of this invention can be configured with dual external crystal oscillators. A 25MHz master clock synchronizes the internal clock of the digital signal processing module 20, and a 24.576MHz high-precision audio clock generates a 48kHz sampling clock through frequency division, supporting different sampling rates to ensure audio synchronization accuracy of ±1ppm. The digital signal processor U1 connects to the audio control module 40 via an SPI bus to enable the audio control module 40 to perform equalization (EQ) adjustment, gain control, and status monitoring of the audio signal. Simultaneously, the digital signal processor U1 integrates Flash storage for firmware and configuration parameters, supports firmware upgrades via a JTAG interface, and works with the MCU in the audio control module 40 via a GPIO interface to remotely upgrade the digital signal processing module 20 through the MCU of the audio control module 40. The digital signal processing module 20 of this invention performs signal processing and clock synchronization functions, achieving audio transmission latency of a few milliseconds, effectively solving the problem of audio signal transmission delay. Furthermore, its simple topology allows for flexible adaptation to conference scenarios of different sizes. The digital signal processor U1 of this invention achieves audio stream synchronization through dynamic clock domain management and supports clock locking in hot-swappable mode. The network layer employs a dual buffering mechanism to ensure that the audio transmission latency is consistently below 2ms, and its anti-interference capability meets the 15kV ESD protection standard.

[0050] Optionally, in this embodiment of the present invention, the network signal transceiver unit 10 includes: a first network signal transceiver module 11 and a second network signal transceiver module 12. In a chain structure, the first network signal transceiver module 11 performs uplink data transmission, and the second network signal transceiver module 12 performs downlink data transmission. In a ring structure, the first network signal transceiver module 11 and the second network signal transceiver module 12 are redundantly designed. Specifically, the chain or ring structure of this invention refers to the network transmission architecture of a digital conferencing system. That is, when a digital conferencing system uses multiple conferencing units, these units are cascaded together via a general network to form a network topology. When the last conferencing unit loops back to the digital conferencing system host, the resulting network topology is a ring structure; when the last conferencing unit does not loop back to the digital conferencing system host, the resulting network topology is a chain structure. Figure 9 The diagram shows a chain-like structure. Figure 10 The diagram shows a ring-shaped structure. Figure 9 As shown, in a digital conferencing system, each bus has one master node (i.e., host) among its multiple nodes. The audio service clocks of the other nodes (slave nodes / child nodes) are synchronized with the master node. Each data bus has two directions: uplink and downlink. The uplink direction is from slave node to master node. The downlink direction is from master node to slave node. In a daisy-chain structure, the first network transceiver module 11 performs uplink signal transmission and reception, and the second network transceiver module 12 performs downlink signal transmission and reception; or, the first network transceiver module 11 performs downlink signal transmission and reception, and the second network transceiver module 12 performs uplink signal transmission and reception. Figure 10 As shown, in the ring structure, the uplink and downlink transmission directions can be specified according to the master node port. When the ring structure is interrupted, the uplink and downlink data directions of the link after the lost node automatically switch, and automatically switch back to the ring structure when the link is restored. In the ring structure, the first network signal transceiver module 11 and the second network signal transceiver module 12 are redundantly designed, i.e., they have backup functionality. By designing a chain-type structure / or a ring structure, the fault tolerance capability of a ring network and the low latency characteristics of a chain network can be combined.

[0051] Optionally, in this embodiment of the present invention, the audio control module 40 includes: an audio controller U4; the audio controller U4 is connected to the audio codec module 30 via an I2C interface, and is connected to the digital signal processing module 20 via an SPI bus and GPIO; the audio controller U4 is used to perform audio equalization adjustment, gain control, and status monitoring. This audio controller U4 can not only receive instructions from the upper-level host to precisely regulate and manage system resources, but also convert audio data received via the USB interface into recording files, achieving effective transmission and storage of audio data.

[0052] Optionally, in this embodiment of the present invention, the audio codec module 30 includes: an audio codec U3; the audio codec U3 is connected to the digital signal processing module 20 via I2S and MSCLK, and to the audio control module 40 via I2C, for decoding audio signals to drive the speaker.

[0053] This invention, by employing the audio codec U3, optimizes the audio processing algorithm, effectively eliminating noise and echo interference, and significantly improving audio quality. Simultaneously, in conjunction with the dedicated digital signal processing module 20, it can be connected to ring / chain conference systems via a universal network cable, ensuring extremely short transmission delays of digital audio signals between conference units.

[0054] refer to Figure 2 , Figure 2 This is a schematic diagram of the power supply tree of a preferred embodiment of the power supply module 50. It should be noted that the power supply tree of the power supply module 50 can be implemented in various ways. Figure 2 Only a preferred implementation method has not yet been proposed.

[0055] Specifically, such as Figure 2As shown, in this embodiment, the power module 50 includes: a 12V~24V DC power supply, a DC / DC1 circuit, a DC / DC2 circuit, an LDO1 circuit, an LDO2 circuit, and a control switch. The DC / DC1 and DC / DC2 circuits are both DC-to-DC circuits, and both can be composed of existing conventional circuits; this invention does not impose specific limitations. The LDO1 and LDO2 circuits are both step-down circuits, and both can be composed of existing conventional circuits; this invention does not impose specific limitations. For better control, this invention directly connects a switch across the 12V~24V DC power supply and the DC / DC1 and DC / DC2 circuits for switching control. After passing through the DC / DC1 circuit, the 12V~24V DC power supply outputs a +12V voltage to supply external audio input / output devices. After passing through the DC / DC2 circuit, the 12V~24V DC power supply outputs a +3.3V voltage to supply the digital signal processing module 20, the first network signal transceiver module 11, the second network signal transceiver module 12, the audio signal controller (audio controller U4), the audio codec U3, the LDO1 circuit, and the LDO2 circuit. The LDO1 circuit outputs a +1.2V voltage to supply the digital signal processing module 20. The LDO2 circuit outputs a +1.8V voltage to supply the audio codec U3.

[0056] The principle of the anti-interference and low-latency conference unit of this utility model will be explained below with a specific embodiment.

[0057] like Figure 3 As shown, in a preferred embodiment, the digital signal processor U1 is connected to the network signal transceiver module via a standard MII interface to realize frame signal transmission and reception and MAC layer management. It is also connected to the audio controller U4 via SPI and GPIO to realize unit status information control and monitoring. The 25MHz pin is connected to the crystal oscillator X1 (reference). Figure 8 The pin 24.576MHz is connected to the crystal oscillator Y1 (reference). Figure 8 ) connection, SPI and Flash interface U2 (reference) Figure 8 Connections, JTAG and Debugging Interface J1 (Reference) Figure 8 (Connection) enables the acquisition, processing, and transmission of relevant data.

[0058] Specifically, such as Figure 3As shown, the digital signal processor U1 is electrically connected to the first network transceiver module 11 and the second network transceiver module 12 via MII_RX_CLK, MII_RX_DV, MII_CRS, MII_RX_ER, MII_RXD0~MII_RXD3, MII_COL, MII_TX_CLK, MII_TX_EN, MII_TXD0~MII_TXD3, MII_INT, MII_MDC, and MII_MDIO. It is also electrically connected to the audio control module 40 via SPI_CLK, SPI_MISO, SPI_MOSI, SPI_CS, SPII_MISO, SPII_CLK, MINT, MBUSY, CRST, FRST, FINITB, and FDONE. The digital signal processor (DSP) U1 is electrically connected to the audio codec U3 via pins SCLK, LRCLK, MICLK, SDOUT, and SDIN. Pin 50 of the DSP U1 is the reset pin; to simplify the hardware circuitry, an RC circuit (resistor R1 and capacitor C1) is used for power-on reset of the DSP U1. The DSP U1 is configured with a dual-clock architecture: X1 (25MHz) provides the system master clock, and Y1 (24.576MHz) generates a 48kHz frame clock and bit clock via internal PLL division. These clocks establish a synchronized audio stream with the audio codec U3 through the I2S bus group (SCLK / LRCLK / MICLK / SDOUT / SDIN).

[0059] The digital signal processor U1 receives frame signals transmitted from the host through the network signal transceiver unit 10. After parsing the frame signals, it obtains audio signals and control signals (transmitted to the audio controller U4). It separates the I2S audio stream and transmits it to the audio codec U3 for PCM decoding to generate an analog signal to drive the speaker. Conversely, the digital signal processing module 20 repackages the 24bit / 48kHz digital audio collected by the microphone and the SPI control commands into frames and transmits them back to the host through the MII interface. The system (digital signal processing module 20) achieves audio stream synchronization through dynamic clock domain management, supports clock locking in hot-swappable mode, and the network layer adopts a dual buffering mechanism to ensure that the audio transmission delay is stable below 2ms, with anti-interference capability reaching the 15kV ESD protection standard.

[0060] Figure 4 and Figure 5The diagrams show the circuit schematics of the first network transceiver module 11 and the second network transceiver module 12. Both modules are connected to the digital signal processing module 20 via standard MII signals, a 25MHz clock signal, and a serial management signal, respectively. Their TX- / + and RD- / + connections are connected to the external signal interface J4 (a physical layer interface) to acquire and transmit relevant data for digital frame signals. When the host sends data, the network transceiver module receives data from the MAC, converts the parallel data into a serial stream, encodes it according to 4B / 5B encoding rules, and finally converts it into an analog signal for transmission. The process is reversed when the host receives data.

[0061] Since the first network signal transceiver module 11 and the second network signal transceiver module 12 operate on the same principle, the following explanation will use the first network signal transceiver module 11 as an example. Specifically, as follows... Figure 4 As shown, the first network signal transceiver module 11 includes a network signal transceiver U5, which is electrically connected to the digital signal processor U1 via MII_RX_CLK, MII_RX_DV, MII_CRS, MII_RX_ER, MII_RXD0~MII_RXD3, MII_COL, MII_TX_CLK, MII_TX_EN, MII_TXD0~MII_TXD3, MII_INT, MII_MDC, and MII_MDIO. It is also electrically connected to the external signal connection interface J4 via PHY_TX+, PHY_TX-, PHY_RD+, and PHY_RD- through TVS diodes D7 and D9. Figure 4As shown, the RESET-PHY pin of the network transceiver U5 is the reset pin. The RESET-PHY pin is directly connected to the audio controller U4 to achieve system-wide synchronous reset management, effectively simplifying timing coordination complexity. Pin 34 is the clock pin, which is electrically connected to the external 25MHz crystal clock source of the digital signal processor U1, providing a precise clock reference for the module. The network transceiver U5 is physically connected from the PHY layer through the differential signal lines PHY_RD+, PHY_RD-, PHY_TX+, and PHY_TX- of interface J4, receiving or transmitting analog signals via TVS diodes D7 / D9. The signal anti-interference circuit provides 15kV ESD protection to ensure signal integrity. The network transceiver U5 receives analog signals from an external network cable via interface J4. It then performs Manchester decoding to convert the signals into digital signals, which are uploaded to the digital signal processor U1 via the MII interface for protocol parsing. The transmitting link operates in reverse: data from the digital signal processor U1 is transmitted to the network transceiver U5 via the MII interface. After 4B / 5B encoding and signal modulation, it outputs analog signals conforming to the 100BASE-TX standard through PHY_TX+ / PHY_TX- differential pairs. This design employs a decoupled architecture between the physical layer and the data link layer.

[0062] refer to Figure 6 The audio control module 40 includes an audio controller U4, which is connected to the audio codec U3 via I2C, to the digital signal processor U1 via SPI and GPIO, to the network transceiver U5 / U6 via REST-PHY, to the crystal oscillator X2 via OSC_IN / OUT, to the serial port interface J6 via URAT_RX1 / TX1, and to the debugging interface J3 via JTAG, thereby realizing the acquisition, processing, and transmission of relevant data. Specifically, as shown... Figure 6As shown, pins SCL and SDA are electrically connected to the audio codec U3. Pin RESET-PHY is electrically connected to the network transceiver U5 / U6. Pins SPI_CLK, SPI_MISO, SPI_MOSI, SPI_CS, SPII_MISO, SPII_CLK, MINT, MBUSY, CRST, FRST, FINITB, and FDONE are electrically connected to the digital signal processor U1. Pins 43 and 42 are electrically connected to the serial interface J6. Pins JTAG_SWCLK and JTAG_SWDIO are electrically connected to the debug interface J3. Pins 5 and 6 are connected to the passive crystal oscillator X2, providing the master clock for the audio controller U4. Pin 7 is the reset pin. To simplify the hardware circuit, an RC circuit (resistor R56 and capacitor C19) is used for the power-on reset of the MCU control unit (i.e., audio controller U4). Pins Boot0 and Boot1 are for selecting the programming configuration mode of the MCU control unit, both using pull-down mode. Pin 17 is connected to the negative side of LED D6 through a current-limiting resistor R65 to realize the indicator light function of the MCU control unit. Pin 25 is connected to button K1 so that when a button is pressed in each conference unit, the audio controller U4 sends a signal (i.e., SPI control command) to the digital signal processor U1 via SPI. The host receives the request from the conference unit through the digital audio bus, issues a command, and uploads it to the digital audio bus.

[0063] like Figure 7 As shown, the audio control module 40 includes an audio codec U3. The audio codec U3 is connected to the digital signal processor U1 via I2S and MSCLK, connected to the audio controller U4 via I2C, connected to the microphone socket via analog input signals, and connected to the headphone socket via analog output signals, thereby realizing the acquisition, processing, and transmission of audio data. Specifically, as... Figure 7As shown, the audio codec U3 is electrically connected to the audio controller U4's pins SCL and SDA via pins CTRL_CLK and CTRL_DATA. It is also electrically connected to the digital signal processor U1's pins SCLK, LRCLK, MICLK, SDOUT, and SDIN via pins SCLK, LRCLK, MICLK, SDOUT, and SDIN. It is electrically connected to the microphone socket via pins MIC_N and MIC_P. The microphone is electrically connected to the microphone via pin MIC_BIAS through an anti-interference and anti-static circuit, and to the headphone socket via pins HP_L and HP_R. The I2S signal format is determined by the bit clock rate and the number of sampling bits. In this invention, the audio codec U3 selects the I2S signal format and 128xFs mode for its audio input / output.

[0064] The audio codec U3 can be flexibly configured with TDM, I2S, and left-right aligned PCM format. Pin 11CPVDD receives a 1.8V power supply from an external LDO power supply. After power-on, the audio controller U4 configures the internal registers of the audio codec U3 via I2C. When an external audio input / output device inputs a raw analog audio signal, it electrically connects to the audio codec U3 via pins MIC_N and MIC_P. Internally, the audio codec U3 performs programmable gain PGA and ADC decoding, converting the signal into an I2S digital signal and transmitting it to the digital signal processor U1. During signal communication between the digital signal processing module 20 and the audio codec U3, the digital signal processor U1 outputs two I2S clock signals—a frame clock and a bit clock—to the audio codec U3 for synchronization of the data stream, enabling the digital signal processor U1 to simultaneously integrate streaming media signals, i.e., I2S input and output signals. The network transceiver U5 / U6 transmits the received MII signal to the digital signal processor U1. After the digital signal processor U1 extracts the audio signal from the frame signal, processes it, and connects it directly to the audio codec U3 for audio output, the audio codec U3 decodes it via the internal DAC in I2S signal format, and then transmits it to the external audio input / output device.

[0065] Compared with the traditional digital signal processor U1, which has high latency, multiple transmission format units, and complex operation, the digital signal processor used in this invention has the advantages of low latency, multiple transmission formats, and simple operation.

[0066] Furthermore, the digital signal processor and network transceiver of this invention, when combined, allow the host of the digital conferencing system to interconnect with external devices via a Dante module (a Dante module typically refers to a hardware module related to Dante audio network technology, used for the digital transmission and processing of audio signals). Moreover, by employing the aforementioned dedicated digital signal processor, this invention features low latency and strong anti-interference capabilities. Simultaneously, the digital signal processor uses a dual-clock domain dynamic coupling method, ensuring clock synchronization accuracy within ±0.5ppm error through phase locking between the 24.576MHz main audio clock and the 25MHz system clock, and supports clock locking in hot-swappable mode, achieving "plug and play" functionality. The network transceiver, through anti-interference circuits such as RC filtering and surge protection circuits, further enhances signal anti-interference capabilities.

[0067] This invention also provides a digital conferencing system. The digital conferencing system includes: a host computer and at least one interference-resistant, low-latency conferencing unit disclosed in this embodiment. The host computer communicates with the interference-resistant, low-latency conferencing unit via a network signal transceiver unit 10.

[0068] Alternatively, in some other embodiments, the digital conferencing system includes multiple interference-resistant, low-latency conferencing units. These multiple interference-resistant, low-latency conferencing units are connected to the host in a daisy-chain cascaded manner via a common network, forming a chain structure, such as... Figure 9 As shown. Alternatively, multiple interference-resistant, low-latency conference units and the host can be cascaded together in a ring structure via a general network. For example... Figure 10 As shown.

[0069] like Figure 9 As shown, in a digital conferencing system, each bus has one master node (i.e., the host) among its multiple nodes. The audio service clocks of the other nodes (slave nodes / child nodes) are synchronized with the master node. Each data bus segment has two directions: uplink and downlink. The uplink direction is from slave node to master node. The downlink direction is from master node to slave node. Figure 10 As shown, in a ring structure, the uplink and downlink transmission directions can be specified according to the master node port. When the ring structure is interrupted, the uplink and downlink data directions of the link after the lost node automatically switch, and automatically switch back to the ring structure when the link is restored. By designing a chain structure / or a ring structure, it is possible to combine the fault tolerance of a ring network with the low latency characteristics of a chain network.

[0070] The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They do not limit the scope of protection of this utility model. All equivalent changes and modifications made within the scope of the claims of this utility model should fall within the scope of the claims of this utility model.

Claims

1. A conference unit with anti-interference and low latency, characterized in that, include: Network signal transceiver unit, digital signal processing module, audio codec module, and audio control module; The audio control module is connected to the digital signal processing module via SPI bus and GPIO. The audio codec module is connected to the audio control module via I2C interface. The digital signal processing module is connected to the digital signal processing module via I2S. The network signal transceiver unit is connected to the digital signal processing module via standard MII bus, and the network signal transceiver unit uses a general-purpose network cable to access the digital conferencing system. The network signal transceiver unit is used to perform data transmission between the digital signal processing module and the host in the digital conferencing system; The digital signal processing module is used to parse the frame signal transmitted through the network signal transceiver unit to obtain audio signals and control signals, and to transmit the acquired digital audio and / or SPI control commands back to the host through the network signal transceiver unit. The audio control module is used to perform audio adjustment control according to the control signal, and to send the SPI control command to the digital signal processing module via the SPI bus; The audio codec module is used to decode the audio signal to generate an analog signal to drive the speaker.

2. The anti-interference, low-latency conference unit according to claim 1, characterized in that, The network signal transceiver unit includes: a first network signal transceiver module and a second network signal transceiver module; In the chain structure, the first network signal transceiver module is used to perform the uplink data transmission function, and the second network signal transceiver module is used to perform the downlink data transmission function. In the ring structure, the first network signal transceiver module and the second network signal transceiver module are redundantly designed.

3. The anti-interference, low-latency conferencing unit according to claim 1, characterized in that, The digital signal processing module includes: a digital signal processor; The digital signal processor is connected to the network signal transceiver unit via a standard MII interface and is used to perform frame signal transmission and reception and PHY layer management. The digital signal processor is connected to the audio control module via SPI bus and GPIO respectively, and is used to perform status information control and monitoring of the conference unit.

4. The anti-interference, low-latency conference unit according to claim 3, characterized in that, The digital signal processor includes: a system master clock circuit and a high-precision audio clock circuit; The system master clock circuit is used to synchronize the internal clock of the digital signal processor; The high-precision audio clock circuit is used to generate a 48kHz sampling clock through frequency division.

5. The anti-interference, low-latency conference unit according to claim 1, characterized in that, The audio control module includes: an audio controller; The audio controller is connected to the audio codec module via an I2C interface, and is also connected to the digital signal processing module via an SPI bus and GPIO. The audio controller is used to perform audio equalization adjustment, gain control, and status monitoring.

6. The anti-interference, low-latency conferencing unit according to claim 1, characterized in that, The audio encoding / decoding module includes: an audio codec; The audio codec is connected to the digital signal processing module via I2S and MSCLK, and to the audio control module via I2C, for decoding the audio signal to drive the speaker.

7. The anti-interference, low-latency conference unit according to any one of claims 1-6, characterized in that, Also includes: Power module; The power module provides power to the network signal transceiver unit, the digital signal processing module, the audio codec module, and the audio control module.

8. The anti-interference, low-latency conference unit according to claim 7, characterized in that, Also includes: An external device interface module connected to the audio control module; The audio control module is connected to external audio devices through the external device interface module.

9. A digital conferencing system, characterized in that, include: The host computer and at least one interference-resistant, low-latency conference unit as described in any one of claims 1-8; the host computer communicates with the interference-resistant, low-latency conference unit via a network signal transceiver unit.

10. The digital conferencing system according to claim 9, characterized in that, Includes multiple anti-interference, low-latency conference units; Multiple anti-interference, low-latency conference units are connected to the host in a chain-like cascade manner via a general network; Alternatively, multiple anti-interference, low-latency conference units can be connected to the host in a ring structure via a general network in a daisy-chain manner.

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