Solar cell, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a solar cell, a cell assembly and a photovoltaic system. The fine grids are arranged on the surface of the silicon substrate, the fine grids are sequentially arranged at intervals in the first direction, each fine grid extends in the second direction, and the second direction intersects with the first direction; wherein at least part of the fine grid comprises at least two sub-fine grid sections which are sequentially arranged at intervals in the second direction, a discontinuous region is arranged between every two adjacent sub-fine grid sections, the discontinuous regions are located in the region, where the welding strip is not welded, of the surface of the silicon substrate, the discontinuous regions are provided with conductive parts, and every two adjacent sub-fine grid sections are connected through the conductive parts. The solar cell provided by the utility model can improve the printing precision of the fine grid, thereby improving the production yield of the solar cell.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, and in particular to a solar cell, a battery module and a photovoltaic system. Background Technology

[0002] With the increasing depletion of fossil fuels, solar energy has become the most widespread and clean renewable energy source. Solar cells, in particular, are devices that directly convert light energy into electrical energy using the photovoltaic effect. Solar cells mainly include bifacial solar cells and back-contact solar cells.

[0003] In related technologies, the surface of solar cells typically requires several fine grids to collect charge carriers. However, the fine grids in the non-welded solder area of ​​a solar cell are usually a continuous, single structure. This results in excessively long fine grids in the non-welded solder area, leading to low grid printing accuracy and affecting the yield of solar cell production. Utility Model Content

[0004] This invention provides a solar cell that aims to solve the problem in existing solar cells where the fine grid is too long in the non-welding strip area, resulting in low printing accuracy of the fine grid and thus affecting the production yield of solar cells.

[0005] This invention is implemented by providing a solar cell, comprising:

[0006] Silicon substrate; and

[0007] A plurality of fine gates are disposed on the surface of the silicon substrate, the plurality of fine gates being arranged sequentially at intervals along a first direction, and each fine gate extending along a second direction intersecting the first direction; wherein, at least a portion of the fine gates include at least two sub-fine gate segments arranged sequentially at intervals along the second direction, and an interruption region is provided between adjacent sub-fine gate segments, the interruption region being located in the non-welded solder strip area on the surface of the silicon substrate, the interruption region being provided with a conductive portion, and adjacent two sub-fine gate segments being connected through the conductive portion.

[0008] Preferably, the conductive portion includes a middle portion and two connecting portions respectively connected to both ends of the middle portion. One connecting portion is connected to one of the two adjacent sub-fine gate segments, and the other connecting portion is connected to the other of the two adjacent sub-fine gate segments. The dimension of the connecting portion along the first direction is greater than the dimension of the middle portion along the first direction.

[0009] Preferably, the connecting portion includes a first end disposed near the middle portion and a second end disposed away from the middle portion, wherein the dimension of the second end in the first direction is greater than the dimension of the first end in the first direction.

[0010] Preferably, the dimension of the connecting portion in the first direction gradually increases from the first end to the second end.

[0011] Preferably, the sub-fine grid segment is connected to the connecting portion, and the sub-fine grid segment extends to the middle portion and is connected to the middle portion.

[0012] Preferably, the ratio of the length of the middle portion to the length of each connecting portion is 2 to 5.

[0013] Preferred options also include:

[0014] A plurality of main gates are disposed on the surface of the silicon substrate, the main gates including a first polar main gate and a second polar main gate that are alternately spaced along the second direction;

[0015] The fine grid includes a plurality of first polar fine grids and a plurality of second polar fine grids. The plurality of first polar fine grids and the plurality of second polar fine grids are arranged alternately and at intervals along the first direction. The first polar fine grids are connected to the first polar main grid, and the second polar fine grids are connected to the second polar main grid.

[0016] At least a portion of the first polar fine gate and / or at least a portion of the second polar fine gate form the discontinuity region in the region where the main gate is not located.

[0017] Preferably, the main gate includes a first main gate located at the edge of the silicon substrate and a second main gate disposed adjacent to the first main gate, and at least a portion of the fine gate forms at least one discontinuity region between the first main gate and the second main gate.

[0018] Preferably, the main grid includes at least two main grid unit segments spaced apart from each other along the first direction, and the fine grids are disposed between adjacent main grid unit segments along the first direction, and the fine grids between adjacent main grid unit segments along the first direction form at least one discontinuity region.

[0019] Preferred options also include:

[0020] A doped layer disposed on the surface of the silicon substrate;

[0021] A passivation layer is disposed on the doped layer, the fine gate passes through the passivation layer and contacts the doped layer, and the conductive portion is located on the passivation layer but does not pass through the passivation layer.

[0022] Preferably, each of the multiple fine grids includes at least two sub-fine grid segments arranged sequentially at intervals along the second direction, and two adjacent sub-fine grid segments of the multiple fine grids are connected by the conductive part, and at least a plurality of the conductive parts are arranged in a row.

[0023] Preferably, the surface of the silicon substrate includes at least two battery regions along the first direction, each battery region is provided with a main gate and a fine gate, an interval region is provided between adjacent battery regions, the main gate in adjacent battery regions is disconnected in the interval region, at least one fine gate is provided in the interval region, and the fine gate in the interval region forms a plurality of discontinuity regions.

[0024] Preferably, the first polar main gate includes a first sub-main gate segment and a second sub-main gate segment spaced apart along the second direction, a first overlapping portion protruding on one side of the first sub-main gate segment, and a second overlapping portion protruding on the other side of the second sub-main gate segment, wherein the first sub-main gate segment and the second sub-main gate segment are spaced apart to form a first gap region;

[0025] The first polar fine grid includes a first unit segment and a second unit segment spaced apart along the second direction. The first unit segment is connected to the first overlapping portion, the second unit segment is connected to the second overlapping portion, and the first unit segment and the second unit segment are spaced apart by the first interval region.

[0026] Preferably, the second polar main gate includes a third sub-main gate segment and a fourth sub-main gate segment spaced apart along the second direction, a third overlapping portion protruding on one side of the third sub-main gate segment, and a fourth overlapping portion protruding on the other side of the fourth sub-main gate segment, wherein the third sub-main gate segment and the fourth sub-main gate segment are spaced apart to form a second interval region.

[0027] The second polar fine grid includes a third unit segment and a fourth unit segment spaced apart along the second direction. The third unit segment is connected to the third overlapping portion, and the fourth unit segment is connected to the fourth overlapping portion. The third unit segment and the fourth unit segment are spaced apart by the second spacing region.

[0028] This invention also provides a battery assembly, including the aforementioned solar cell.

[0029] This utility model also provides a photovoltaic system, including the above-mentioned battery components.

[0030] The solar cell provided by this utility model forms at least one discontinuity region in the non-welded strip area of ​​at least a portion of the fine grids. The fine grids form at least two sub-fine grid segments spaced sequentially along a second direction in the non-welded strip area, and conductive parts are provided in the discontinuity region to connect adjacent sub-fine grid segments. Since the adjacent sub-fine grid segments are independently arranged, the adjacent sub-fine grid segments of the fine grid are discontinuous with each other, which can avoid the fine grids being too long in the non-welded strip area. This allows the fine grids to be printed in segments, which can improve the printing accuracy of the fine grids in the non-welded strip area, thereby improving the production yield of the solar cell. Moreover, the two adjacent sub-fine grid segments are connected by conductive parts, which realizes the conductivity between the two adjacent sub-fine grid segments, thereby achieving good carrier collection between the two sub-fine grid segments. At the same time, the conductive parts can also play a role in fixing the two adjacent sub-fine grid segments, improving the reliability of the sub-fine grid segments fixed on the silicon substrate surface. Attached Figure Description

[0031] Figure 1 A plan view of a solar cell provided for an embodiment of this utility model;

[0032] Figure 2 for Figure 1 A magnified schematic diagram of part A in the middle;

[0033] Figure 3 A schematic diagram of the removal of conductive parts from the fine grid of a solar cell provided in an embodiment of this utility model;

[0034] Figure 4 A schematic diagram of a fine grid conductive portion provided for an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the conductive part of a solar cell provided in an embodiment of this utility model;

[0036] Figure 6 This is a partial structural cross-sectional view of a solar cell provided in an embodiment of the present invention;

[0037] Figure 7 for Figure 1 A magnified schematic diagram of part B in the middle;

[0038] Figure 8 for Figure 1 A magnified schematic diagram of part C in the middle;

[0039] Figure 9 for Figure 1 A magnified schematic diagram of part D in the middle. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present utility model, and should not be construed as limiting the present utility model. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining the present utility model and are not intended to limit the present utility model.

[0041] In the description of this utility model, it should be understood that the terms "upper", "lower", "back", "front", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] The following disclosure provides numerous different embodiments or examples for implementing various structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention; however, those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0044] Please refer to Figures 1-4 The present invention provides a solar cell comprising:

[0045] Silicon substrate 1; and

[0046] A plurality of fine gates 2 are disposed on the surface of a silicon substrate 1, the plurality of fine gates 2 being arranged sequentially at intervals along a first direction Y, and each fine gate 2 extending along a second direction X, the second direction X intersecting the first direction Y; wherein, at least a portion of the fine gates 2 includes at least two sub-fine gate segments 25 arranged sequentially at intervals along the second direction X, and an interruption region 26 is provided between two adjacent sub-fine gate segments 25, the interruption region 26 being located in the non-welded solder strip area on the surface of the silicon substrate 1, and a conductive portion 27 is provided in the interruption region 26, and two adjacent sub-fine gate segments 25 are connected through the conductive portion 27.

[0047] In this embodiment of the invention, the solar cell can be a bifacial solar cell or a back-contact solar cell. When the solar cell is a bifacial solar cell, the surface of the silicon substrate 1 can be the front and back sides of the solar cell, and fine grids 2 can be provided on both the front and back sides of the solar cell. When the solar cell is a back-contact solar cell, the surface of the silicon substrate 1 is the back side of the solar cell, and fine grids 2 are provided on the back side of the solar cell. The several fine grids 2 provided on the surface of the silicon substrate 1 are used to collect and transport photogenerated carriers, thereby realizing the electrical energy conversion of the solar cell.

[0048] In this embodiment of the present invention, the surface of the silicon substrate 1 of the solar cell includes a region for welding the solder strip and a region for not welding the solder strip. The region for welding the solder strip is the region on the surface of the silicon substrate 1 for setting the solder strip, and the solar cells are connected into a battery string using the solder strip. The region for not welding the solder strip is the region on the surface of the silicon substrate 1 other than the region for welding the solder strip, that is, the region on the surface of the silicon substrate 1 for which no solder strip is required.

[0049] In this embodiment of the invention, only a portion of the fine gates 2 may be intermittently formed with at least two sub-fine gate segments 25 in the non-welded solder area on the surface of the silicon substrate 1, and adjacent sub-fine gate segments 25 of the fine gate 2 may be connected by conductive portions 27; alternatively, all fine gates 2 may be intermittently formed with at least two sub-fine gate segments 25 in the non-welded solder area on the surface of the silicon substrate 1, and adjacent sub-fine gate segments 25 of the fine gate 2 may be connected by conductive portions 27.

[0050] The solar cell provided in this embodiment of the invention forms at least one discontinuity region 26 in the non-welded ribbon region of the non-welded ribbon area on the surface of the silicon substrate 1 for at least a portion of the fine grids 2. This allows the fine grids 2 to be arranged in the non-welded ribbon region as at least two sub-fine grid segments 25 spaced sequentially along the second direction X. Since adjacent sub-fine grid segments 25 are independently arranged, and are discontinuous, the length of the fine grids 2 in the non-welded ribbon region is avoided from becoming excessively long. This allows the fine grids 2 to be printed in segments, improving the printing accuracy of the fine grids 2 in the non-welded ribbon region, thereby improving the production efficiency of the solar cell. The yield is improved; moreover, a conductive part 27 is provided in the discontinuity region 26 between two adjacent sub-fine gate segments 25, and the two adjacent sub-fine gate segments 25 are connected by the conductive part 27 to achieve conductivity between the two adjacent sub-fine gate segments 25, thereby achieving good carrier collection between the two sub-fine gate segments 25; at the same time, the conductive part 27 can not only electrically connect the two adjacent sub-fine gate segments 25, but also fix the two adjacent sub-fine gate segments 25, thereby improving the structural strength of the two adjacent sub-fine gate segments 25, and thus improving the reliability of the sub-fine gate segments 25 of the fine gate 2 fixed on the surface of the silicon substrate 1.

[0051] Please refer to the reference. Figure 5 As an embodiment of the present invention, the conductive part 27 includes a middle part 271 and two connecting parts 272 respectively connected to both ends of the middle part 271. One connecting part 272 is connected to one of the two adjacent sub-fine gate segments 25, and the other connecting part 272 is connected to the other sub-fine gate segment 25. The dimension L1 of the connecting part 272 along the first direction Y is greater than the dimension L2 of the middle part 271 along the first direction Y.

[0052] In this embodiment, the dimensions L1 of the connecting portion 272 along the first direction Y and the dimension L2 of the intermediate portion 271 along the first direction Y can be uniformly or non-uniformly distributed. When the dimension L1 of the connecting portion 272 along the first direction Y is non-uniformly distributed, the dimension L1 of the connecting portion 272 along the first direction Y is the maximum value of the dimension L1 of the connecting portion 272 along the first direction Y. When the dimension L2 of the intermediate portion 271 along the first direction Y is non-uniformly distributed, the dimension L2 of the intermediate portion 271 along the first direction Y is the maximum value of the dimension L2 of the intermediate portion 271 along the first direction Y.

[0053] In this embodiment, since the dimension L1 of the connecting portion 272 along the first direction Y is larger than the dimension L2 of the middle portion 271 along the first direction Y, on the one hand, the reliability of the connection between the connecting portion 272 of the conductive portion 27 and the sub-fine grid segment 25 can be improved; on the other hand, since the dimension L2 of the middle portion 271 along the first direction Y is smaller than the dimension L1 of the connecting portion 272 along the first direction Y, it is beneficial to reduce the amount of printing paste used in the conductive portion 27, and thus reduce the printing cost of the solar cell.

[0054] In this embodiment, the two connecting portions 272 of each conductive portion 27 can have the same shape and size, or they can have differences. Preferably, the two connecting portions 272 of each conductive portion 27 have the same shape and size, which facilitates the design and printing of the conductive portion 27.

[0055] As an embodiment of the present invention, the connecting portion 272 includes a first end 2721 disposed near the middle portion 271 and a second end 2722 disposed away from the middle portion 271. The size of the second end 2722 in the first direction Y is greater than the size of the first end 2721 in the first direction Y.

[0056] In this embodiment, the size of the second end 2722 in the first direction Y is controlled to be larger than the size of the first end 2721 in the first direction Y, so that the longitudinal size of the connecting part 272 is larger as it gets closer to the sub-fine grid segment 25. This is beneficial to further improve the overlap reliability of the connecting part 272 and the sub-fine grid segment 25 and reduce the risk of misalignment between the connecting part 272 and the sub-fine grid segment 25.

[0057] As an embodiment of the present invention, the size of the connecting portion 272 in the first direction Y gradually increases from the first end 2721 to the second end 2722.

[0058] In this embodiment, the size of the control connection portion 272 in the first direction Y gradually increases from the first end 2721 to the second end 2722, so that the longitudinal dimension of the connection portion 272 is larger as it gets closer to the sub-fine grid segment 25. This can further improve the overlap reliability between the connection portion 272 of the conductive portion 27 and the sub-fine grid segment 25. At the same time, it is beneficial to further reduce the amount of printing paste used in the conductive portion 27, which helps to reduce the printing cost of the solar cell.

[0059] As an embodiment of the present invention, the sub-fine grid segment 25 is connected to the connecting portion 272, and the sub-fine grid segment 25 extends to the middle portion 271 and is connected to the middle portion 271.

[0060] In this embodiment, the sub-fine gate segment 25 is connected to both the connecting portion 272 and the intermediate portion 271, which helps to increase the contact area between the sub-fine gate segment 25 and the conductive portion 27, improve the conductivity reliability between the sub-fine gate segment 25 and the conductive portion 27, and also helps to improve the reliability of the sub-fine gate segment 25 fixed on the surface of the silicon substrate 1.

[0061] In one embodiment of this utility model, the ratio of the length of the middle part 271 to the length of each connecting part 272 is 2 to 5.

[0062] In this embodiment, the length direction of the middle part 271 and the length direction of the connecting part 272 are both along the second direction X. The ratio of the length of the middle part 271 to the length of each connecting part 272 is controlled to be 2 to 5. This can not only achieve reliable overlap between the sub-fine grid segment 25 and the connecting part 272 at the same time, but also help reduce the printing paste of the conductive part 27.

[0063] Please refer to the reference. Figures 1-2 and Figures 7-9 As one embodiment of this utility model, it also includes:

[0064] A plurality of main gates 3 are disposed on the surface of silicon substrate 1. The main gates 3 include a first polarity main gate 31 and a second polarity main gate 32 that are alternately disposed along the second direction X.

[0065] The fine grid 2 includes a plurality of first polar fine grids 21 and a plurality of second polar fine grids 22. The plurality of first polar fine grids 21 and the plurality of second polar fine grids 22 are arranged alternately along the first direction Y. The first polar fine grids 21 are connected to the first polar main grid 31, and the second polar fine grids 22 are connected to the second polar main grid 32.

[0066] At least a portion of the first polarity fine grid 21 and / or at least a portion of the second polarity fine grid 22 form a discontinuity region 26 in the region where the main grid 3 is not located.

[0067] In this embodiment, the solar cell is a back-contact solar cell. The main grid 3 is used to collect the charge carriers collected by the fine grid 2. Pads 5 are respectively provided on the first polarity main grid 31 and the second polarity main grid 32, and the first polarity main grid 31 and the second polarity main grid 32 are soldered to the solder ribbon through the pads 5. The number of first polarity main grids 31 and second polarity main grids 32 included in the main grid 3 is not limited. Preferably, there are multiple first polarity main grids 31 and multiple second polarity main grids 32, which are arranged alternately and at intervals along the second direction X.

[0068] In this embodiment, each first polar fine gate 21 may form a discontinuity region 26 in the area of ​​the non-welded solder strip, or only a portion of the first polar fine gates 21 may form discontinuities 26 in the area of ​​the non-welded solder strip. Adjacent sub-fine gate segments 25 of the first polar fine gate 21 are connected by conductive portions 27, and each first polar fine gate 21 forms a break at the position of the second polar main gate 32 to achieve separation from the second polar main gate 32. Similarly, each second polar fine gate 22 may form a discontinuity region 26 in the area of ​​the non-welded solder strip, or only a portion of the second polar fine gates 22 may form discontinuities 26 in the area of ​​the non-welded solder strip. Adjacent sub-fine gate segments 25 of the second polar fine gate 22 are connected by conductive portions 27, and each second polar fine gate 22 forms a break at the position of the first polar main gate 31 to achieve separation from the first polar main gate 31.

[0069] In one embodiment of this invention, the conductive portion 27 is made of the same material as the main gate 3. Optionally, the conductive portion 27 and the main gate 3 are simultaneously printed on the surface of the silicon substrate 1 to facilitate the printing and processing of the conductive portion 27. Of course, the conductive portion 27 can also be printed separately on the surface of the silicon substrate 1.

[0070] In a preferred embodiment of the present invention, the main gate 3 includes a first main gate 301 located at the edge of the silicon substrate 1 and a second main gate 302 disposed adjacent to the first main gate 301, and at least a portion of the fine gate 2 forms at least one discontinuity region 26 between the first main gate 301 and the second main gate 302.

[0071] like Figures 1-2 As shown, the first polar fine gate 21 between the first main gate 301 and the second main gate 302 adjacent to the first main gate 301 forms a discontinuity region 26 between the first main gate 301 and the second main gate 302 in the second polar main gate 32. The first polar fine gate 21 is connected between two adjacent sub-fine gate segments 25 of the second polar main gate 32 through conductive parts 27 provided in the discontinuity region 26.

[0072] In this embodiment, the pad 5 connecting the first main gate 301 is disposed on the side of the first main gate 301 near the second main gate 302, and the pad 5 connecting the first main gate 301 is connected to the first main gate 301 through a conductive structure 6. The first main gate 301 and the second main gate 302 are, respectively, a first polarity main gate and a second polarity main gate.

[0073] In this embodiment, the pad 5 on the first main gate at the edge of the silicon substrate 1 in the related art is moved inward. The distance between the first main gate 301 and the second main gate 302 is usually greater than the distance between adjacent main gates 3 in the middle position. Therefore, the length of the fine gate 2 between the first main gate 301 and the second main gate 302 is usually relatively long. However, in this embodiment of the present invention, the fine gate 2 between the first main gate 301 and the second main gate 302 is spaced to form at least one discontinuity region 26, thereby forming at least two spaced sub-fine gate segments 25 between the first main gate 301 and the second main gate 302. Adjacent two sub-fine gate segments 25 are connected by a conductive part 27, which can avoid the fine gate 2 between the first main gate 301 and the second main gate 302 being too long. The fine gate 2 between the first main gate 301 and the second main gate 302 can be printed in segments of each sub-fine gate segment 25, which can improve the printing accuracy of the fine gate 2 between the first main gate 301 and the second main gate 302, thereby improving the production yield of solar cells.

[0074] Please refer to the reference. Figure 6 As one embodiment of this utility model, it also includes:

[0075] A doped layer 7 is disposed on the surface of the silicon substrate 1;

[0076] A passivation layer 8 is provided on the doped layer 7. The fine gate 2 passes through the passivation layer 8 and contacts the doped layer 7. The conductive part 27 is located on the passivation layer 8 and does not pass through the passivation layer 8.

[0077] In this embodiment, the doped layer 7 can specifically be one or a combination of doped polycrystalline silicon, doped microcrystalline silicon, or doped amorphous silicon. The passivation layer 8 can specifically be at least one or a combination of silicon nitride, silicon carbide, and silicon oxynitride.

[0078] In this embodiment, the fine grid 2 specifically uses a burn-through paste. For example, the burn-through paste can be aluminum paste or silver-aluminum paste containing glass powder. During the printing of the fine grid 2, the paste of the fine grid 2 passes through the passivation layer 8 and contacts the doped layer 7, achieving electrical contact between the fine grid 2 and the doped layer 7. The conductive part 27 can use a non-burn-through paste. For example, the non-burn-through paste can be aluminum paste or silver-aluminum paste without glass powder. During the printing of the conductive part 27, the paste of the conductive part 27 will not burn through the passivation layer 8 and contact the doped layer 7, avoiding metallization damage to the doped layer 7 caused by the conductive part 27, which is beneficial to improving battery efficiency.

[0079] As an embodiment of the present invention, each of the multiple fine grids 2 includes at least two sub-fine grid segments 25 arranged sequentially at intervals along the second direction X. Two adjacent sub-fine grid segments 25 of the multiple fine grids 2 are connected by conductive parts 27, and at least a plurality of conductive parts 27 are arranged in a row.

[0080] In this embodiment, each of the multiple fine grids 2 is configured as at least two sub-fine grid segments 25 arranged sequentially at intervals along the second direction X. Adjacent sub-fine grid segments 25 are provided with discontinuity regions 26, and conductive parts 27 are provided in the discontinuity regions 26. Since the two adjacent sub-fine grid segments 25 of the multiple fine grids 25 are connected by the conductive parts 27, it is convenient to print the multiple fine grids 25 in segments, which can further improve the printing accuracy of the multiple fine grids 2, thereby improving the production yield of solar cells. Moreover, the multiple conductive parts 27 can be arranged in one or more columns, and the multiple conductive parts 27 in each column are located at the same position in the second direction X, which facilitates the printing of the conductive parts 27.

[0081] Please refer to the reference. Figure 7 As an embodiment of the present invention, the main grid 3 includes at least two main grid unit segments 30 spaced apart from each other along the first direction Y, and a fine grid 2 is provided between two adjacent main grid unit segments 30 along the first direction Y, and the fine grid 2 between two adjacent main grid unit segments 30 along the first direction Y forms at least one discontinuity region 26.

[0082] In this embodiment, the main grid 3 is a discontinuous structure in the first direction Y, that is, the main grid 3 is intermittently arranged in the first direction Y, and the main grid 3 is divided into multiple main grid unit segments 3 in the first direction Y. The first polarity main grid 31 and the second polarity main grid 32 both include at least two main grid unit segments 30 that are spaced apart from each other along the first direction Y. In the related art, the fine grid 2 between two adjacent main grid unit segments 30 along the first direction Y is a continuous structure that spans the entire cell along the second direction X. In this embodiment of the present invention, the fine grid 2 between two adjacent main grid unit segments 30 is arranged as at least two sub-fine grid segments 25 spaced apart along the second direction X. The two adjacent sub-fine grid segments 25 are connected by a conductive part 27 disposed in the discontinuity region 26, which can avoid the continuous length of the fine grid 2 being too long. The fine grid 2 can be printed in segments, which can improve the printing accuracy of the fine grid 2, thereby improving the production yield of solar cells.

[0083] The location of the fine grid 2 between two adjacent main grid unit segments 30 is not limited; it can be located at one-third, two-thirds, or one-half of the cell, or simultaneously at these locations. Optionally, a first polarity fine grid 21 and a second polarity fine grid 22 are provided between adjacent main grid unit segments 30. The first polarity fine grid 21 forms a discontinuity region 26 between adjacent main grid unit segments 30 of the second polarity main grid 32. The discontinuity region 26 is provided with a conductive part 27, and adjacent sub-fine grid segments 25 of the first polarity fine grid 21 are connected through the conductive part 27. The second polarity fine grid 22 forms a discontinuity region 26 between adjacent main grid unit segments 30 of the first polarity main grid 31. The discontinuity region 26 is provided with a conductive part 27, and adjacent sub-fine grid segments 25 of the second polarity fine grid 22 are connected through the conductive part 27.

[0084] Please refer to the reference. Figure 8 As an embodiment of the present invention, the first polar main gate 31 includes a first sub-main gate segment 311 and a second sub-main gate segment 312 spaced apart along the second direction X, a first overlapping portion 313 protruding on one side of the first sub-main gate segment, and a second overlapping portion 314 protruding on the other side of the second sub-main gate segment 312. The first sub-main gate segment 311 and the second sub-main gate segment 312 are spaced apart to form a first spacing region 315.

[0085] The first polar fine grid 21 is connected to the first polar main grid 31, and the second polar fine grid 22 is spaced apart from the first polar main grid 32. The first polar fine grid 21 includes a first unit segment 211 and a second unit segment 212 spaced apart along the second direction X. The first unit segment 211 is connected to the first overlapping portion 313, and the second unit segment 212 is connected to the second overlapping portion 314. The first unit segment 211 and the second unit segment 212 are spaced apart by a first spacing region 315.

[0086] In this embodiment, the first polar main gate 31 is configured to include a first sub-main gate segment 311 and a second sub-main gate segment 312 spaced apart along the second direction X, a first overlapping portion 313 protruding on one side of the first sub-main gate segment 311, and a second overlapping portion 314 protruding on the other side of the second sub-main gate segment 312. The first polar fine gate 21 connected to the first polar main gate 31 includes a first unit segment 211 and a second unit segment 212 spaced apart along the second direction X; since the first unit segment 211 and the second unit segment 212 of the first polar fine gate 21 are in the first polar main gate 31, the first unit segment 211 and the second unit segment 212 are in the second polar main gate 31. The first polar main grid 31 is spaced apart by a first interval region 315. That is, the first polar fine grid 21 connecting the first polar main grid 31 is set as an independent first unit segment 211 and a second unit segment 212, so that the first unit segment 211 and the second unit segment 212 are discontinuous with each other. This can avoid the first polar fine grid 21 connecting the first polar main grid 31 from being too long. Therefore, the first unit segment 211 and the second unit segment 212 of the first polar fine grid 21 can also be printed in segments, thereby further improving the printing accuracy of the first polar fine grid 21.

[0087] Because the first unit segment 211 and the second unit segment 212 of the first polar fine grid 21 are printed in segments, the relative offset of the first unit segment 211 and the second unit segment 212 in the first direction Y can be reduced. Therefore, it is beneficial to reduce the size design of the first overlapping portion 313 and the second overlapping portion 314 on the first polar main grid 31 in the first direction Y. The first overlapping portion 313 and the second overlapping portion 314 are set to a smaller size in the first direction Y, which also allows the first overlapping portion 313 and the second overlapping portion 314 to form a good overlap with the first unit segment 211 and the second unit segment 212 respectively. Therefore, it is beneficial to reduce the size of the first overlapping portion 313 and the second overlapping portion 314. The smaller size of the first polar grid 31 helps to save on the amount of printing paste used, reducing the printing cost of the first polar grid 31 and thus lowering the battery production cost. Furthermore, since the first polar grid 21 is configured as independent first unit segments 211 and second unit segments 212, the dimensions of the first overlapping portion 313 and the second overlapping portion 314 on the first polar grid 31 in the first direction Y can be reduced. This allows for an increase in the distance between the first overlapping portion 313 and the second overlapping portion 314 and the second polar grid 22 in the first direction Y, thereby reducing the short-circuit risk between the first polar grid 31 and the second polar grid 22 and improving battery reliability. Additionally, since the first polar grid 31 has a first spacing region 315, and the first unit segments 211 and 212 are spaced apart in the first spacing region 315, the length of the first polar grid 21 can be reduced, decreasing the paste used in the first polar grid 21 and further reducing costs.

[0088] Please refer to the reference. Figure 9As an embodiment of the present invention, the second polarity main gate 32 includes a third sub-main gate segment 321 and a fourth sub-main gate segment 322 spaced apart along the second direction X, a third overlapping portion 323 protruding on one side of the third sub-main gate segment 321, and a fourth overlapping portion 324 protruding on one side of the fourth sub-main gate segment 322. The third sub-main gate segment 321 and the fourth sub-main gate segment 322 are spaced apart to form a second spacing region 325.

[0089] The second polar fine grid 22 is connected to the second polar main grid 32. The first polar fine grid 21 is spaced apart from the second polar main grid 32. The second polar fine grid 22 includes a third unit segment 221 and a fourth unit segment 222 spaced apart along the second direction X. The third unit segment 221 is connected to the third overlapping portion 323, and the fourth unit segment 222 is connected to the fourth overlapping portion 324. The third unit segment 221 and the fourth unit segment 222 are spaced apart by the second spacing region 325.

[0090] In this embodiment, the second polar main gate 32 is configured to include a third sub-main gate segment 321 and a fourth sub-main gate segment 322 spaced apart along the second direction X, a third overlapping portion 323 protruding on one side of the third sub-main gate segment 321, and a fourth overlapping portion 324 protruding on one side of the fourth sub-main gate segment 322. The second polar fine gate 22 connected to the second polar main gate 32 includes a third unit segment 221 and a fourth unit segment 222 spaced apart along the second direction X. Because the third unit segment 221 and the fourth sub-main gate segment 322 of the second polar fine gate 22 are spaced apart along the second direction X; The four unit segments 222 are spaced apart on the second polar main grid 32 by the second interval area 325. That is, the second polar fine grids 22 connecting the second polar main grid 32 are set as independent third unit segments 221 and fourth unit segments 222, so that the third unit segments 221 and fourth unit segments 222 are discontinuous with each other. This can avoid the second polar fine grids 22 connecting the second polar main grid 32 from being too long. The second polar fine grids 22 connecting the second polar main grid 32 are printed in segments, which can improve the printing accuracy of the second polar fine grids 22.

[0091] Furthermore, since the third unit segment 221 and the fourth unit segment 222 are printed in segments, the relative offset between the third unit segment 221 and the fourth unit segment 222 in the first direction Y can be reduced. This facilitates the reduction of the size design of the third overlapping portion 323 and the fourth overlapping portion 324 on the second polar main grid 32 in the first direction Y. Setting the third overlapping portion 323 and the fourth overlapping portion 324 to a smaller size in the first direction Y also allows the third overlapping portion 323 and the fourth overlapping portion 324 to form a good overlap with the third unit segment 221 and the fourth unit segment 222 respectively, thereby saving printing space on the second polar main grid 32. The reduced amount of paste used lowers the printing cost of the second polarity main grid 32, further reducing battery production costs. Furthermore, by minimizing the dimensions of the third and fourth overlapping portions 323 and 324 on the second polarity main grid 32 in the first direction Y, and by allowing these portions to avoid obstructing the first polarity fine grid 21, the distance between the third and fourth overlapping portions 323 and the first polarity fine grid 21 in the first direction Y can be increased. This reduces the risk of short circuits between the second polarity main grid 32 and the first polarity fine grid 21, improving battery reliability. Additionally, the second spacing region 325 on the second polarity main grid 32, with the third unit segment 221 and the fourth unit segment 222 spaced apart through it, reduces the length of the second polarity fine grid 22, decreasing paste usage and further reducing costs.

[0092] This utility model embodiment also provides a battery assembly, which includes the solar cell described in the above embodiment. It should be noted that this battery assembly has the same or similar beneficial effects as the solar cell described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0093] This utility model embodiment also provides a photovoltaic system, which includes the battery module described in the above embodiment. It should be noted that this photovoltaic system has the same or similar beneficial effects as the battery module described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0094] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0095] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0096] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A solar cell, characterized in that, include: Silicon substrate; and A plurality of fine gates are disposed on the surface of the silicon substrate, the plurality of fine gates being arranged sequentially at intervals along a first direction, and each fine gate extending along a second direction intersecting the first direction; wherein, at least a portion of the fine gates include at least two sub-fine gate segments arranged sequentially at intervals along the second direction, and an interruption region is provided between adjacent sub-fine gate segments, the interruption region being located in the non-welded solder strip area on the surface of the silicon substrate, the interruption region being provided with a conductive portion, and adjacent two sub-fine gate segments being connected through the conductive portion.

2. The solar cell according to claim 1, characterized in that, The conductive portion includes a middle portion and two connecting portions respectively connected to both ends of the middle portion. One connecting portion is connected to one of the two adjacent sub-fine gate segments, and the other connecting portion is connected to the other of the two adjacent sub-fine gate segments. The dimension of the connecting portion along the first direction is greater than the dimension of the middle portion along the first direction.

3. The solar cell according to claim 2, characterized in that, The connecting portion includes a first end disposed near the middle portion and a second end disposed away from the middle portion, wherein the dimension of the second end in the first direction is greater than the dimension of the first end in the first direction.

4. The solar cell according to claim 3, characterized in that, The dimension of the connecting portion in the first direction gradually increases from the first end to the second end.

5. The solar cell according to any one of claims 2 to 4, characterized in that, The sub-fine grid segment is connected to the connecting portion, and the sub-fine grid segment extends to the middle portion and is connected to the middle portion.

6. The solar cell according to claim 2, characterized in that, The ratio of the length of the middle section to the length of each of the connecting sections is 2 to 5.

7. The solar cell according to claim 1, characterized in that, Also includes: A plurality of main gates are disposed on the surface of the silicon substrate, the main gates including a first polar main gate and a second polar main gate that are alternately spaced along the second direction; The fine grid includes a plurality of first polar fine grids and a plurality of second polar fine grids. The plurality of first polar fine grids and the plurality of second polar fine grids are arranged alternately and at intervals along the first direction. The first polar fine grids are connected to the first polar main grid, and the second polar fine grids are connected to the second polar main grid. At least a portion of the first polar fine gate and / or at least a portion of the second polar fine gate form the discontinuity region in the region where the main gate is not located.

8. The solar cell according to claim 7, characterized in that, The main gate includes a first main gate located at the edge of the silicon substrate and a second main gate disposed adjacent to the first main gate, wherein at least a portion of the fine gate forms at least one discontinuity region between the first main gate and the second main gate.

9. The solar cell according to claim 7, characterized in that, The main grid includes at least two main grid unit segments spaced apart from each other along the first direction, and the fine grids are disposed between adjacent main grid unit segments along the first direction, and the fine grids between adjacent main grid unit segments along the first direction form at least one discontinuity region.

10. The solar cell according to claim 1, characterized in that, Also includes: A doped layer disposed on the surface of the silicon substrate; A passivation layer is disposed on the doped layer, the fine gate passes through the passivation layer and contacts the doped layer, and the conductive portion is located on the passivation layer but does not pass through the passivation layer.

11. The solar cell according to claim 1, characterized in that, Each of the multiple fine grids includes at least two sub-fine grid segments arranged sequentially at intervals along the second direction. Two adjacent sub-fine grid segments of the multiple fine grids are connected by the conductive part, and at least a plurality of the conductive parts are arranged in a row.

12. The solar cell according to claim 7, characterized in that, The first polar main gate includes a first sub-main gate segment and a second sub-main gate segment spaced apart along the second direction, a first overlapping portion protruding on one side of the first sub-main gate segment, and a second overlapping portion protruding on the other side of the second sub-main gate segment. The first sub-main gate segment and the second sub-main gate segment are spaced apart to form a first gap area. The first polar fine grid includes a first unit segment and a second unit segment spaced apart along the second direction. The first unit segment is connected to the first overlapping portion, the second unit segment is connected to the second overlapping portion, and the first unit segment and the second unit segment are spaced apart by the first interval region.

13. The solar cell according to claim 7 or 12, characterized in that, The second polarity main gate includes a third sub-main gate segment and a fourth sub-main gate segment spaced apart along the second direction, a third overlapping portion protruding on one side of the third sub-main gate segment, and a fourth overlapping portion protruding on the other side of the fourth sub-main gate segment, wherein the third sub-main gate segment and the fourth sub-main gate segment are spaced apart to form a second spacing region; The second polar fine grid includes a third unit segment and a fourth unit segment spaced apart along the second direction. The third unit segment is connected to the third overlapping portion, and the fourth unit segment is connected to the fourth overlapping portion. The third unit segment and the fourth unit segment are spaced apart by the second spacing region.

14. A battery assembly, characterized in that, Includes the solar cell described in any one of claims 1 to 13.

15. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 14.

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