Nonvolatile two-terminal memory cell, memory and electronic device

Abstract

The utility model discloses a nonvolatile two-end storage unit, a memory and electronic equipment, the nonvolatile two-end storage unit comprises a second area, the second area comprises a second area lower electrode metal connecting layer, a second area functional layer and a second area upper electrode metal connecting layer, and the second region functional layer is electrically connected with the second region lower electrode metal connecting layer and the second region upper electrode metal connecting layer respectively. Due to the effect of the second area functional layer, the upper surface of the second area lower electrode metal connecting layer is prevented from being oxidized or oxidation diffusion is slowed down in the machining process, meanwhile, the second area lower electrode metal connecting layer is prevented from being damaged in the etching process, and in addition, the etching efficiency is improved. And electric connection between the second region lower electrode metal connecting layer and the second region upper electrode metal connecting layer can be ensured.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a non-volatile two-terminal memory cell and products thereof. Background Technology

[0002] Resistive Random Access Memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on changes in the resistance of a material. It typically consists of a lower electrode, a switching layer, and a upper electrode. In existing technologies, during the fabrication of RRAM, the lower electrode metal interconnect layer in the peripheral circuit area is exposed to air for an extended period. During this time, the air can cause oxidation of the upper surface of the lower electrode metal interconnect layer, leading to increased resistance and poor contact between the lower and upper electrode metal interconnect layers. Furthermore, the etching process used to form the interconnect vias of the upper electrode in the second region based on a patterned photomask may damage the upper surface or even the entire lower electrode metal interconnect layer, resulting in defects in the non-volatile two-terminal memory cell.

[0003] In view of this, there is an urgent need to provide a solution for a non-volatile two-terminal memory cell that prevents the upper surface of the lower electrode metal interconnect layer of the second region from being oxidized or slows down the oxidation diffusion during the processing, prevents the lower electrode metal interconnect layer of the second region from being damaged during etching, and ensures that the lower electrode metal interconnect layer of the second region is electrically connected to the upper electrode metal interconnect layer of the second region. Utility Model Content

[0004] In order to at least address one or more of the technical problems mentioned above, this disclosure proposes a solution for a non-volatile two-end storage cell and its products in several aspects.

[0005] In a first aspect, this disclosure provides a non-volatile two-terminal memory cell including a second region, wherein the second region includes a second region lower electrode metal connection layer 112, a second region functional layer 342 and a second region upper electrode metal connection layer 192, the second region functional layer 342 being electrically connected to the second region lower electrode metal connection layer 112 and the second region upper electrode metal connection layer 192 respectively.

[0006] In some embodiments, the second region further includes a first dielectric layer 130, in which a second region lower electrode interconnect via 142 is formed, and a second region functional layer 342 is located in the second region lower electrode interconnect via 142, with the bottom of the second region functional layer 342 in contact with the upper surface of the second region lower electrode metal connection layer 112.

[0007] In some embodiments, the upper surface of the second functional layer 342 is lower than the upper surface of the first dielectric layer 130.

[0008] In some embodiments, the second region further includes a second dielectric layer 170, in which a second region upper electrode interconnect via 182 is formed, and a second region upper electrode metal connection layer 192 is located in the second region upper electrode interconnect via 182, with the bottom of the second region upper electrode metal connection layer 192 in contact with the upper surface of the second region functional layer 342.

[0009] In some embodiments, the bottom of the upper electrode metal connection layer 192 of the second region is located in the lower electrode interconnect via 142 of the second region and is in contact with the upper surface of the functional layer 342 of the second region.

[0010] In some embodiments, the non-volatile two-terminal storage cell further includes a first region, wherein the first region includes a first region lower electrode metal connection layer 111, a first region upper electrode metal connection layer 191 and a first dielectric layer 130, wherein a first region lower electrode interconnect via 141 is formed in the first dielectric layer 130, wherein the material in the first region lower electrode interconnect via 141 is electrically connected to the first region lower electrode metal connection layer 111 and the first region upper electrode metal connection layer 191 respectively.

[0011] In a second aspect, this disclosure provides a memory comprising one or more non-volatile end-to-end memory cells according to any embodiment of this disclosure.

[0012] In a third aspect, this disclosure provides an electronic device, wherein the electronic device includes the memory described in the embodiments of this disclosure.

[0013] This embodiment discloses a second functional layer 342 formed between the second region lower electrode metal connection layer 112 and the second region upper electrode metal connection layer 192, thereby achieving electrical connection between the two regions. Since the second functional layer 342 is formed earlier than the second region upper electrode metal connection layer 192, the copper on the upper surface of the second region lower electrode metal connection layer 112 can be prevented from oxidation or its diffusion can be slowed, while simultaneously increasing the QTime (Queue Time) of the fabrication process. Because the second functional layer 342 covers the second region lower electrode metal connection layer 112, it prevents damage to the second region lower electrode metal connection layer 112 during etching. Since the material of the second functional layer 342 is conductive, the addition of the second functional layer 342 achieves the aforementioned functions while maintaining the electrical connection between the second region lower electrode metal connection layer 112 and the second region upper electrode metal connection layer 192. Attached Figure Description

[0014] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0015] Figures 1A-1F A schematic diagram of the semiconductor cross-sectional structure of the peripheral circuit region of a non-volatile two-terminal memory cell fabricated using existing technology is shown.

[0016] Figure 2 A schematic diagram of the semiconductor cross-sectional structure of the peripheral circuit region of the non-volatile two-terminal memory cell according to an embodiment of this disclosure is shown.

[0017] Figures 3A-3H A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating a method for fabricating a non-volatile two-terminal memory cell according to some embodiments of this disclosure;

[0018] Figures 4A-4J A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating a method for fabricating a non-volatile two-terminal memory cell according to other embodiments of this disclosure.

[0019] Appendix Symbols:

[0020] 110-Lower electrode metal connection layer, 111-First region lower electrode metal connection layer, 112-Second region lower electrode metal connection layer, 120-Lower dielectric layer, 130-First dielectric layer, 141-First region lower electrode interconnect via, 142-Second region lower electrode interconnect via, 1511-Second lower electrode metal layer 1, 15111-First region second lower electrode metal layer 1, 1512-Second lower electrode metal layer 2, 152-Second switching layer, 153-Second upper electrode metal layer, 154-Upper electrode hard mask layer, 159-Sidewall, 170-Second dielectric layer, 181-First region upper electrode interconnect via, 182-Second region upper electrode interconnect via, 191-First region upper electrode metal connection layer, 192-Second region upper electrode metal connection layer;

[0021] 250A - First stacked layer of the first region, 250B - First stacked layer of the second region, 251 - First lower electrode metal layer, 252 - First switching layer, 253 - First upper electrode metal layer;

[0022] 342 - Second functional layer, 350 - Storage cell stacking layer, 391 - First patterned photomask layer, 393 - Third patterned photomask layer, 394 - Fourth patterned photomask layer;

[0023] 50 - Stop line, 80 - Memory cell array area, 90 - Peripheral circuit area. Detailed Implementation

[0024] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0028] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0029] Figures 1A-1F A schematic diagram of the semiconductor cross-sectional structure of the peripheral circuit region of a non-volatile two-terminal memory cell fabricated using existing technology is shown.

[0030] Figure 1A A schematic diagram of the semiconductor cross-sectional structure of the second region lower electrode metal interconnect layer 112 in the prior art is shown.

[0031] like Figure 1A As shown, the lower dielectric layer 120 surrounds the second lower electrode metal connection layer 112 located in the peripheral circuit region 90, and exposes the upper surface of the second lower electrode metal connection layer 112. The upper surface of the second lower electrode metal connection layer 112 is flush with the upper surface of the lower dielectric layer 120.

[0032] Figure 1B A schematic diagram of a semiconductor cross-sectional structure forming the first dielectric layer 130 in the prior art is shown.

[0033] like Figure 1B As shown, a first dielectric layer 130 is deposited on the upper surface of the second region lower electrode metal connection layer 112, which is surrounded by a lower dielectric layer 120, using a thin film deposition process. The first dielectric layer 130 may consist of multiple layers.

[0034] Figure 1C A schematic diagram of a semiconductor cross-sectional structure for forming a second region lower electrode interconnect via 142 in the prior art is shown.

[0035] like Figure 1CAs shown, a patterned photomask layer is formed above the first dielectric layer 130, the pattern of which can be used to define the pattern of the subsequently formed second region lower electrode interconnect via 142 located in the peripheral circuit region 90. Based on this patterned photomask layer, the exposed first dielectric layer 130 is etched to form the second region lower electrode interconnect via 142 in the first dielectric layer 130, and the patterned photomask layer is removed.

[0036] Specifically, the second region lower electrode interconnect via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. The cross-sectional shape and size of the second region lower electrode interconnect via 142 are not limited. Preferably, the cross-sectional shape of the second region lower electrode interconnect via 142 is an inverted trapezoid, the width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, the width of the upper base of the inverted trapezoid is greater than 1000 Å, the width of the lower base of the inverted trapezoid is greater than 600 Å, and the angle between the waist and the lower base of the inverted trapezoid is greater than 105 degrees.

[0037] Figure 1D A schematic diagram of a semiconductor cross-sectional structure of a second dielectric layer 170 deposited in the prior art is shown.

[0038] like Figure 1D As shown, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130 and the surface of the exposed second region lower electrode metal interconnect layer 112, such that the second dielectric layer 170 at least fills the remaining space of the second region lower electrode interconnect via 142.

[0039] Figure 1E A schematic diagram of a semiconductor cross-sectional structure for forming the upper electrode interconnect via 182 in the second region is shown in the prior art.

[0040] like Figure 1E As shown, a patterned photomask layer is formed above the second dielectric layer 170, the pattern of which can be used to define the pattern of the subsequently formed upper electrode interconnect via 182 located in the peripheral circuit region 90. Based on this patterned photomask layer, the exposed second dielectric layer 170 is etched to form the upper electrode interconnect via 182 in the second dielectric layer 170, and the patterned photomask layer is removed.

[0041] Specifically, the upper electrode interconnect via 182 of the second region is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the lower electrode metal connection layer 112 of the second region. The cross-sectional shape and size of the lower electrode interconnect via 142 of the second region are not limited.

[0042] Figure 1F A schematic diagram of a semiconductor cross-sectional structure in the prior art for forming the upper electrode metal interconnect layer 192 of the second region is shown.

[0043] like Figure 1FAs shown, the upper electrode interconnect via 182 in the second region is filled with a second region upper electrode metal interconnect layer 192. The second region upper electrode metal interconnect layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second region lower electrode metal interconnect layer 112.

[0044] In the prior art, during the fabrication of the lower and upper electrodes of a non-volatile two-sided memory cell, after etching the first dielectric layer 130 to form the lower electrode interconnect via (i.e., the second region lower electrode interconnect via 142 mentioned above), the upper surface of the second region lower electrode metal interconnect layer 112 is directly exposed to air until the second region upper electrode metal interconnect layer 192 is formed. During this period, due to the effect of air, the upper surface of the second region lower electrode metal interconnect layer 112 may be oxidized, leading to problems such as increased resistance of the second region lower electrode metal interconnect layer 112 and poor contact between the second region lower electrode metal interconnect layer 112 and the second region upper electrode metal interconnect layer 192. Simultaneously, during the etching process of the second region upper electrode interconnect via 182 based on the patterned photomask layer, the upper surface of the second region lower electrode metal interconnect layer 112, or even the entire second region lower electrode metal interconnect layer 112, may be damaged, resulting in defects in the non-volatile two-sided memory cell.

[0045] In view of this, the present disclosure provides a non-volatile dual-ended memory cell. In addition to the second region including a second region lower electrode metal interconnect layer 112 and a second region upper electrode metal interconnect layer 192, the second region functional layer 342 is also included. The second region functional layer 342 is located within the second region lower electrode interconnect via 142 and between the second region lower electrode metal interconnect layer 112 and the second region upper electrode metal interconnect layer 192, and is electrically connected to both the second region lower electrode metal interconnect layer 112 and the second region upper electrode metal interconnect layer 192.

[0046] Figure 2 A schematic diagram of the semiconductor cross-sectional structure of the peripheral circuit region of a non-volatile two-terminal memory cell according to an embodiment of this disclosure is shown.

[0047] like Figure 2 As shown, the non-volatile dual-ended storage cell includes a second region, which comprises a second region lower electrode metal interconnect layer 112, a second region functional layer 342, and a second region upper electrode metal interconnect layer 192. The second region functional layer 342 is located at the bottom of the second region lower electrode interconnect via 142, with its upper surface in contact with the second region upper electrode metal interconnect layer 192 and its lower surface in contact with the second region lower electrode metal interconnect layer 112.

[0048] Since the formation of the second functional layer 342 precedes the formation of the second upper electrode metal interconnect layer 192, the copper on the upper surface of the second lower electrode metal interconnect layer 112 can be prevented from oxidation or its oxidation diffusion can be slowed down, while increasing the QTime (Queue Time) of the fabrication process. Because the second functional layer 342 covers the second lower electrode metal interconnect layer 112, it prevents damage to the second lower electrode metal interconnect layer 112 during etching. Since the material of the second functional layer 342 is conductive, the electrical connection between the second lower electrode metal interconnect layer 112 and the second upper electrode metal interconnect layer 192 is still maintained after the addition of the second functional layer 342.

[0049] Figures 3A-3H A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating a method for fabricating a non-volatile two-terminal memory cell according to some embodiments of this disclosure.

[0050] Figure 3A A schematic diagram of the semiconductor cross-sectional structure forming the first patterned photomask layer 391 according to an embodiment of this application is shown.

[0051] like Figure 3A As shown, a multilayer semiconductor structure is provided, and a first patterned photomask layer 391 is formed on top of the semiconductor structure. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed lower electrode interconnect vias 141 in the first region of the memory cell array region 80 and the lower electrode interconnect vias 142 in the second region of the peripheral circuit region 90.

[0052] Specifically, the semiconductor structure is processed to form the following structure in sequence: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, and a first patterned photomask layer 391.

[0053] The lower electrode metal connection layer 110 includes a first lower electrode metal connection layer 111 located in the memory cell array region 80 and a second lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are separated by a lower dielectric layer 120 to prevent short circuits from forming between the two first lower electrode metal connection layers 111, between the two second lower electrode metal connection layers 112, or between the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112. Simultaneously, the upper surfaces of the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first lower electrode metal connection layer 111, the second lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0054] The number of lower electrode metal connection layers 111 in the first region can be one or more. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be the same or different. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be copper. The main advantages of copper compared to other metals are its high electrical conductivity, high thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, other metals can also be used for the lower electrode metal connection layers 111 and 112 in the first region as needed, and this is not limited here.

[0055] Specifically, the material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, or a low-k dielectric material. More specifically, the low-k dielectric material can be porous silicon dioxide, silicon fluoride glass, etc. In the embodiments of this application, the lower dielectric layer 120 can also be selected from other materials according to the actual application scenario and process requirements, and is not limited here.

[0056] Specifically, various known processes can be used to fabricate the lower dielectric layer 120 around the lower electrode metal interconnect layer 110, and the embodiments of this application are not limited in this respect.

[0057] For example, a lower dielectric layer 120 is made to surround a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, exposing the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112. This part of the process includes: first, providing a lower dielectric layer 120, forming a patterned photomask layer on the lower dielectric layer 120, selectively exposing photoresist using an exposure machine, developing to remove exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing remaining photoresist, and continuing to form the desired first groove located in the memory cell array region 80 and the second groove located in the peripheral circuit region 90 by dry etching or wet etching, wherein the number of first grooves can be single or multiple. Then, metal material is deposited in the first groove and the second groove. Finally, the metal material is planarized to form a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, such that the upper surfaces of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush. Thus, a lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 is obtained, and the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112 are exposed.

[0058] Specifically, the lower electrode metal connection layer 110, surrounded by the lower dielectric layer 120, can isolate the first region lower electrode metal connection layer 111 from other unrelated parts; it can also isolate the second region lower electrode metal connection layer 112 from other unrelated parts. This prevents current from flowing along unwanted paths, avoiding short circuits and leakage. For example, it prevents direct connections between the two first region lower electrode metal connection layers 111, between the two second region lower electrode metal connection layers 112, or between the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112, thus avoiding short circuits.

[0059] Specifically, the first dielectric layer 130 is formed on the upper surface of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the exposed lower dielectric layer 120. The first dielectric layer 130 can be formed by a thin film deposition process. The first dielectric layer 130 can be a single layer or multiple layers. For example, the first dielectric layer 130 can include a first dielectric layer and a first dielectric layer stacked sequentially. The first dielectric layer can be a silicon nitride (SiN) thin film or a doped silicon carbide (NDC) thin film, and the first dielectric layer can be a low-temperature oxide (LTO), a silicon dioxide layer (SiO2), or a silicon rich oxide (SRO), etc. In the embodiments of this application, the first dielectric layer and the first dielectric layer can also be made of other materials according to the actual application scenario and process requirements, which are not limited here.

[0060] The first dielectric layer 130 can protect the first region second lower electrode metal layer 15111 and the second region functional layer 342 (including the second region second lower electrode metal layer 15112) from external damage.

[0061] Specifically, a first patterned photomask layer 391 is formed above the first dielectric layer 130. The first patterned photomask layer 391 can be made using either positive or negative photoresist. The first patterned photomask layer 391 can be formed using various known processes, and this application embodiment is not limited in this respect. For example, a photomask layer is coated above the first dielectric layer 130, and the photomask layer is exposed to form exposed and unexposed areas. Then, the exposed photomask layer is developed to remove the photomask layer in the exposed or unexposed areas, forming the first patterned photomask layer 391. When a positive photoresist is used, the photomask layer in the exposed areas changes from being insoluble in the developer to being soluble in the developer and is removed during development. When a negative photoresist is used, the photomask layer in the exposed areas changes from being soluble in the developer to being insoluble in the developer and is not removed during development. Thus, when a negative photoresist is used, the photomask layer in the unexposed areas is removed.

[0062] Figure 3B This illustration shows a schematic cross-sectional structure of a semiconductor forming a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142, according to an embodiment of this application.

[0063] like Figure 3B As shown, based on the first patterned photomask layer 391, the exposed first dielectric layer 130 is etched to form a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 in the first dielectric layer 130, and the first patterned photomask layer 391 is removed.

[0064] Specifically, the first region lower electrode interconnect via 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first region lower electrode metal connection layer 111. The second region lower electrode interconnect via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. Both the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum-shaped structure or a trapezoidal structure. In the embodiments of this application, the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can also be selected with other structural shapes according to the actual application scenario and process requirements, which are not limited here.

[0065] In this embodiment, the cross-sectional shape of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 is an inverted trapezoid. The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid. The width of the upper base of the inverted trapezoid is greater than 1000 Å, the width of the lower base of the inverted trapezoid is greater than 600 Å, and the included angle between the waist and the lower base of the inverted trapezoid is greater than 105 degrees.

[0066] Specifically, since the first lower electrode interconnect via 141 located in the memory cell array region 80 corresponds to the subsequently formed first upper electrode interconnect via 181 located in the memory cell array region 80, and the second lower electrode interconnect via 142 located in the peripheral circuit region 90 corresponds to the subsequently formed second upper electrode interconnect via 182 located in the peripheral circuit region 90, the first lower electrode interconnect via 141 and the second lower electrode interconnect via 142, as well as the first upper electrode interconnect via 181 and the second upper electrode interconnect via 182, can be etched based on the first patterned photomask layer 391.

[0067] Figure 3C A schematic diagram of the semiconductor cross-sectional structure of a second lower electrode metal layer 1511 deposited according to an embodiment of this application is shown.

[0068] like Figure 3C As shown, a second lower electrode metal layer 1511 is deposited in the first region lower electrode interconnect via 141, the second region lower electrode interconnect via 142, and on the upper surface of the first dielectric layer 130 through a thin film deposition process, so that the second lower electrode metal layer 1511 fills the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0069] In the embodiments of this application, during the deposition of the second lower electrode metal layer 1511, the second lower electrode metal layer 1511 may be deposited only on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, or the second lower electrode metal layer 1511 may be deposited on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, as well as on a portion of the upper surface of the first dielectric layer 130. However, the deposited second lower electrode metal layer 1511 must at least completely fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0070] Figure 3D A schematic diagram of a semiconductor cross-sectional structure of a second lower electrode metal layer 1511 planarization process according to an embodiment of this application is shown.

[0071] like Figure 3D As shown, the second lower electrode metal layer 1511 is planarized to form a first region second lower electrode metal layer 15111 and a second region second lower electrode metal layer 15112. Specifically, the first region second lower electrode metal layer 15111 fills the first region lower electrode interconnect via 141, and the second region second lower electrode metal layer 15112 fills the second region lower electrode interconnect via 142. The upper surfaces of the first region second lower electrode metal layer 15111, the second region second lower electrode metal layer 15112, and the upper surface of the first dielectric layer 130 are flush.

[0072] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0073] Specifically, the first lower electrode metal layer 15111 of the first region is electrically connected to the first lower electrode metal connecting layer 111, and the second lower electrode metal layer 15112 of the second region is electrically connected to the second lower electrode metal connecting layer 112.

[0074] In this embodiment, the bottom of the second lower electrode metal layer 15111 in the first region is in contact with the upper surface of the lower electrode metal connecting layer 111 in the first region, and the bottom of the second lower electrode metal layer 15112 in the second region is in contact with the upper surface of the lower electrode metal connecting layer 112 in the second region.

[0075] Specifically, the first lower electrode metal layer 15111 and the second lower electrode metal layer 15112 in the first region can be a single layer or multiple layers. The first lower electrode metal layer 15111 and the second lower electrode metal layer 15112 in the first region can be one or more of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), etc. In the embodiments of this application, the first region second lower electrode metal layer 15111 and the first region lower electrode metal connecting layer 111 can be made of the same metal material, and the second region second lower electrode metal layer 15112 and the second region lower electrode metal connecting layer 112 can be made of the same metal material, so that the first region second lower electrode metal layer 15111 and the first region lower electrode metal connecting layer 111 are in close contact, and the second region second lower electrode metal layer 15112 and the second region lower electrode metal connecting layer 112 are in close contact, avoiding the formation of holes between the two materials due to the different coefficients of thermal expansion caused by thermal expansion and contraction.

[0076] Figure 3E A schematic diagram of the semiconductor cross-sectional structure forming the memory cell stack layer 350 and sidewall 159 according to an embodiment of this application is shown.

[0077] like Figure 3EAs shown, a memory cell stack layer 350 is deposited on the upper surface of the exposed first dielectric layer 130, the upper surface of the second lower electrode metal layer 15111 in the first region, and the upper surface of the second lower electrode metal layer 15112 in the second region. The memory cell stack layer 350 includes the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Next, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 are etched using photolithography and etching processes. Then, sidewalls 159 are deposited on the etched second switching layer 152, the second upper electrode metal layer 153, the upper electrode hard mask layer 154, and the exposed areas of the first dielectric layer 130. The deposited sidewalls 159 and the second lower electrode metal layer 1512 are etched to stop the etching process on the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap the memory cell stack layer 350 from the side.

[0078] In the embodiments of this application, during the etching process of the deposited sidewall 159 and the second lower electrode metal layer 1512, some or all of the second lower electrode metal layer 15112 in the second region may be consumed due to over-etching. In this embodiment, a portion of the second lower electrode metal layer 15112 in the second region is consumed, and the remaining portion forms the second functional layer 342.

[0079] At this time, the materials of the second lower electrode metal layer 15111 in the first region and the functional layer 342 in the second region are the same, and the thickness of the second lower electrode metal layer 15111 in the first region is not less than the thickness of the functional layer 342 in the second region.

[0080] The functions of the second functional layer 342 include at least the following two aspects. Taking the lower electrode metal connection layer 112 of the second region as a copper conductor as an example.

[0081] First, the second functional layer 342 is used as a barrier layer here. The second functional layer 342 covers the copper conductor. After the upper surface of the second lower electrode metal connection layer 112 is exposed to copper (i.e. after the second lower electrode interconnect via 142 is formed), by covering the second functional layer 342, the copper on the upper surface of the second lower electrode metal connection layer 112 can be prevented from being oxidized or the oxidation diffusion can be slowed down. At the same time, it can increase the QTime (Queue Time or process time interval) of the fabrication process.

[0082] Secondly, the second functional layer 342 can be used as an etching stop layer. When etching is performed on the top of the second functional layer 342, it serves as a stop layer for the etching process, thereby effectively controlling the accuracy of etching stop and preventing the copper wire (i.e., the second lower electrode metal connection layer 112) from being etched, which would lead to the damage of the copper wire.

[0083] Preferably, the thickness of the second functional layer 342 is between 10 Å and 50 Å. If the thickness is less than 10 Å, the second functional layer 342 will be too thin, posing a risk of being etched through and causing it to fail. Furthermore, a second functional layer 342 that is too thin is too costly to manufacture in actual production. If the thickness is greater than 50 Å, the second functional layer 342 will significantly increase the resistivity of the conductive metal interconnects in the peripheral circuit region 90. Therefore, a thickness of 10 Å to 50 Å for the second functional layer 342 avoids a significant increase in resistivity, prevents etching through and thus failure, and facilitates fabrication in actual production.

[0084] Specifically, the second lower electrode metal layer 1512 may be made of the same material or a different material from the aforementioned second lower electrode metal layer 15111 in the first region. The material used for the second lower electrode metal layer 1512 may include one or more of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al).

[0085] Specifically, the material of the second switching layer 152 may include metal oxides such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), and tantalum oxide (TaO), which are used to change the resistance between the second lower electrode metal layer 1512 and the second upper electrode metal layer 153. In the embodiments of this application, the second switching layer 152 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0086] Specifically, the material used for the second upper electrode metal layer 153 may include one or more of gold (Au), platinum (Pt), copper (Cu), and aluminum (Al). In the embodiments of this application, the second upper electrode metal layer 153 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0087] Specifically, the upper electrode hard mask layer 154 may be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonoxylate, and silicon carbonitride. The upper electrode hard mask layer 154 is used to protect the underlying second upper electrode metal layer 153 during subsequent fabrication processes. The upper electrode hard mask layer 154 may be a non-conductive layer.

[0088] Figure 3F A schematic diagram of the semiconductor cross-sectional structure forming the second dielectric layer 170 and the first patterned photomask layer 391 according to an embodiment of this application is shown.

[0089] like Figure 3F As shown, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack 350, the surface of the exposed sidewall 159, and the upper surface of the second region functional layer 342. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the memory cell stack 350 and fills the remaining space of the second region lower electrode interconnect via 142.

[0090] Then, a first patterned photomask layer 391 is formed over the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0091] Figure 3G This illustration shows a schematic cross-sectional structure of a semiconductor forming a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182, according to an embodiment of this application.

[0092] like Figure 3G As shown, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 and the upper electrode hard mask layer 154 are etched until the corresponding positions of the second upper electrode metal layer 153 are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the second functional layer 342 are exposed. A first region upper electrode interconnect via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154, and a second region upper electrode interconnect via 182 is formed in the second dielectric layer 170. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second functional layer 342. Then, the first patterned photomask layer 391 is removed.

[0093] Specifically, the bottom of the first region upper electrode interconnect via 181 is in contact with the second upper electrode metal layer 153, and the bottom of the second region upper electrode interconnect via 182 is in contact with the second region functional layer 342.

[0094] Figure 3H This illustration shows a schematic cross-sectional structure of a semiconductor structure forming a first region upper electrode metal interconnect layer 191 and a second region upper electrode metal interconnect layer 192, according to an embodiment of this application.

[0095] like Figure 3HAs shown, the first region upper electrode interconnect via 181 is filled with a first region upper electrode metal connection layer 191, and the second region upper electrode interconnect via 182 is filled with a second region upper electrode metal connection layer 192. The first region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom is in contact with the memory cell stack layer 350; the second region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second region functional layer 342.

[0096] Specifically, the second upper electrode metal layer 153 is electrically connected to the first region upper electrode metal connection layer 191, and the second region functional layer 342 is electrically connected to the second region upper electrode metal connection layer 192.

[0097] Specifically, the second dielectric layer 170 may be made of silicon nitride (Si3N4). In the embodiments of this application, the second dielectric layer 170 may also be made of other materials depending on the actual application scenario and process requirements, and no limitation is made here.

[0098] Specifically, the second dielectric layer 170 can isolate the second upper electrode metal layer 153 and the first region upper electrode metal connection layer 191 from the non-connection area, and isolate the second region upper electrode metal connection layer 192 from the non-connection area, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0099] Specifically, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can be made of conductive materials such as copper. In the embodiments of this application, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can also be made of other metals as needed, and are not limited here.

[0100] Figures 4A-4J A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating a method for fabricating a non-volatile two-terminal memory cell according to other embodiments of this disclosure.

[0101] Figure 4A A schematic diagram of the semiconductor cross-sectional structure forming the first patterned photomask layer 391 according to an embodiment of this application is shown.

[0102] like Figure 4A As shown, a multilayer semiconductor structure is provided, and a first patterned photomask layer 391 is formed on top of the semiconductor structure. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed lower electrode interconnect vias 141 in the first region of the memory cell array region 80 and the lower electrode interconnect vias 142 in the second region of the peripheral circuit region 90.

[0103] Specifically, the semiconductor structure is processed to form the following structure in sequence: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, and a first patterned photomask layer 391.

[0104] The lower electrode metal connection layer 110 includes a first lower electrode metal connection layer 111 located in the memory cell array region 80 and a second lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are separated by a lower dielectric layer 120 to prevent short circuits from forming between the two first lower electrode metal connection layers 111, between the two second lower electrode metal connection layers 112, or between the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112. Simultaneously, the upper surfaces of the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first lower electrode metal connection layer 111, the second lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0105] The number of lower electrode metal connection layers 111 in the first region can be one or more. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be the same or different. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be copper. The main advantages of copper compared to other metals are its high electrical conductivity, high thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, other metals can also be used for the lower electrode metal connection layers 111 and 112 in the first region as needed, and this is not limited here.

[0106] Specifically, the material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, or a low-k dielectric material. More specifically, the low-k dielectric material can be porous silicon dioxide, silicon fluoride glass, etc. In the embodiments of this application, the lower dielectric layer 120 can also be selected from other materials according to the actual application scenario and process requirements, and is not limited here.

[0107] Specifically, various known processes can be used to fabricate the lower dielectric layer 120 around the lower electrode metal interconnect layer 110, and the embodiments of this application are not limited in this respect.

[0108] For example, a lower dielectric layer 120 is made to surround a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, exposing the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112. This part of the process includes: first, providing a lower dielectric layer 120, forming a patterned photomask layer on the lower dielectric layer 120, selectively exposing photoresist using an exposure machine, developing to remove exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing remaining photoresist, and continuing to form the desired first groove located in the memory cell array region 80 and the second groove located in the peripheral circuit region 90 by dry etching or wet etching, wherein the number of first grooves can be single or multiple. Then, metal material is deposited in the first groove and the second groove. Finally, the metal material is planarized to form a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, such that the upper surfaces of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush. Thus, a lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 is obtained, and the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112 are exposed.

[0109] Specifically, the lower electrode metal connection layer 110, surrounded by the lower dielectric layer 120, can isolate the first region lower electrode metal connection layer 111 from other unrelated parts; it can also isolate the second region lower electrode metal connection layer 112 from other unrelated parts. This prevents current from flowing along unwanted paths, avoiding short circuits and leakage. For example, it prevents direct connections between the two first region lower electrode metal connection layers 111, between the two second region lower electrode metal connection layers 112, or between the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112, thus avoiding short circuits.

[0110] Specifically, the first dielectric layer 130 is formed on the upper surface of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the exposed lower dielectric layer 120. The first dielectric layer 130 can be formed by a thin film deposition process. The first dielectric layer 130 can be a single layer or multiple layers. For example, the first dielectric layer 130 can include a first dielectric layer and a first dielectric layer stacked sequentially. The first dielectric layer can be a silicon nitride (SiN) thin film or a doped silicon carbide (NDC) thin film, and the first dielectric layer can be a low-temperature oxide (LTO), a silicon dioxide layer (SiO2), or a silicon rich oxide (SRO), etc. In the embodiments of this application, the first dielectric layer and the first dielectric layer can also be made of other materials according to the actual application scenario and process requirements, which are not limited here.

[0111] The first dielectric layer 130 can protect the first stacked layer 250A in the first region and the functional layer 342 in the second region (including the first stacked layer 250B in the second region) from external damage.

[0112] Specifically, a first patterned photomask layer 391 is formed above the first dielectric layer 130. The first patterned photomask layer 391 can be made using either positive or negative photoresist. The first patterned photomask layer 391 can be formed using various known processes, and this application embodiment is not limited in this respect. For example, a photomask layer is coated above the first dielectric layer 130, and the photomask layer is exposed to form exposed and unexposed areas. Then, the exposed photomask layer is developed to remove the photomask layer in the exposed or unexposed areas, forming the first patterned photomask layer 391. When a positive photoresist is used, the photomask layer in the exposed areas changes from being insoluble in the developer to being soluble in the developer and is removed during development. When a negative photoresist is used, the photomask layer in the exposed areas changes from being soluble in the developer to being insoluble in the developer and is not removed during development. Thus, when a negative photoresist is used, the photomask layer in the unexposed areas is removed.

[0113] Figure 4B This illustration shows a schematic cross-sectional structure of a semiconductor forming a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142, according to an embodiment of this application.

[0114] like Figure 4BAs shown, based on the first patterned photomask layer 391, the exposed first dielectric layer 130 is etched to form a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 in the first dielectric layer 130, and the first patterned photomask layer 391 is removed.

[0115] Specifically, the first region lower electrode interconnect via 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first region lower electrode metal connection layer 111. The second region lower electrode interconnect via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. Both the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum-shaped structure or a trapezoidal structure. In the embodiments of this application, the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can also be selected with other structural shapes according to the actual application scenario and process requirements, which are not limited here.

[0116] In this embodiment, the cross-sectional shape of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 is an inverted trapezoid. The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid. The width of the upper base of the inverted trapezoid is greater than 1000 Å, the width of the lower base of the inverted trapezoid is greater than 600 Å, and the included angle between the waist and the lower base of the inverted trapezoid is greater than 105 degrees.

[0117] Specifically, since the first lower electrode interconnect via 141 located in the memory cell array region 80 corresponds to the subsequently formed first upper electrode interconnect via 181 located in the memory cell array region 80, and the second lower electrode interconnect via 142 located in the peripheral circuit region 90 corresponds to the subsequently formed second upper electrode interconnect via 182 located in the peripheral circuit region 90, the first lower electrode interconnect via 141 and the second lower electrode interconnect via 142, as well as the first upper electrode interconnect via 181 and the second upper electrode interconnect via 182, can be etched based on the first patterned photomask layer 391.

[0118] Figure 4C This illustration shows a schematic diagram of a semiconductor cross-sectional structure in which a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 are deposited sequentially according to an embodiment of this application.

[0119] like Figure 4CAs shown, a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 are sequentially deposited in the first region lower electrode interconnect via 141, the second region lower electrode interconnect via 142, and on the upper surface of the first dielectric layer 130 through a thin film deposition process, so that the deposited first lower electrode metal layer 251, first switching layer 252, and first upper electrode metal layer 253 at least fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0120] In the embodiments of this application, during the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in sequence, the material may be deposited only on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, or deposited on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, as well as on a portion of the upper surface of the first dielectric layer 130. However, the deposited material must at least fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, and ensure that the first switching layer 252 is located between the first lower electrode metal layer 251 and the first upper electrode metal layer 253, separating the two.

[0121] In the embodiments of this application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure, and the material used may be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. Alternatively, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 may use the same metal material, thereby ensuring close contact between the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 and avoiding the formation of voids.

[0122] When the first lower electrode metal layer 251 adopts a two-layer structure, it may include a first lower electrode metal layer 1 and a first lower electrode metal layer 2 covering the upper surface of the first lower electrode metal layer 1. In this case, the first lower electrode metal layer 1 can be made of TiN (titanium nitride), and the first lower electrode metal layer 2 can be made of W (tungsten). The first lower electrode metal layer 2 can serve as a connecting layer between the first lower electrode metal layer 1 and the first switching layer. Furthermore, by using W (tungsten) as the material for the first lower electrode metal layer 2, not only is good thermal conductivity and low resistance ensured, but heat can also be quickly conducted, promoting heat dissipation and reducing heat generation, thereby minimizing thermal damage to the fabricated non-volatile two-sided memory cell. Using W (tungsten) as the material for the first lower electrode metal layer 2 also ensures higher inertness, preventing chemical reactions between the first lower electrode metal layer 2 and the first switching layer, thus ensuring the thermal stability of the fabricated non-volatile two-sided memory cell.

[0123] In the embodiments of this application, the material of the first switching layer 252 may be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), or tantalum oxide (TaO), which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 may also be selected from other materials according to the actual application scenario and process requirements, which are not limited here.

[0124] In the embodiments of this application, the first upper electrode metal layer 253 may be a single-layer or multi-layer structure.

[0125] When the first upper electrode metal layer 253 adopts a two-layer structure, the first upper electrode metal layer 253 may include a first upper electrode metal layer one and a first upper electrode metal layer two covering the surface of the first upper electrode metal layer one. In this case, the material used in the first upper electrode metal layer one is more easily oxidized than the material used in the first upper electrode metal layer two. The material used in the first upper electrode metal layer one may be AlN (aluminum nitride), and the material used in the first upper electrode metal layer two may be TiN (titanium nitride).

[0126] The material used in the first upper electrode metal layer is more easily oxidized than the material used in the second upper electrode metal layer. The purpose is that, as the upper electrode of the non-volatile two-sided memory cell, the first upper electrode metal layer provides metal ions to the first switching layer 252, but also prevents the first upper electrode metal layer from being oxidized and causing adverse effects, such as reduced conductivity. Therefore, the second upper electrode metal layer, which is less prone to oxidation than the first upper electrode metal layer, needs to cover the first upper electrode metal layer, thereby reducing the possibility of the first upper electrode metal layer being oxidized and ensuring that the characteristics of the non-volatile two-sided memory cell are not affected.

[0127] Other materials can also be used for the first upper electrode metal layer one and the first upper electrode metal layer two.

[0128] Figure 4D A schematic diagram of the semiconductor cross-sectional structure before planarization is shown in an embodiment of this application.

[0129] like Figure 4D As shown, a stop line 50 is set before planarization. When the semiconductor structure reaches the height of the stop line 50 during planarization, the planarization process stops. The height of the stop line 50 is not higher than the upper surface of the first dielectric layer 130, so that after planarization, the semiconductor structure forms a first stacked layer that fills the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0130] Figure 4E A schematic diagram of the semiconductor cross-sectional structure after planarization processing according to an embodiment of this application is shown.

[0131] like Figure 4E As shown, a planarization process is used to expose the upper surface of the first dielectric layer 130, forming a first stacked layer 250A in the first region and a first stacked layer 250B in the second region. Specifically, the first stacked layer 250A in the first region fills the lower electrode interconnect via 141 in the first region, and the first stacked layer 250B in the second region fills the lower electrode interconnect via 142 in the second region. The upper surfaces of the first stacked layer 250A in the first region, the upper surfaces of the first stacked layer 250B in the second region, and the upper surface of the first dielectric layer 130 are flush.

[0132] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0133] Specifically, the first stacked layer 250A in the first region is electrically connected to the lower electrode metal connection layer 111 in the first region, and the first stacked layer 250B in the second region is electrically connected to the lower electrode metal connection layer 112 in the second region.

[0134] In this embodiment, the bottom of the first stacked layer 250A in the first region is in contact with the upper surface of the lower electrode metal connection layer 111 in the first region, and the bottom of the first stacked layer 250B in the second region is in contact with the upper surface of the lower electrode metal connection layer 112 in the second region.

[0135] Figure 4F A schematic diagram of the semiconductor cross-sectional structure forming the second functional layer 342 according to an embodiment of this application is shown.

[0136] like Figure 4F As shown, after planarization, the first stacked layer 250B of the second region is etched, and the etching consumes part or all of the first stacked layer 250B of the second region.

[0137] In an embodiment of this application, based on a specific patterned photomask layer, the first stacked layer 250B of the second region is etched, and the etching process is stopped at the upper surface of the first lower electrode metal layer 251 of the first stacked layer 250B of the second region, with the remaining portion forming the second region functional layer 342. Then the patterned photomask layer is removed.

[0138] The pattern of the patterned photomask can be used to etch the first stacked layer 250B in the second region, and its material and the specific method of formation are not limited.

[0139] At this time, the materials of the first lower electrode metal layer 251 and the second functional layer 342 are the same, and the thickness of the first lower electrode metal layer 251 is not less than the thickness of the second functional layer 342.

[0140] The functions of the second functional layer 342 include at least the following two aspects. Taking the lower electrode metal connection layer 112 of the second region as a copper conductor as an example.

[0141] First, the second functional layer 342 is used as a barrier layer here. The second functional layer 342 covers the copper conductor. After the upper surface of the second lower electrode metal connection layer 112 is exposed to copper (i.e. after the second lower electrode interconnect via 142 is formed), by covering the second functional layer 342, the copper on the upper surface of the second lower electrode metal connection layer 112 can be prevented from being oxidized or the oxidation diffusion can be slowed down. At the same time, it can increase the QTime (Queue Time or process time interval) of the fabrication process.

[0142] Secondly, the second functional layer 342 can be used as an etching stop layer. When etching is performed on the top of the second functional layer 342, it serves as a stop layer for the etching process, thereby effectively controlling the accuracy of etching stop and preventing the copper wire (i.e., the second lower electrode metal connection layer 112) from being etched, which would lead to the damage of the copper wire.

[0143] Preferably, the thickness of the second functional layer 342 is between 10 Å and 50 Å. If the thickness is less than 10 Å, the second functional layer 342 will be too thin, posing a risk of being etched through and causing it to fail. Furthermore, a second functional layer 342 that is too thin is too costly to manufacture in actual production. If the thickness is greater than 50 Å, the second functional layer 342 will significantly increase the resistivity of the conductive metal interconnects in the peripheral circuit region 90. Therefore, a thickness of 10 Å to 50 Å for the second functional layer 342 avoids a significant increase in resistivity, prevents etching through and thus failure, and facilitates fabrication in actual production.

[0144] Figure 4G A schematic diagram of the semiconductor cross-sectional structure forming the second dielectric layer 170 according to an embodiment of this application is shown.

[0145] like Figure 4G As shown, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the upper surface of the first stacked layer 250A in the first region, and the upper surface of the functional layer 342 in the second region. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the first stacked layer 250A in the first region and fills the remaining space of the lower electrode interconnect via 142 in the second region.

[0146] Figure 4H A schematic diagram of the semiconductor cross-sectional structure forming the first patterned photomask layer 391 according to an embodiment of this application is shown.

[0147] like Figure 4H As shown, a first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0148] Figure 4I This illustration shows a schematic cross-sectional structure of a semiconductor forming a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182, according to an embodiment of this application.

[0149] like Figure 4IAs shown, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 is etched until the corresponding positions of the first stacked layer 250A in the first region are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the functional layer 342 in the second region are exposed. First region upper electrode interconnect vias 181 and 182 are formed in the second dielectric layer 170. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the first stacked layer 250A in the first region; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the functional layer 342 in the second region. Then, the first patterned photomask layer 391 is removed.

[0150] Specifically, the bottom of the first upper electrode interconnect via 181 is in contact with the first upper electrode metal layer 253, and the bottom of the second upper electrode interconnect via 182 is in contact with the second functional layer 342.

[0151] Figure 4J This illustration shows a schematic cross-sectional structure of a semiconductor structure forming a first region upper electrode metal interconnect layer 191 and a second region upper electrode metal interconnect layer 192, according to an embodiment of this application.

[0152] like Figure 4J As shown, the first region upper electrode interconnect via 181 is filled with a first region upper electrode metal interconnect layer 191, and the second region upper electrode interconnect via 182 is filled with a second region upper electrode metal interconnect layer 192. The first region upper electrode metal interconnect layer 191 is located in the memory cell array region 80, and its bottom is in contact with the first stacked layer 250A of the first region; the second region upper electrode metal interconnect layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the functional layer 342 of the second region. The entire lower surface of the bottom of the first region upper electrode metal interconnect layer 191 is in contact with the upper surface of the first upper electrode metal layer 253, so that the first region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 253 are in full contact, and short circuit is prevented from caused by the partial contact of the bottom of the first region upper electrode metal interconnect layer 191 with the upper surface of the first lower electrode metal layer 251.

[0153] Specifically, the first upper electrode metal layer 253 is electrically connected to the first region upper electrode metal connection layer 191, and the second region functional layer 342 is electrically connected to the second region upper electrode metal connection layer 192.

[0154] Specifically, the second dielectric layer 170 may be made of silicon nitride (Si3N4). In the embodiments of this application, the second dielectric layer 170 may also be made of other materials depending on the actual application scenario and process requirements, and no limitation is made here.

[0155] Specifically, the second dielectric layer 170 can isolate the first region upper electrode metal connection layer 191 and the second region upper electrode metal connection layer 192 from the non-connection area, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0156] Specifically, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can be made of conductive materials such as copper. In the embodiments of this application, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can also be made of other metals as needed, and are not limited here.

[0157] In summary, by utilizing the non-volatile two-terminal memory unit provided above, this embodiment of the present disclosure forms a second functional layer 342 between the second region lower electrode metal connection layer 112 and the second region upper electrode metal connection layer 192, thereby achieving electrical connection between the second region lower electrode metal connection layer 112 and the second region upper electrode metal connection layer 192 through the second functional layer 342. Since the formation of the second functional layer 342 precedes the formation of the second region upper electrode metal connection layer 192, the copper on the upper surface of the second region lower electrode metal connection layer 112 can be prevented from oxidation or its oxidation diffusion can be slowed down, while simultaneously increasing the QTime (Queue Time) of the fabrication process. Because the second functional layer 342 covers the second region lower electrode metal connection layer 112, damage to the second region lower electrode metal connection layer 112 during etching can be prevented. Since the material of the second functional layer 342 is conductive, the electrical connection between the lower electrode metal connection layer 112 and the upper electrode metal connection layer 192 of the second region is still guaranteed after the addition of the second functional layer 342.

[0158] In one embodiment of this application, a memory is also provided, which includes one or more non-volatile dual-ended memory cells as described in the embodiments of this application. This memory employs the aforementioned non-volatile dual-ended memory cells, thereby improving the yield rate of the memory.

[0159] In one embodiment of this application, an electronic device is also provided, which includes the memory described in the embodiment of this application. This electronic device uses the aforementioned memory, thus reducing the possibility of quality problems occurring in the memory within the electronic device.

[0160] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A non-volatile two-ended storage cell, comprising a second region, characterized in that, The second region includes a second region lower electrode metal connection layer (112), a second region functional layer (342), and a second region upper electrode metal connection layer (192). The second region functional layer (342) is electrically connected to the second region lower electrode metal connection layer (112) and the second region upper electrode metal connection layer (192), respectively.

2. The non-volatile two-terminal storage unit according to claim 1, characterized in that, The second region also includes a first dielectric layer (130), in which a second region lower electrode interconnect via (142) is formed, and a second region functional layer (342) is located in the second region lower electrode interconnect via (142), with the bottom of the second region functional layer (342) in contact with the upper surface of the second region lower electrode metal connection layer (112).

3. The non-volatile two-terminal storage unit according to claim 2, characterized in that, The upper surface of the second functional layer (342) is lower than the upper surface of the first dielectric layer (130).

4. The non-volatile two-terminal storage unit according to claim 3, characterized in that, The second region also includes a second dielectric layer (170), in which a second region upper electrode interconnect via (182) is formed, and a second region upper electrode metal connection layer (192) is located in the second region upper electrode interconnect via (182), and the bottom of the second region upper electrode metal connection layer (192) is in contact with the upper surface of the second region functional layer (342).

5. The non-volatile two-terminal storage unit according to claim 4, characterized in that, The bottom of the upper electrode metal connection layer (192) of the second region is located in the lower electrode interconnect via (142) of the second region and is in contact with the upper surface of the functional layer (342) of the second region.

6. The non-volatile two-terminal storage cell according to claim 4 or 5, further comprising a first region, characterized in that, The first region includes a first region lower electrode metal connection layer (111), a first region upper electrode metal connection layer (191), and a first dielectric layer (130). A first region lower electrode interconnect via (141) is formed in the first dielectric layer (130), wherein the material in the first region lower electrode interconnect via (141) is electrically connected to the first region lower electrode metal connection layer (111) and the first region upper electrode metal connection layer (191), respectively.

7. The non-volatile two-terminal storage unit according to claim 6, characterized in that, The material in the first region lower electrode interconnect via (141) includes a first region second lower electrode metal layer (15111), the bottom of the first region second lower electrode metal layer (15111) is in contact with the upper surface of the first region lower electrode metal connection layer (111).

8. The non-volatile two-terminal storage unit according to claim 7, characterized in that, The first region also includes a memory cell stack layer (350), the bottom of which is in contact with the upper surface of the second lower electrode metal layer (15111) of the first region.

9. The non-volatile two-terminal storage unit according to claim 8, characterized in that, The storage cell stack layer (350) includes a second lower electrode metal layer (1512), a second switching layer (152), a second upper electrode metal layer (153), and an upper electrode hard mask layer (154) stacked in sequence.

10. The non-volatile two-terminal storage unit according to claim 9, characterized in that, The first region also includes a second dielectric layer (170), in which a first region upper electrode interconnect via (181) is formed, and a first region upper electrode metal connection layer (191) is located in the first region upper electrode interconnect via (181), and the bottom of the first region upper electrode metal connection layer (191) is in contact with the memory cell stack layer (350).

11. The non-volatile two-terminal storage unit according to claim 10, characterized in that, The first region upper electrode metal connection layer (191) penetrates the upper electrode hard mask layer (154) of the memory cell stack layer (350), and the bottom of the first region upper electrode metal connection layer (191) is in contact with the upper surface of the second upper electrode metal layer (153).

12. The non-volatile two-terminal storage unit according to claim 7, characterized in that, The thickness of the second lower electrode metal layer (15111) in the first region is greater than or equal to the thickness of the functional layer (342) in the second region.

13. The non-volatile two-terminal storage unit according to claim 7, characterized in that, The material of the second lower electrode metal layer (15111) in the first region is the same as the material of the functional layer (342) in the second region.

14. The non-volatile two-terminal storage cell according to claim 6, characterized in that, The material in the first region lower electrode interconnect via (141) includes a first region first stacked layer (250A), the bottom of which is in contact with the upper surface of the first region lower electrode metal connection layer (111).

15. The non-volatile two-terminal storage cell according to claim 14, characterized in that, The first region also includes a second dielectric layer (170), in which a first region upper electrode interconnect via (181) is formed, and a first region upper electrode metal connection layer (191) is located in the first region upper electrode interconnect via (181), and the bottom of the first region upper electrode metal connection layer (191) is in contact with the upper surface of the first region first stacked layer (250A).

16. The non-volatile two-terminal storage cell according to claim 15, characterized in that, The first stacked layer (250A) of the first region includes a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) stacked in sequence, and the bottom of the upper electrode metal connection layer (191) of the first region is in contact with the upper surface of the first upper electrode metal layer (253).

17. The non-volatile two-terminal storage cell according to claim 16, characterized in that, The thickness of the first lower electrode metal layer (251) is greater than or equal to the thickness of the second functional layer (342).

18. The non-volatile two-terminal storage cell according to claim 16, characterized in that, The material of the first lower electrode metal layer (251) is the same as the material of the second functional layer (342).

19. The non-volatile two-terminal storage cell according to claim 10, characterized in that, The first lower electrode interconnect via (141) and the second lower electrode interconnect via (142) in the first dielectric layer (130), and the first upper electrode interconnect via (181) and the second upper electrode interconnect via (182) in the second dielectric layer (170) are all formed based on the first patterned photomask layer (391).

20. The non-volatile two-terminal storage unit according to claim 2, characterized in that, The cross-sectional shape of the lower electrode interconnect via (142) in the second region is an inverted trapezoid.

21. The non-volatile two-terminal storage cell according to claim 20, characterized in that, The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, the width of the upper base of the inverted trapezoid is greater than 1000 Å, and the width of the lower base of the inverted trapezoid is greater than 600 Å.

22. The non-volatile two-terminal storage unit according to claim 20, characterized in that, The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

23. A memory, characterized in that, The memory includes one or more non-volatile two-ended memory cells according to any one of claims 1-22.

24. An electronic device, characterized in that, The electronic device includes the memory as described in claim 23.

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