Optical debugging module

Abstract

The utility model relates to an optical debugging module, which comprises a processor module, an FPGA (Field Programmable Gate Array) module, an optical port module, an Ethernet interface module, a power supply module, a debugging interface module, a storage module and a clock synchronization module, the clock synchronization module comprises a clock source, a phase-locked loop and a clock distribution chip; the phase-locked loop receives an initial clock signal output by the clock source and generates an adjusted clock signal; the clock distribution chip distributes the adjusted clock signal generated by the phase-locked loop to the first output channel and the second output channel; the clock signal output from the first output channel is input to the processor module; the clock signal output from the second output channel is input to the FPGA module; the FPGA module, the optical port module, the Ethernet interface module, the power supply module, the debugging interface module and the storage module are all connected to the processor module. According to the utility model, the time sequence cooperation between the processor and the FPGA can be optimized, and stricter time sequence constraint conditions under various communication protocol scenes can be satisfied.

Description

Technical Field

[0001] This utility model relates to the field of optical communication technology, and in particular to an optical debugging module. Background Technology

[0002] With the rapid development of smart grid technology, optical modulation modules capable of integrating multiple communication protocols are being developed and optimized to better achieve direct interconnection with modern smart substation control and protection systems. Optical modulation modules typically include a processor module and an FPGA module connected to the processor module for high-speed data processing and logic control. However, in scenarios requiring the integration of multiple communication protocols, the processor must not only efficiently schedule tasks between different protocols but also ensure that each protocol can accurately complete data processing and transmission within a specified time. This requirement presents a significant challenge to the design of existing optical modulators: how to optimize the timing coordination between the processor and the field-programmable gate array (FPGA) while ensuring data transmission accuracy and precision to meet stricter timing constraints, thereby ensuring efficient, stable, and reliable smart grid communication. Utility Model Content

[0003] To address the shortcomings of existing technologies, this invention provides an optical debugging module that optimizes the timing coordination between the processor and the field-programmable gate array (FPGA) while ensuring the accuracy and precision of data transmission. This allows for meeting more stringent timing constraints under various communication protocol scenarios, thereby ensuring the high efficiency, stability, and reliability of smart grid communication.

[0004] Specifically, the optical debugging module of this utility model includes: a processor module, an FPGA module, an optical port module, an Ethernet interface module, a power supply module, a debugging interface module, a storage module, and a clock synchronization module;

[0005] The clock synchronization module includes a clock source, a phase-locked loop, and a clock distribution chip;

[0006] The phase-locked loop receives the initial clock signal output by the clock source and generates an adjusted clock signal;

[0007] The clock distribution chip distributes the adjusted clock signal generated by the phase-locked loop to the first output channel and the second output channel;

[0008] The clock signal output from the first output channel is input to the processor module; the clock signal output from the second output channel is input to the FPGA module.

[0009] The FPGA module, optical port module, Ethernet interface module, power supply module, debug interface module, and storage module are all connected to the processor module.

[0010] Preferably, the crystal oscillator of the clock source is 100MHz to 125MHz, and the root mean square jitter of the clock source is less than 1ps.

[0011] Preferably, the clock distribution chip is a clock distribution chip that supports multiple output level standards; the multiple output level standards include LVCMOS, LVPECL and LVDS.

[0012] Preferably, the clock distribution chip is an IDT 8T49N247 or a TI LMK04828.

[0013] Preferably, the clock synchronization module further includes a first buffer and a second buffer; the clock signal output from the first output channel is input to the processor module via the first buffer; the clock signal output from the second output channel is input to the FPGA module via the second buffer.

[0014] Preferably, the first and second buffers are of the model TI SN65LVPE12 or TI SN65LVDS1.

[0015] Preferably, the processor module integrates IEC61850, IEC60044-8 and Modbus TCP communication protocols; the processor module uses a dual-core A9 ARM processor.

[0016] Preferably, the optical port module adopts an LC 100Mbps optical port.

[0017] Preferably, the Ethernet interface module uses a 100 Mbps RJ45 port.

[0018] Preferably, the debugging interface module adopts an RS232 debugging interface; the storage module includes a TF card slot.

[0019] Compared with the prior art, the advantages of this utility model are:

[0020] 1. By adding a high-precision clock synchronization signal between the processor and FPGA module in the optical debugging module, the reliability of data transmission can be significantly improved, high-speed data processing can be supported, stringent protocol requirements can be met, the overall performance of the system can be enhanced, the stability and reliability of the system can be improved, the design and debugging can be simplified, and future expansion and upgrades can be supported. This better meets the timing requirements between the processor module and FPGA module that need to integrate multiple communication protocols (e.g., IEC61850, IEC60044-8 and Modbus TCP), and better realizes direct interconnection with modern intelligent substation control and protection systems.

[0021] 2. The phase-locked loop (PLL) can adjust the clock frequency and phase of the initial clock signal generated by the clock source, ensuring the stability and synchronization of the clock signal while reducing jitter. By distributing the clock signal output by the PLL to the processor module and the FPGA module, the delay of the clock signal on different paths can be kept consistent, reducing deviation.

[0022] 3. By enabling the clock distribution chip to have multiple output level standards, the needs of different modules and interfaces can be met, improving system flexibility, signal quality and transmission distance, simplifying design, reducing costs, supporting mixed signal systems, and improving system reliability and fault tolerance, thereby better adapting to the needs of optical debugging modules that require handling multiple protocols and high-speed signal transmission.

[0023] 4. By adding a buffer after the output channel of the clock distribution chip and providing the output signal of the buffer to the processor module and FPGA module respectively, the driving capability of the clock signal can be enhanced and jitter and reflection during transmission can be reduced. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the optical debugging module of this utility model.

[0025] Figure 2 This is a schematic diagram of the clock synchronization module of this utility model.

[0026] Figure 3 This is a schematic diagram illustrating the application of the optical debugging module of this utility model. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The embodiments described in this application are merely some embodiments of this utility model, not all embodiments. Based on the spirit of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this utility model.

[0028] In one embodiment, the present invention discloses an optical debugging module.

[0029] like Figure 1-2 The optical debugging module includes a processor module, an FPGA module, an optical port module, an Ethernet interface module, a power supply module, a debugging interface module, a storage module, and a clock synchronization module.

[0030] The clock synchronization module includes a clock source, a phase-locked loop, and a clock distribution chip;

[0031] The phase-locked loop receives the initial clock signal output by the clock source and generates an adjusted clock signal;

[0032] The clock distribution chip distributes the adjusted clock signal generated by the phase-locked loop to the first output channel and the second output channel;

[0033] The clock signal output from the first output channel is input to the processor module; the clock signal output from the second output channel is input to the FPGA module.

[0034] The FPGA module, optical port module, Ethernet interface module, power supply module, debug interface module, and storage module are all connected to the processor module.

[0035] By adding a high-precision clock synchronization signal between the processor and FPGA module in the optical debugging module, the reliability of data transmission can be significantly improved, high-speed data processing can be supported, stringent protocol requirements can be met, the overall performance of the system can be enhanced, the stability and reliability of the system can be improved, the design and debugging can be simplified, and future expansion and upgrades can be supported. This better meets the needs of processor modules and FPGA modules that require the integration of multiple communication protocols (e.g., IEC61850, IEC60044-8 and Modbus TCP).

[0036] Furthermore, the phase-locked loop (PLL) can adjust the clock frequency and phase of the initial clock signal generated by the clock source, ensuring the stability and synchronization of the clock signal while reducing jitter. By distributing the clock signal output by the PLL to the processor module and the FPGA module, the delay of the clock signal on different paths can be kept consistent, reducing deviation.

[0037] Preferably, the crystal oscillator of the clock source is between 100MHz and 125MHz, and the root mean square jitter of the clock source is less than 1ps. By selecting the above parameters, it can be ensured that the clock source provides a stable reference clock signal.

[0038] More preferably, the clock distribution chip supports multiple output level standards; these multiple output level standards include LVCMOS, LVPECL, and LVDS. Enabling the clock distribution chip to support multiple output level standards can meet the needs of different modules and interfaces, improving system flexibility, signal quality, and transmission distance, simplifying design, reducing costs, supporting mixed-signal systems, and improving system reliability and fault tolerance. This better adapts to the needs of optical debugging modules that require handling multiple protocols and high-speed signal transmission.

[0039] More preferably, the clock distribution chip is an IDT 8T49N247 or a TI LMK04828.

[0040] More preferably, the clock synchronization module further includes a first buffer and a second buffer; the clock signal output from the first output channel is input to the processor module via the first buffer; the clock signal output from the second output channel is input to the FPGA module via the second buffer. By adding a buffer after the output channel of the clock distribution chip and providing the signals output by the buffer to the processor module and the FPGA module respectively, the driving capability of the clock signal can be enhanced, and jitter and reflection during transmission can be reduced.

[0041] More preferably, the first and second buffers are of the model TI SN65LVPE12 or TISN65LVDS1.

[0042] More specifically, the processor module, as the core of the circuit board, is responsible for overall data processing and logic control. Preferably, the processor module integrates IEC61850, IEC60044-8, and Modbus TCP communication protocols. This allows the module to communicate directly with smart grid devices without the need for additional communication converters or middleware, thereby simplifying the communication system architecture, reducing costs, and improving system stability and reliability. Figure 3 As shown. Furthermore, the processor module preferably uses a dual-core A9 ARM processor, which features high performance and low power consumption, capable of meeting complex data processing needs.

[0043] The FPGA module is directly connected to the processor module, exchanging data and instructions via a high-speed data bus or dedicated interface. The FPGA module implements specific data processing and logic control functions to assist the processor module in improving overall performance.

[0044] The processor module connects to the optical port module via an internal data bus or a dedicated interface. The optical port module is responsible for transmitting and receiving high-speed fiber optic data. Data transmission between the processor module and the optical port module is achieved through the fiber optic interface, ensuring high-speed and stable data transmission. The optical port module preferably uses an LC 100Mbps optical port module. Preferably, the optical port module includes one IEC60044-8 standard transmit optical port and one receive optical port, supporting high-speed data transmission and meeting the needs of applications with high bandwidth requirements.

[0045] The processor module connects to the Ethernet interface module via an internal data bus or a dedicated interface. The Ethernet interface module preferably uses multiple 100Mbps RJ45 ports for connecting external network devices, supporting 100Mbps network transmission, meeting various network access requirements, and enabling Ethernet data transmission. The processor module communicates with the external network through the Ethernet interface module to exchange and transmit data.

[0046] The power module provides a stable power supply to the entire circuit board. It employs a dual 24V DC power supply design to ensure stable power supply to the circuit board and improve system reliability. Through power lines or a power bus, the power module distributes electrical energy to each module on the circuit board, ensuring that each module can function properly.

[0047] The debug interface module is directly connected to the processor module and is used to communicate with the processor module during development or maintenance to implement debugging functions. The debug interface module preferably uses an RS232 debug interface.

[0048] The storage module is used to store data or programs and can be connected to the processor module via an internal data bus, facilitating data backup or program updates for users. A TF card slot is preferred for the storage module.

[0049] In summary, compared with the prior art, this utility model has the following advantages:

[0050] 1. By adding a high-precision clock synchronization signal between the processor and FPGA module in the optical debugging module, the reliability of data transmission can be significantly improved, high-speed data processing can be supported, stringent protocol requirements can be met, the overall performance of the system can be enhanced, the stability and reliability of the system can be improved, the design and debugging can be simplified, and future expansion and upgrades can be supported. This better meets the timing requirements between the processor module and FPGA module that need to integrate multiple communication protocols (e.g., IEC61850, IEC60044-8 and Modbus TCP), and better realizes direct interconnection with modern intelligent substation control and protection systems.

[0051] 2. The phase-locked loop (PLL) can adjust the clock frequency and phase of the initial clock signal generated by the clock source, ensuring the stability and synchronization of the clock signal while reducing jitter. By distributing the clock signal output by the PLL to the processor module and the FPGA module, the delay of the clock signal on different paths can be kept consistent, reducing deviation.

[0052] 3. By enabling the clock distribution chip to have multiple output level standards, the needs of different modules and interfaces can be met, improving system flexibility, signal quality and transmission distance, simplifying design, reducing costs, supporting mixed signal systems, and improving system reliability and fault tolerance, thereby better adapting to the needs of optical debugging modules that require handling multiple protocols and high-speed signal transmission.

[0053] 4. By adding a buffer after the output channel of the clock distribution chip and providing the output signal of the buffer to the processor module and FPGA module respectively, the driving capability of the clock signal can be enhanced and jitter and reflection during transmission can be reduced.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this utility model should be covered within the protection scope of the claims of this utility model.

Claims

1. An optical debugging module, characterized in that, include: Processor module, FPGA module, optical port module, Ethernet interface module, power supply module, debug interface module, storage module, and clock synchronization module; The clock synchronization module includes a clock source, a phase-locked loop, and a clock distribution chip; The phase-locked loop receives the initial clock signal output by the clock source and generates an adjusted clock signal; The clock distribution chip distributes the adjusted clock signal generated by the phase-locked loop to the first output channel and the second output channel; The clock signal output from the first output channel is input to the processor module; The clock signal output from the second output channel is input to the FPGA module; The FPGA module, optical port module, Ethernet interface module, power supply module, debug interface module, and storage module are all connected to the processor module.

2. The optical debugging module according to claim 1, characterized in that, The crystal oscillator of the clock source is 100MHz to 125MHz, and the root mean square jitter of the clock source is less than 1ps.

3. The optical debugging module according to claim 1, characterized in that, The clock distribution chip supports multiple output level standards; these multiple output level standards include LVCMOS, LVPECL, and LVDS.

4. The light commissioning module of claim 3, wherein, The clock distribution chip is either IDT8T49N247 or TI LMK04828.

5. The optical debugging module according to claim 3, characterized in that, The clock synchronization module further includes a first buffer and a second buffer; the clock signal output from the first output channel is input to the processor module via the first buffer; the clock signal output from the second output channel is input to the FPGA module via the second buffer.

6. The optical commissioning module of claim 5, wherein, The first and second buffers are of model number TI SN65LVPE12 or TI SN65LVDS1.

7. The optical debugging module according to claim 1, characterized in that, The processor module integrates IEC61850, IEC60044-8 and Modbus TCP communication protocols; the processor module uses a dual-core A9 ARM processor.

8. The light commissioning module of claim 1, wherein, The optical port module uses an LC 100Mbps optical port.

9. The optical commissioning module of claim 1, wherein, The Ethernet interface module uses a 100Mbps RJ45 port.

10. The optical commissioning module of claim 1, wherein, The debugging interface module adopts an RS232 debugging interface; the storage module includes a TF card slot.

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