Electronic package
By employing techniques such as redistribution of circuit layers, through-silicon vias, and flip-chip technology, the heterogeneous integration and heat dissipation issues of electronic packaging components have been resolved, thereby improving assembly yield and flexural strength.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- KORE SEMICONDUCTOR INC
- Filing Date
- 2025-05-20
- Publication Date
- 2026-05-08
AI Technical Summary
Existing technologies struggle to integrate heterogeneous wiring structures, circuit structures, interposers, multiple electronic components, and encapsulating colloids, and also struggle to effectively dissipate heat and improve flexural strength.
By employing redistribution circuitry, through-silicon vias, flip-chip technology, and encapsulation technology, combined with conductive bumps, conductive contacts, thermal conductive layers, and heat dissipation components, a composite electronic package is formed, achieving heterogeneous integration and efficient heat dissipation.
It achieves efficient integration and heat dissipation of electronic packaging components, improving assembly yield and flexural strength.
Smart Images
Figure CN224218810U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, and more particularly to an electronic package capable of heterogeneously integrating different components. Background Technology
[0002] To ensure the continued miniaturization and multifunctionality of electronic products, semiconductor devices and electronic packages must constantly evolve towards smaller dimensions. For example, commonly used advanced packaging technologies for semiconductor devices and electronic packages include 2.5D integrated circuit (IC) packaging technology, 3D integrated circuit (IC) packaging technology, and fan-out package on package (FO-PoP) technology.
[0003] Furthermore, 2.5D or 3D integrated circuit packaging technologies using through-silicon vias (TSV) have become an important development direction in the semiconductor industry in recent years due to their advantages of better bandwidth and lower power consumption, as well as their ability to provide higher integration to break through the limits of tiny dimensions (such as micrometers / nanometers).
[0004] However, existing technologies are generally unable to heterogeneously integrate wiring structures, circuit structures, interposers (conductive vias), multiple electronic components and encapsulating colloids and other different components to form composite electronic packages. They are also not easy to use thermally conductive layers and / or heat dissipation components (such as heat sinks and support feet) to quickly dissipate the heat generated by the electronic package or multiple electronic components. Furthermore, most of them cannot make electronic packages have the characteristics of flexural resistance or high flexural strength.
[0005] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Utility Model Content
[0006] In view of the deficiencies in the prior art, this application provides an electronic package, comprising: a wiring structure; an interposer disposed on the wiring structure, the interposer having a plurality of conductive vias for electrically connecting the wiring structure; a plurality of electronic components disposed on the interposer for electrically connecting the plurality of conductive vias; and an encapsulating colloid formed on the wiring structure to cover the interposer and the plurality of electronic components.
[0007] In the aforementioned electronic package, a circuit structure is formed on the interposer, the circuit structure having at least one dielectric layer and at least one bonding dielectric layer as a circuit layer, the wiring structure having at least one insulating layer and at least one bonding insulating layer as a redistributed circuit layer, and the redistributed circuit layer of the wiring structure is electrically connected to the circuit layer of the circuit structure.
[0008] The aforementioned electronic package also includes multiple conductive bumps and multiple conductive contacts. The multiple conductive bumps are formed between the wiring structure and the circuit structure, and the multiple conductive contacts are formed between the multiple conductive through holes of the interposer and the multiple electronic components. The encapsulating colloid further covers the multiple conductive bumps and multiple conductive contacts.
[0009] The aforementioned electronic package may include multiple conductive bumps, wherein the wiring structure has at least one redistributed circuit layer, the circuit structure has at least one circuit layer, and the redistributed circuit layer of the wiring structure is electrically connected to the circuit layer of the circuit structure through multiple conductive bumps.
[0010] The aforementioned electronic package may include multiple conductive contacts, wherein multiple electronic components are connected to an interposer through multiple conductive contacts, and the multiple electronic components are sequentially electrically connected to multiple conductive contacts, multiple conductive vias of the interposer, and wiring structures.
[0011] The aforementioned electronic package may include multiple conductive bumps and multiple conductive contacts, wherein the upper surfaces of the multiple electronic components and the upper surface of the encapsulating colloid are coplanar.
[0012] The aforementioned electronic package may include a plurality of conductors and a substrate, wherein the plurality of conductors are formed between the wiring structure and the substrate to electrically connect the wiring structure and the substrate.
[0013] The aforementioned electronic package may include a thermally conductive layer formed on the upper surface of multiple electronic components.
[0014] The aforementioned electronic package may include a heat sink formed on a thermally conductive layer, with the thermally conductive layer situated between multiple electronic components and the heat sink.
[0015] The aforementioned electronic package may include a heat sink having a heat sink and at least one support foot attached to the heat sink, wherein the heat sink or support foot contacts or is close to a plurality of electronic components.
[0016] As can be seen from the above, this application provides an innovative electronic package that can heterogeneously integrate various components such as wiring structures, circuit structures, interposers (conductive vias), multiple electronic components, and encapsulating colloids to form a composite electronic package, and can also effectively improve the overall performance of the electronic package.
[0017] This application can effectively connect or integrate various components such as wiring structures, circuit structures, interposers (conductive vias), multiple electronic components, and encapsulating colloids in series or in a heterogeneous manner, thereby improving the assembly yield of electronic packages.
[0018] This application can make good use of thermally conductive layers and / or heat dissipation components (such as heat sinks and support feet) to facilitate the rapid dissipation of heat generated by electronic packages or multiple electronic components, and can also effectively improve the heat dissipation performance of electronic packages or multiple electronic components.
[0019] This application can make good use of the heat sink and support feet (such as support brackets) of the heat sink to protect or strengthen the electronic package, and can also give the electronic package the characteristics of flexural resistance or high flexural strength. Attached Figure Description
[0020] Figures 1A to 1F This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.
[0021] Figure 2 This is a cross-sectional schematic diagram of another embodiment of the electronic package of this application.
[0022] Figure 3 This is a cross-sectional schematic diagram of yet another embodiment of the electronic package of this application.
[0023] Explanation of reference numerals in the attached figures
[0024] 1 Electronic package
[0025] 10 carrier boards
[0026] 20. Wiring Structure
[0027] 21 First Relay Line Layer
[0028] 22 Insulation layer
[0029] 23 Conductors
[0030] 30. Circuit Structure
[0031] 31 Line Layer
[0032] 32 Dielectric layers
[0033] 33 Conductive bumps
[0034] 40 Intermediary Board
[0035] 41 Conductive Through-hole
[0036] 50 electronic components
[0037] 51 Upper surface
[0038] 52 Conductive contacts
[0039] 60 Encapsulated Colloid
[0040] 61 Upper surface
[0041] 70 substrate
[0042] 71 Second Relay Line Layer
[0043] 72 Conductive Components
[0044] 80 Thermal conductive layer
[0045] 81 Heat sink
[0046] 82 heat sink
[0047] 83 Support feet. Detailed Implementation
[0048] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0049] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "below," "one," "two," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0050] Figures 1A to 1F This is a cross-sectional schematic diagram of the manufacturing method of the electronic package 1 of this application, and the electronic package 1 may be a composite package structure, etc. At the same time, the "at least one" mentioned in this application means one or more (such as one, two or three), "multiple" means two or more (such as two, three, four or ten or more), "upper surface" may mean the upper side, the first side or the first surface, and "lower surface" may mean the lower side, the second side or the second surface, and the upper surface is relative to the lower surface.
[0051] like Figure 1A As shown, a removable carrier board 10 is provided, and a wiring structure 20 is formed on the carrier board 10 using redistribution layer (RDL) technology. The wiring structure 20 has at least one insulating layer 22, a first redistribution layer (RDL) 21, and at least one first redistribution layer 21 bonded to the insulating layer 22.
[0052] In one embodiment, the wiring structure 20 has a plurality of (e.g., two or three) first redistribution wiring layers 21 and a plurality of (e.g., two or three) insulating layers 22, and the outermost (e.g., the uppermost and lowermost) insulating layer 22 can be exposed to the outermost (e.g., the uppermost and lowermost) first redistribution wiring layers 21.
[0053] In one embodiment, the carrier plate 10 is a removable temporary carrier. The carrier plate 10 is made of materials such as glass, semiconductor (such as silicon), composite polymer materials, etc., and the shape of the carrier plate 10 is such as rectangular, square, circular, polygonal, etc.
[0054] like Figure 1B As shown, a through-silicon via (TSV) technique is used to form an interposer 40 having multiple conductive vias 41, with the multiple conductive vias 41 penetrating the upper and lower surfaces of the interposer 40. Simultaneously, a wiring structure 30 can be formed on the interposer 40 with the multiple conductive vias 41, and the wiring structure 30 can have at least one dielectric layer 32 and at least one wiring layer 31 bonded to the dielectric layer 32, with the wiring layer 31 of the wiring structure 30 electrically connected to the multiple conductive vias 41 of the interposer 40. Then, the first overlay wiring layer 21 of the wiring structure 20 is electrically connected to the wiring layer 31 of the wiring structure 30 through multiple conductive bumps 33.
[0055] In one embodiment, the circuit structure 30 may have multiple (e.g., two or three) circuit layers 31 and multiple (e.g., two or three) dielectric layers 32, and the outermost (e.g., the uppermost and lowermost) dielectric layer 32 may be exposed to the outermost (e.g., the uppermost and lowermost) circuit layers 31.
[0056] In one embodiment, the dielectric layer 32 is, for example, an insulating layer, the conductive bump 33 is, for example, a conductor, a conductive element, a conductive contact, a metal contact, a solder ball, a tin ball, etc., the interposer 40 is, for example, a silicon wafer, a silicon wafer, an interposer, etc., and the conductive via 41 is, for example, a through-silicon via (TSV), etc.
[0057] like Figure 1C As shown, flip-chip technology can be used to place multiple (e.g., at least two) electronic components 50 on an interposer 40 through multiple conductive contacts 52, so that the multiple electronic components 50 are sequentially electrically connected to the multiple conductive contacts 52, the multiple conductive vias 41 of the interposer 40, the circuit layer 31 of the circuit structure 30 and the first redistribution circuit layer 21 of the wiring structure 20, and the multiple electronic components 50 are sequentially electrically connected to each other through the multiple conductive contacts 52, the multiple conductive vias 41 of the interposer 40 and the circuit layer 31 of the circuit structure 30.
[0058] In one embodiment, the electronic component 50 is, for example, an active component, a passive component, or a combination thereof. The active component is, for example, a chip (semiconductor chip), and the passive component is, for example, a resistor, a capacitor, or an inductor. The conductive contact 52 is, for example, a metal contact, a conductive bump, a conductive element, a solder ball, or a solder ball.
[0059] like Figure 1D As shown, a molding technique is used to form an encapsulating colloid 60 on the wiring structure 20 to cover the wiring structure 30 (such as the outermost wiring layer 31 and dielectric layer 32), multiple conductive bumps 33, interposer 40, multiple electronic components 50 (such as chips) and multiple conductive contacts 52, etc., and the upper surface 61 of the encapsulating colloid 60 may be higher than the upper surface 51 of the multiple electronic components 50 (such as chips) (such as the back / non-functional surface).
[0060] like Figure 1E As shown, techniques such as grinding, etching, or photolithography are used to remove... Figure 1D A portion of the encapsulating colloid 60 is used to reduce the thickness of the encapsulating colloid 60 and to expose the upper surface 61 of the encapsulating colloid 60 to the upper surface 51 (e.g., back / non-functional surface) of multiple electronic components 50 (e.g., chips).
[0061] In one embodiment, the upper surfaces 51 of the plurality of electronic components 50 and the upper surface 61 of the encapsulating colloid 60 may be coplanar, and the upper surfaces 51 of the plurality of electronic components 50 are flush with the upper surface 61 of the encapsulating colloid 60. However, in other embodiments, the upper surfaces 51 of the plurality of electronic components 50 and the upper surface 61 of the encapsulating colloid 60 may not be coplanar, and the upper surfaces 51 of the plurality of electronic components 50 are not flush with the upper surface 61 of the encapsulating colloid 60.
[0062] like Figure 1F As shown, remove Figure 1E The carrier board 10 is then used to form a plurality of conductors 23 on the wiring structure 20 to electrically connect to the first redistribution layer 21, thereby obtaining the electronic package 1 of this application.
[0063] In one embodiment, the conductor 23 is, for example, a conductive bump, a conductive element, a conductive contact, a metal contact, a solder ball, a tin ball, etc.
[0064] Figure 2 This is a cross-sectional schematic diagram of another embodiment of the electronic package 1 of this application, and the electronic package 1 may further include a substrate 70 having a second redistribution circuit layer 71 and a plurality of conductive elements 72.
[0065] That is, such as Figure 2As shown, the substrate 70 may be disposed below a plurality of conductors 23, the substrate 70 may have at least one second redistribution layer 71 to electrically connect the plurality of conductors 23, and a plurality of conductive elements 72 may be formed on the substrate 70 to electrically connect the second redistribution layer 71.
[0066] In one embodiment, the substrate 70 may have multiple (e.g., two or three) second redistribution circuit layers 71, with the outermost (e.g., the uppermost and lowermost) second redistribution circuit layer 71 exposed.
[0067] In one embodiment, the substrate 70 is, for example, a glass substrate, a semiconductor substrate (such as a silicon substrate), a ceramic substrate, a multilayer substrate, a printed circuit board (PCB), etc., and the conductive element 72 is, for example, a conductor, a conductive bump, a conductive contact, a metal contact, a solder ball, a solder ball, etc.
[0068] Figure 3 This is a cross-sectional schematic diagram of another embodiment of the electronic package 1 of this application, and the electronic package 1 may further include a thermally conductive layer 80 and / or a heat sink 81.
[0069] That is, such as Figure 3 As shown, the thermal conductive layer 80 can be formed on the upper surface 51 (such as the back / non-functional surface) of multiple electronic components 50 (such as chips) and the upper surface 61 of the encapsulating colloid 60, and the heat dissipation component 81 can be disposed on the upper surface of the substrate 70 to directly contact the thermal conductive layer 80, thereby rapidly dissipating the heat generated by the electronic package 1 or multiple electronic components 50 to the outside (such as the air) through the thermal conductive layer 80 and the heat dissipation component 81.
[0070] In one embodiment, the heat sink 81 has a heat sink 82 and at least one (or more) support feet 83 attached to the heat sink 82, and the heat sink 82 and the support feet 83 may be integrally formed. Meanwhile, the heat sink 82 may directly contact the thermally conductive layer 80, which may be located between multiple electronic components 50 (encapsulation colloid 60) and the heat sink 82 of the heat sink 81, and the support feet 83 may be attached or fixed to the upper surface of the substrate 70 via an adhesive layer (not shown).
[0071] However, in other embodiments, the electronic package 1 may not need to include a thermally conductive layer 80, so that the heat sink 82 of the heat sink 81 can directly contact or approach the upper surface 51 of the plurality of electronic components 50, and the support foot 83 of the heat sink 81 can directly contact or approach the side of the plurality of electronic components 50.
[0072] In one embodiment, the thermally conductive layer 80 is, for example, a thermal interface material (TIM), and is made of, for example, a thermally conductive material, a metal material, a solder material, etc., and has a high thermal conductivity (e.g., 86 W / mK). The heat sink 82 and the support foot 83 are made of, for example, a heat dissipation material or a metal material, and the support foot 83 is, for example, a support frame.
[0073] Therefore, this application provides an electronic package 1, including: a wiring structure 20; an interposer 40 disposed on the wiring structure 20, and the interposer 40 having a plurality of conductive through holes 41 for electrically connecting the wiring structure 20; a plurality of electronic components 50 disposed on the interposer 40 for electrically connecting the plurality of conductive through holes 41; and an encapsulating colloid 60 formed on the wiring structure 20 to cover the interposer 40 and the plurality of electronic components 50.
[0074] In one embodiment, the interposer 40 is provided with a wiring structure 30 to electrically connect the wiring structure 20. The wiring structure 20 has at least one insulating layer 22 and at least one first redistributed wiring layer 21 (or redistributed wiring layer) bonded to the insulating layer 22, and the wiring structure 30 has at least one dielectric layer 32 and at least one wiring layer 31 bonded to the dielectric layer 32, and the first redistributed wiring layer 21 of the wiring structure 20 is electrically connected to the wiring layer 31 of the wiring structure 30.
[0075] In one embodiment, the upper surface 51 of the plurality of electronic components 50 and the upper surface 61 of the encapsulating colloid 60 are coplanar.
[0076] In one embodiment, the electronic package 1 may include a plurality of conductive bumps 33, the wiring structure 20 has at least one first redistribution layer 21, the wiring structure 30 has at least one wiring layer 31, and the first redistribution layer 21 of the wiring structure 20 is electrically connected to the wiring layer 31 of the wiring structure 30 through the plurality of conductive bumps 33.
[0077] In one embodiment, the electronic package 1 may include a plurality of conductive contacts 52, wherein a plurality of electronic components 50 are connected to an intermediate plate 40 through the plurality of conductive contacts 52, and the plurality of electronic components 50 are electrically connected in sequence to the plurality of conductive contacts 52, a plurality of conductive through holes 41 of the intermediate plate 40, a circuit structure 30 and a wiring structure 20.
[0078] In one embodiment, the electronic package 1 may include a plurality of conductive bumps 33 and a plurality of conductive contacts 52, wherein the plurality of conductive bumps 33 are formed between the wiring structure 20 and the line structure 30, the plurality of conductive contacts 52 are formed between the plurality of conductive through holes 41 of the interposer 40 and the plurality of electronic components 50, and the encapsulating colloid 60 further covers the plurality of conductive bumps 33 and the plurality of conductive contacts 52.
[0079] In one embodiment, the electronic package 1 may include a plurality of conductors 23 and a substrate 70, wherein the plurality of conductors 23 are formed between the wiring structure 20 and the substrate 70 to electrically connect the wiring structure 20 and the substrate 70.
[0080] In one embodiment, the electronic package 1 may include a thermally conductive layer 80 formed on the upper surface 51 of a plurality of electronic components 50.
[0081] In one embodiment, the electronic package 1 may include a heat sink 81 formed on a thermally conductive layer 80, and the thermally conductive layer 80 is located between a plurality of electronic components 50 and the heat sink 81.
[0082] In one embodiment, the electronic package 1 may include a heat sink 81 having a heat sink 82 and at least one support foot 83 attached to the heat sink 82, wherein the heat sink 82 or the support foot 83 contacts or is close to a plurality of electronic components 50.
[0083] In summary, the electronic package 1 of this application has at least the following features, advantages or technical effects.
[0084] 1. This application can heterogeneously integrate various components such as wiring structure 20, circuit structure 30, interposer 40 (conductive via 41), multiple electronic components 50 and encapsulating colloid 60 to form a composite electronic package 1 (composite package structure), and can also effectively improve the overall performance of the electronic package 1.
[0085] 2. This application can make good use of Redistributed Line Layer (RDL) technology, Through Silicon Via (TSV) technology, Flip Chip technology, Molding technology, etc., to facilitate the effective connection or heterogeneous integration of various components such as wiring structure 20, circuit structure 30, interposer 40 (conductive via 41), multiple electronic components 50 and encapsulation colloid 60, and can also improve the overall performance or assembly yield of electronic package 1.
[0086] Third, this application can make good use of the thermal conductive layer 80 and / or heat dissipation components 81 (such as heat sink 82 and support foot 83) to facilitate the rapid dissipation of heat generated by the electronic package 1 or multiple electronic components 50 to the outside (such as the air), and can also efficiently improve the heat dissipation performance of the electronic package 1 or multiple electronic components 50.
[0087] Fourth, this application can make good use of heat sinks 82 and support feet 83 of heat sinks 81 made of, for example, metal materials to protect or strengthen electronic package 1, and can also make electronic package 1 have the characteristics of flexural resistance or high flexural strength.
[0088] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: A wiring structure; An intermediate plate is disposed on the wiring structure, and the intermediate plate has a plurality of conductive through holes for electrically connecting the wiring structure. Multiple electronic components are disposed on the intermediate plate and electrically connected to the multiple conductive vias; as well as An encapsulating colloid is formed on the wiring structure to encapsulate the interposer and the plurality of electronic components.
2. The electronic package as described in claim 1, characterized in that, The interposer has a circuit structure having at least one dielectric layer and at least one circuit layer bonded to the dielectric layer. The wiring structure has at least one insulating layer and at least one redistributed circuit layer bonded to the insulating layer, and the redistributed circuit layer of the wiring structure is electrically connected to the circuit layer of the circuit structure.
3. The electronic package as described in claim 2, characterized in that, The electronic package also includes multiple conductive bumps and multiple conductive contacts, wherein the multiple conductive bumps are formed between the wiring structure and the circuit structure, the multiple conductive contacts are formed between the multiple conductive through holes of the interposer and the multiple electronic components, and the encapsulating colloid further covers the multiple conductive bumps and the multiple conductive contacts.
4. The electronic package as described in claim 2, characterized in that, The electronic package also includes a plurality of conductive bumps, wherein the wiring structure has at least one overlay layer, the wiring structure has at least one line layer, and the overlay layer of the wiring structure is electrically connected to the line layer of the wiring structure through the plurality of conductive bumps.
5. The electronic package as described in claim 1, characterized in that, The electronic package also includes multiple conductive contacts, wherein the multiple electronic components are connected to the interposer through the multiple conductive contacts, and the multiple electronic components are electrically connected in sequence to the multiple conductive contacts, the multiple conductive vias of the interposer, and the wiring structure.
6. The electronic package as claimed in claim 1, characterized in that, The upper surfaces of the multiple electronic components are coplanar with the upper surface of the encapsulating colloid.
7. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes a plurality of conductors and a substrate, wherein the plurality of conductors are formed between the wiring structure and the substrate to electrically connect the wiring structure and the substrate.
8. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes a thermally conductive layer formed on the upper surface of the plurality of electronic components.
9. The electronic package as claimed in claim 8, characterized in that, The electronic package also includes a heat sink formed on the thermally conductive layer, and the thermally conductive layer is located between the plurality of electronic components and the heat sink.
10. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes a heat sink having a heat sink and at least one support foot attached to the heat sink, and the heat sink or the support foot is in contact with or close to the plurality of electronic components.