Bus residual electricity recycling circuit after spark

Abstract

The utility model discloses a bus residual electricity recycling circuit after spark, the residual electricity recycling circuit is applied to a power supply circuit of an electric precipitator, the power supply circuit comprises a rectification voltage regulation module, a filter inductor L, a bus filter capacitor C0 and a load module, the input end of the rectification voltage regulation module is used for connecting 380V alternating current voltage, and the output end of the rectification voltage regulation module is used for connecting the filter inductor L with the bus filter capacitor C0. A first output end of the rectification voltage regulation module is connected with a first end of the filter inductor L, a second end of the filter inductor L is respectively connected with a first end of the bus filter capacitor C0 and a first input end of the load module, and a second output end of the rectification voltage regulation module and a second end of the bus filter capacitor C0 are respectively connected with a second input end of the load module; the residual electricity recycling circuit comprises a controller, a residual electricity recycling storage circuit, a residual electricity recycling storage control circuit and a residual electricity cyclic utilization control circuit.

Description

Technical Field

[0001] This utility model relates to the field of environmental protection technology, specifically to a circuit for recovering and utilizing residual electricity from a spark-generated busbar. Background Technology

[0002] With the continuous and in-depth implementation of my country's environmental protection policies, electrostatic precipitators (ESPs), as a highly efficient waste gas treatment device, are widely used in heavy industrial fields such as thermal power plants and steel mills. ESPs use a high-voltage electric field to charge suspended particles in the airflow and adsorb them onto the collecting electrodes, thereby effectively removing dust, reducing the concentration of particulate matter in flue gas, improving air quality, and reducing environmental pollution. They have advantages such as high dust removal efficiency, low energy consumption, low equipment operating resistance, and strong large-scale flue gas treatment capacity, making them an important industrial flue gas treatment facility.

[0003] However, during the actual operation of an electrostatic precipitator, factors such as dust composition, temperature, and humidity in the airflow can cause spark discharges at the electrodes (cathode and anode) inside the equipment, leading to instability in the internal electric field. This discharge phenomenon can cause a momentary increase in bus voltage. If effective measures are not taken in time, it may cause serious damage to the equipment, reduce dust removal efficiency, or even cause equipment failure, affecting the continuity of production and environmental protection.

[0004] Currently, domestic electrostatic precipitator power supplies typically address the issue of bus voltage rise after spark discharge using two methods. The first method involves connecting a discharge resistor or controllable discharge circuit in parallel with the bus filter capacitor, using these resistors or circuits to dissipate the bus voltage during spark lockout. The second method involves activating the inverter circuit and connecting the load after spark lockout ends to reduce the bus voltage. Once the voltage returns to a safe level, the front-end rectifier and voltage regulation circuit is then activated. However, these existing technical solutions have limitations. They cannot effectively solve the problems of excessively rapid bus voltage rise during spark lockout, inability to dissipate voltage in real time, or system response delays, still affecting equipment stability and dust removal efficiency.

[0005] Therefore, in the operation of existing electrostatic precipitators, the rise in bus voltage after spark discharge, the untimely consumption of bus voltage, and the response delay have become problems that urgently need to be solved. Utility Model Content

[0006] Therefore, this utility model provides a circuit for recovering residual electricity from the bus after spark discharge to solve the problems of increased bus voltage, untimely consumption of bus voltage, and delayed response in existing electrostatic precipitators during operation.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A residual power recovery circuit for a spark-generated busbar is disclosed. This circuit is applied to the power supply circuit of an electrostatic precipitator. The power supply circuit includes a rectifier and voltage regulator module, a filter inductor L, a busbar filter capacitor C0, and a load module. The input terminal of the rectifier and voltage regulator module is connected to a 380V AC voltage. The first output terminal of the rectifier and voltage regulator module is connected to the first terminal of the filter inductor L. The second terminal of the filter inductor L is connected to both the first terminal of the busbar filter capacitor C0 and the first input terminal of the load module. The second output terminal of the rectifier and voltage regulator module and the second terminal of the busbar filter capacitor C0 are connected to the second input terminal of the load module.

[0009] The residual electricity recovery and utilization circuit includes a controller, a residual electricity recovery and storage circuit, a residual electricity recovery and storage control circuit, and a residual electricity recycling control circuit.

[0010] The first input terminal of the residual power recovery and storage circuit is connected to the second terminal of the filter inductor L; the second input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recovery and storage control circuit; the third input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recycling control circuit; the first output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recovery and storage control circuit; and the second output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recycling control circuit.

[0011] The second input terminal of the residual electricity recovery and storage control circuit is connected to the first output terminal of the controller.

[0012] The second input terminal of the residual power recycling control circuit is connected to the second output terminal of the controller, and the second output terminal of the residual power recycling control circuit is connected to the first input terminal of the controller; the third output terminal of the controller is connected to the input terminal of the rectifier voltage regulation module.

[0013] The controller receives spark signals, real-time bus voltage signals, and residual energy storage voltage signals, and coordinates the operation of the residual energy recovery and storage circuit, the residual energy recovery and storage control circuit, and the residual energy recycling control circuit by generating control signals. The residual energy recovery and storage circuit quickly recovers and stores the residual energy from the bus after a spark occurs. The residual energy recovery and storage control circuit monitors the bus voltage in real time and dynamically reduces the bus voltage to a target value by adjusting the switching frequency of the residual energy recovery and storage circuit. The residual energy recycling control circuit gradually releases the stored energy to the bus after the spark lockout ends, ensuring a smooth transition of the bus voltage and realizing the recycling of residual energy.

[0014] Optionally, the residual power recovery and storage circuit includes a first MOSFET Q1, a second MOSFET Q2, a first diode D1, a first capacitor Ch, and a first reactor L1;

[0015] The first terminal of the first MOSFET Q1 is connected to the first output terminal of the residual power recovery and storage circuit, the second terminal of the first MOSFET Q1 is connected to the second output terminal of the rectifier voltage regulation module, and the third terminal of the first MOSFET Q1 is connected to the first terminal of the first diode D1 and the first terminal of the first reactor L1, respectively.

[0016] The first terminal of the second MOSFET Q2 is connected to the first output terminal of the controller, the second terminal of the second MOSFET Q2 is connected to the second terminal of the first diode D1 and the first terminal of the first capacitor Ch, and the third terminal of the second MOSFET Q2 is connected to the second terminal of the filter inductor L.

[0017] The second terminal of the first reactor L1 is connected to the second terminal of the filter inductor L, and the second terminal of the first capacitor Ch is connected to the second output terminal of the rectifier voltage regulation module.

[0018] Optionally, the residual power recovery and storage control circuit includes a first voltage sampling and storage circuit, a first voltage sampling and tracking control circuit, and a second voltage sampling and tracking control circuit.

[0019] The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and storage circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and storage circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively.

[0020] The third input terminal of the first voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling tracking control circuit is connected to the first terminal of the first MOS transistor Q1.

[0021] The third input terminal of the second voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling tracking control circuit is connected to the third output terminal of the first voltage sampling tracking control circuit, the first output terminal of the second voltage sampling tracking control circuit is connected to the second input terminal of the first voltage sampling storage circuit, and the second output terminal of the second voltage sampling tracking control circuit is connected to the third input terminal of the first voltage sampling storage circuit.

[0022] The first target connection terminal is the connection terminal between the second terminal of the first reactor L1 and the second terminal of the filter inductor L.

[0023] Optionally, the first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2, and a second transistor VT2;

[0024] The first low-pass filter includes a third resistor R3 and a first capacitor C1. The first end of the third resistor R3 is connected to the first target connection terminal, and the second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input terminal of the first operational amplifier U1, respectively.

[0025] The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling tracking control circuit, and the first input terminal of the second voltage sampling tracking control circuit, respectively; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1;

[0026] The second terminal of the first transistor VT1 is connected to the first terminal of the fifth resistor R5, the first terminal of the second capacitor C2, and the non-inverting input terminal of the second operational amplifier U2, respectively; the third terminal of the first transistor VT1 is connected to the first output terminal of the second voltage sampling tracking control circuit.

[0027] The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling tracking control circuit and the second input terminal of the second voltage sampling tracking control circuit, respectively.

[0028] The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are grounded;

[0029] The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

[0030] Optionally, the first voltage sampling tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6, and a second AND gate U7;

[0031] The non-inverting input of the third operational amplifier U3 is connected to the first terminals of the sixth resistor R6 and the seventh resistor R7, respectively. The inverting input of the third operational amplifier U3 is connected to the first terminals of the eighth resistor R8 and the ninth resistor R9, respectively. The output of the third operational amplifier U3 is connected to the second terminals of the ninth resistor R9 and the eleventh resistor R11, respectively. The second terminal of the sixth resistor R6 is connected to the output of the second operational amplifier U2, and the second terminal of the seventh resistor R7 is grounded. The second terminal of the eighth resistor R8 is connected to the first terminal of the adjustable resistor RP2, and the second terminal of the adjustable resistor RP2 is connected to the 5V voltage output terminal. The third terminal of the adjustable resistor RP2 is connected to the first terminal of the twelfth resistor R12, and the second terminal of the twelfth resistor R12 is grounded.

[0032] The non-inverting input of the first comparator U4 is connected to the second terminal of the eleventh resistor R11 and the first terminal of the third capacitor C3, respectively. The inverting input of the first comparator U4 is connected to the first terminal of the tenth resistor R10, respectively. The output of the first comparator U4 is connected to the first terminal of the thirteenth resistor R13 and the first terminal of the first inverter U5, respectively. The second terminal of the third capacitor C3 is grounded. The second terminal of the tenth resistor R10 is electrically connected to the output of the first operational amplifier U1 and the first input of the residual current recycling control circuit, respectively. The second terminal of the thirteenth resistor R13 is connected to the 5V voltage output terminal.

[0033] The second terminal of the first inverter U5 is connected to the first input terminal of the first AND gate U6; the second input terminal of the first AND gate U6 is connected to the first output terminal of the controller, and the first output terminal of the controller is used to output a spark generation signal; the output terminal of the first AND gate U6 is connected to the first input terminal of the second AND gate U7.

[0034] The second input terminal of the second AND gate U7 is connected to the second output terminal of the controller, and the second output terminal of the controller is used to output a fixed-frequency PWM1 signal; the output terminal of the second AND gate U7 is connected to the first terminal of the first MOS transistor Q1.

[0035] Optionally, the second voltage sampling tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10, and a second inverter U11;

[0036] The non-inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fifteenth resistor R15, the inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fourteenth resistor R14, and the output of the fourth operational amplifier U8 is connected to the first input of the third AND gate U9 and the first terminal of the sixteenth resistor R16. The second terminal of the fifteenth resistor R15 is connected to the output of the second operational amplifier U2, the second terminal of the fourteenth resistor R14 is connected to the output of the first operational amplifier U1, and the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal.

[0037] The second input terminal of the third AND gate U9 is connected to the third terminal of the first transistor VT1 and the output terminal of the second inverter U11, respectively; the output terminal of the third AND gate U9 is connected to the first input terminal of the first OR gate U10; and the input terminal of the second inverter U11 is connected to the first output terminal of the controller.

[0038] The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6, and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2.

[0039] Optionally, the residual power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit.

[0040] The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0041] The second input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the first voltage sampling tracking control circuit, the third input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling tracking control circuit is connected to the first terminal of the second MOS transistor Q2.

[0042] The second input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the third voltage sampling tracking control circuit, the third input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling tracking control circuit is connected to the second input terminal of the second voltage sampling storage circuit.

[0043] The second target connection terminal is the connection terminal between the second terminal of the second MOS transistor Q2 and the second terminal of the first diode D1.

[0044] Optionally, the second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12;

[0045] The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5. The first end of the twentieth resistor R20 is connected to the second target connection terminal, and the second end of the twentieth resistor R20 is connected to the first end of the fifth capacitor C5 and the non-inverting input terminal of the fifth operational amplifier U12. The second end of the fifth capacitor C5 is grounded.

[0046] The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0047] The second end of the 21st resistor R21 is connected to the first end of the 22nd resistor R22, the first end of the sixth capacitor C6, and the first input terminal of the third voltage sampling and tracking control circuit, respectively; the other end of the 22nd resistor R22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, the third end of the third transistor VT3 is connected to the output terminal of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

[0048] Optionally, the third voltage sampling tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14, and a fourth AND gate U15;

[0049] The non-inverting input of the sixth operational amplifier U13 is connected to the second terminal of the twenty-first resistor R21, the inverting input of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is connected to the first terminal of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0050] The non-inverting input of the seventh operational amplifier U14 is connected to the second terminal of the twenty-fourth resistor R24 ​​and the first terminal of the seventh capacitor C7, respectively; the inverting input of the seventh operational amplifier U14 is connected to the first terminal of the twenty-third resistor R23; the output of the seventh operational amplifier U14 is connected to the first input of the fourth AND gate U15; the second terminal of the seventh capacitor C7 is grounded; the second terminal of the twenty-third resistor R23 is connected to the output of the first operational amplifier U1.

[0051] The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

[0052] Optionally, the fourth voltage sampling tracking control circuit includes a second comparator U17, a fifth AND gate U18, and a third inverter U19;

[0053] The non-inverting input of the second comparator U17 is connected to the first terminal of the fifteenth resistor R15; the inverting input of the second comparator U17 is connected to the first terminal of the fourteenth resistor R14; the output of the second comparator U17 is connected to the first terminal of the sixteenth resistor R16 and the first input of the fifth AND gate U18; the second terminal of the fifteenth resistor R15 is connected to the output of the sixth operational amplifier U13; the second terminal of the fourteenth resistor R14 is connected to the output of the fifth operational amplifier U12; and the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal.

[0054] The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3;

[0055] The input terminal of the third inverter U19 is connected to the first output terminal of the controller.

[0056] This utility model has at least the following beneficial effects:

[0057] This application provides a circuit for recovering and utilizing residual electricity on the bus after spark discharge. By efficiently recovering, storing, and recycling the residual electricity on the bus after spark discharge, it effectively solves the problems of bus voltage rise, untimely consumption of residual electricity, and system response delay in the prior art. First, the circuit quickly transfers excess energy from the bus filter capacitor C0 to the storage capacitor after sparking, preventing a rapid rise in bus voltage caused by continuous power supply from the filter inductor L and reverse charging of inductive loads. This prevents secondary breakdown, arcing, and other damage to the equipment caused by bus overvoltage, ensuring the stable operation of the electrostatic precipitator. Second, the residual electricity recovery and storage control circuit monitors and adjusts the bus voltage in real time, using PWM signals to precisely control the residual electricity recovery process and dynamically reduce the bus voltage to the target range, avoiding equipment malfunctions caused by unstable bus voltage. Furthermore, after spark blocking ends, the residual electricity recycling control circuit gradually releases the stored energy to the bus, avoiding sudden rises or fluctuations in bus voltage and realizing the recycling of residual electricity, reducing energy waste and improving energy utilization efficiency. This invention also utilizes a unified controller to coordinate and manage the real-time acquisition of spark signals, bus voltage signals, and residual electricity storage signals, dynamically adjusting the residual electricity recovery and release process to ensure rapid system response and voltage stability. In summary, this invention solves the problem of bus voltage rise after spark discharge while achieving efficient utilization of residual electricity and dynamic stable control of bus voltage, comprehensively improving the operating efficiency and reliability of electrostatic precipitators. It effectively overcomes the limitations of existing technologies and possesses significant technological advancements and practical application value. Attached Figure Description

[0058] To more clearly illustrate the prior art and the present invention, the accompanying drawings used in the description of the prior art and the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other drawings from the provided drawings without any creative effort.

[0059] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which this utility model can be implemented. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this utility model can produce, should still fall within the scope of the technical content disclosed in this utility model.

[0060] Figure 1 This is a circuit block diagram of a power supply circuit in the prior art;

[0061] Figure 2A circuit principle block diagram of a power supply circuit and a residual power recovery circuit provided for embodiments of this utility model;

[0062] Figure 3 A circuit diagram of a residual power recovery and storage circuit provided for an embodiment of this utility model;

[0063] Figure 4 A circuit diagram of a residual power recovery and storage control circuit provided for an embodiment of this utility model;

[0064] Figure 5 A circuit diagram of a residual power recycling control circuit provided for an embodiment of this utility model;

[0065] Figure 6 A functional block diagram of a residual power recycling control circuit provided for an embodiment of this utility model. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0067] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," "fourth," etc. (if present), in the specification, claims, and accompanying drawings of this utility model are intended to distinguish the objects they refer to. For schemes with a sequential flow, this terminology need not be interpreted as describing a specific order or sequence; for schemes with device structures, this terminology does not distinguish between matters of importance or positional relationships.

[0068] Furthermore, the terms “comprising,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may also include other steps or units that are not expressly listed but are inherent to these processes, methods, products, or devices, or steps or units added based on further optimizations of the inventive concept.

[0069] The following section introduces the implementation background of the technical solutions provided in the embodiments of this application.

[0070] With the deepening of my country's environmental protection policies, electrostatic precipitators, as key equipment for removing dust from production waste gas, have become essential facilities in thermal power plants, steel plants, and other industries, resulting in strong market demand.

[0071] An electrostatic precipitator is a purification device that removes suspended particles carried in airflow based on electrostatic force. Under the action of a high-voltage electric field, charged dust particles are adsorbed onto the collecting electrode, reducing the concentration of particulate matter in the exhaust gas, thereby improving air quality and reducing environmental pollution. Compared with other dust removal equipment, electrostatic precipitators have advantages such as high dust removal efficiency, low energy consumption, low equipment operating resistance, and large-scale flue gas treatment capacity.

[0072] During electrostatic precipitator (ESP) applications, the composition, temperature, humidity, and the internal cathode and anode of the dust collector are affected by numerous uncontrollable factors, leading to changes in withstand voltage and causing spark flashover, also known as discharge, within the ESP. When this occurs, a timely assessment is crucial, requiring the power module to be shut down and power supply to the ESP to cease. During this process, the bus voltage continues to rise due to the rectifier / regulator not immediately disconnecting power and the sudden disconnection of the inductive load. This rise in bus voltage exceeds the bus voltage at the moment of discharge. When the spark lockout period ends and the load is ready to be reconnected, this bus voltage cannot be used directly to prevent secondary breakdown, which could reduce dust removal efficiency and cause overvoltage damage to the inverter unit and load-side components.

[0073] Currently, existing domestic electrostatic precipitator power supply equipment addresses the issue of increased bus voltage after sparking:

[0074] A discharge resistor or a controllable discharge circuit is connected in parallel at the bus filter capacitor terminal to dissipate the bus voltage during spark blocking.

[0075] After the spark lockout time ends, the inverter circuit is first turned on to reduce the bus voltage by connecting the load. After the bus voltage is reduced, the front-end rectifier voltage regulation circuit is turned on.

[0076] Based on the commonly used methods for dealing with the rise in bus voltage after sparking, it can be seen that they all reduce the bus voltage consumption by connecting a discharge resistor or a controllable discharge circuit and by connecting a downstream load. This is done at the cost of sacrificing dust removal efficiency and wasting electrical energy to prevent secondary breakdown and ensure the stability of the load-side components. However, they fail to fundamentally solve the problem of the bus voltage continuing to rise due to various factors after sparking.

[0077] like Figure 1As shown, in the first power supply equipment processing method described above, the front-end rectifier and voltage regulator module cannot be immediately shut off after a spark occurs. It continues to charge the bus filter capacitor C0 after the spark, causing the bus voltage to rise. Even if it is immediately shut off, the magnetic energy stored in the filter inductor L after the spark continues to supply power to the bus filter capacitor, causing the bus voltage to continue to rise. If the rectifier and voltage regulator module is operating at its rated value when the spark occurs, the bus voltage will inevitably exceed the rated DC540V after the spark. This does not solve the problem of the impact of the increased bus voltage after the spark on the main circuit components. The only solution is to improve the selection criteria of the components to ensure stable circuit operation and to open the controllable discharge circuit during the spark lockout period to reduce the bus voltage. However, this inevitably leads to energy waste, and the parallel discharge resistor method further wastes energy.

[0078] The second power supply equipment handling method described above, which involves lowering the bus voltage by connecting to the load after the spark lockout time, can reduce the bus voltage to some extent. However, it cannot guarantee against secondary breakdown or even arcing. Once secondary breakdown or arcing occurs, it can continuously reduce dust removal efficiency, affect the stability of equipment components, and waste electrical energy. Furthermore, the extent to which the bus voltage is lowered by this method is uncontrollable. Random changes at the load end can easily cause the bus voltage to be suddenly "drained." If the front-end rectifier and voltage regulator are then activated, it can easily cause bus oscillation, affecting the secondary voltage output and thus the dust collector's dust removal efficiency, as well as the stability of the components.

[0079] None of the above methods can effectively address the increase in bus voltage after sparking. They can only ensure circuit stability by selecting higher capacitors, but even then, it is difficult to guarantee the lifespan of components. They all reduce bus voltage by wasting electrical energy. They all sacrifice dust removal efficiency to prevent secondary breakdown, which inevitably affects dust removal efficiency, energy waste, and circuit operation stability.

[0080] Therefore, in the operation of existing electrostatic precipitators, the rise in bus voltage after spark discharge, the untimely consumption of bus voltage, and the response delay have become problems that urgently need to be solved.

[0081] Next, through some specific embodiments and accompanying drawings, we will describe in detail how this application solves the problems of increased bus voltage after spark discharge, untimely consumption of bus voltage, and response delay during the operation of the above-mentioned existing electrostatic precipitators.

[0082] like Figure 2As shown in the figure, this application provides a circuit for recovering residual electricity from a spark-generated busbar, applied to the power supply circuit of an electrostatic precipitator. The power supply circuit includes a rectifier and voltage regulator module, a filter inductor L, a busbar filter capacitor C0, and a load module. The input terminal of the rectifier and voltage regulator module is used to connect to a 380V AC voltage. The first output terminal of the rectifier and voltage regulator module is connected to the first terminal of the filter inductor L. The second terminal of the filter inductor L is connected to the first terminal of the busbar filter capacitor C0 and the first input terminal of the load module, respectively. The second output terminal of the rectifier and voltage regulator module and the second terminal of the busbar filter capacitor C0 are respectively connected to the second input terminal of the load module.

[0083] The residual electricity recovery and utilization circuit includes a controller, a residual electricity recovery and storage circuit, a residual electricity recovery and storage control circuit, and a residual electricity recycling control circuit.

[0084] The first input terminal of the residual power recovery and storage circuit is connected to the second terminal of the filter inductor L; the second input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recovery and storage control circuit; the third input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recycling control circuit; the first output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recovery and storage control circuit; and the second output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recycling control circuit.

[0085] The second input terminal of the residual electricity recovery and storage control circuit is connected to the first output terminal of the controller.

[0086] The second input terminal of the residual power recycling control circuit is connected to the second output terminal of the controller, and the second output terminal of the residual power recycling control circuit is connected to the first input terminal of the controller; the third output terminal of the controller is connected to the input terminal of the rectifier voltage regulation module.

[0087] The controller receives spark signals, real-time bus voltage signals, and residual energy storage voltage signals, and coordinates the operation of the residual energy recovery and storage circuit, the residual energy recovery and storage control circuit, and the residual energy recycling control circuit by generating control signals. The residual energy recovery and storage circuit quickly recovers and stores the residual energy from the bus after a spark occurs. The residual energy recovery and storage control circuit monitors the bus voltage in real time and dynamically reduces the bus voltage to a target value by adjusting the switching frequency of the residual energy recovery and storage circuit. The residual energy recycling control circuit gradually releases the stored energy to the bus after the spark lockout ends, ensuring a smooth transition of the bus voltage and realizing the recycling of residual energy.

[0088] This application discloses a circuit for recovering residual electricity from the busbar after sparking. For example... Figure 2As shown: A residual power recovery and storage circuit is connected in parallel before the filter capacitor C1, and a residual power recovery and storage control circuit and a residual power recycling control circuit are matched.

[0089] The circuit described is currently used in the recovery and recycling of residual electricity on the bus after the spark in a high-voltage electrostatic precipitator. When a discharge occurs inside the electrostatic precipitator, since the rectifier voltage regulation module is mostly a three-phase fully controlled bridge rectifier composed of thyristors, and a filter inductor L is usually connected in series after the rectifier voltage regulation module for filtering, the thyristors cannot be turned off in time after the spark, and the magnetic energy stored in the filter inductor L will continue to supply power to the bus filter capacitor C0. When the discharge occurs, the IGBT is suddenly turned off, cutting off the downstream inductive load module (rectifier transformer). The load module will cause reverse charging of the bus filter capacitor C0 through the IGBT freewheeling diode. Thus, the bus filter capacitor C0, after the thyristor's delayed turn-off, the power supply of the filter inductor L, and the reverse charging of the inductive load, will cause the bus voltage value after the spark to be higher than the system's given bus voltage. Its characteristic is that after the spark signal appears, the bus voltage will rise to a certain value and remain unchanged. Based on this characteristic, the circuit is applied to a high-voltage electrostatic precipitator power supply, which can stabilize the bus voltage after sparking and collect residual electricity from the bus. This process can effectively prevent the bus voltage from being forced to rise after sparking, prevent damage to components such as the rectifier voltage regulation module, bus filter capacitor C0, and inverter module, and recover and store residual electricity. It can also reduce the bus voltage value to an ideal preset value according to system requirements, thereby ensuring circuit stability while achieving energy saving, reducing bus ripple, improving dust collection efficiency, and preventing secondary breakdown.

[0090] The rectifier and voltage regulator module is used to connect to 380V AC power, rectify it, and output a stable DC voltage. The output terminal of the rectifier and voltage regulator module is connected to the bus filter capacitor C0 through the filter inductor L, providing a smooth voltage to the power bus.

[0091] The bus filter capacitor C0 is used for filtering and stabilizing the bus voltage. It is connected to the load module to ensure the normal operation of the load.

[0092] The input terminal of the residual power recovery and storage circuit is connected to the output terminal of the filter inductor L, and is also connected to the residual power recovery and storage control circuit and the residual power recycling control circuit. Its core components include a storage capacitor, switching devices (such as MOSFETs), diodes, and reactors, which can quickly store the residual power of the bus and convert it into reusable electrical energy.

[0093] The residual electricity recovery and storage control circuit samples the bus voltage signal in real time and compares it with the target voltage value. By controlling the switching frequency and duty cycle in the residual electricity recovery and storage circuit, the bus voltage is dynamically adjusted.

[0094] After the spark lockout time ends, the residual power recycling control circuit gradually releases the electrical energy stored in the residual power recovery and storage circuit to the bus, realizing the recycling of residual power and ensuring a smooth transition of bus voltage.

[0095] When a spark occurs: After the spark signal is triggered, the controller shuts down the rectifier voltage regulation module and stops supplying power to the bus. At the same time, the controller controls the switching devices in the residual power recovery and storage circuit to quickly transfer the residual power in the bus filter capacitor C0 to the storage capacitor, thereby reducing the bus voltage to the target range.

[0096] During spark lockout: The residual power recovery and storage circuit continuously recovers residual power from the bus. The controller dynamically adjusts the recovery frequency based on the real-time sampled bus voltage signal to ensure that the bus voltage remains stable within a safe range.

[0097] After the spark lockout ends: the controller gradually releases the energy from the storage capacitor to the bus through the residual current recycling control circuit, while simultaneously restarting the rectifier and voltage regulation module to ensure a smooth recovery of the bus voltage. The release process involves gradually increasing the duty cycle of the PWM signal to prevent bus voltage fluctuations or sudden spikes.

[0098] This invention, through the coordinated operation of the residual power recovery and storage circuit and the residual power recovery and storage control circuit, can quickly transfer the residual power on the bus to the storage capacitor after a spark occurs. This prevents the bus voltage from rising rapidly due to the continuous power supply of the filter inductor and the reverse charging of the inductive load, thereby effectively preventing secondary breakdown or arcing of the equipment that may be caused by excessive bus voltage and protecting the normal operation of the electrostatic precipitator.

[0099] During the spark lockout period, the residual energy recovery and storage circuit can dynamically and continuously recover excess electrical energy from the bus and store it in a capacitor, avoiding energy waste. Simultaneously, after the spark lockout period ends, the residual energy recycling control circuit gradually releases the stored electrical energy back to the bus, realizing the recycling of residual energy and improving energy efficiency.

[0100] This invention uses a residual energy recovery and storage control circuit and a controller to sample the bus voltage in real time and compare it with a preset target voltage value. The operating state of the residual energy recovery and storage circuit is dynamically adjusted to ensure that the bus voltage remains within a safe range. After spark blocking ends, the residual energy recycling control circuit gradually releases the stored energy through a PWM signal, ensuring a smooth transition of the bus voltage and avoiding sudden rises or overshoots, thus improving the system's voltage stability.

[0101] Spark discharge is a common phenomenon in the operation of electrostatic precipitators. Improper handling can lead to equipment damage and reduced dust removal efficiency. This invention solves the problems of increased bus voltage and untimely consumption after spark discharge by using an efficient residual electricity recovery and utilization mechanism. This improves the operational reliability and stability of the electrostatic precipitator, while ensuring equipment safety and extending its service life.

[0102] Compared with existing technologies, this invention achieves rapid regulation of the bus voltage through the real-time control and feedback mechanism of the controller, avoiding bus voltage fluctuations or instability caused by system response delays. The residual power recovery and release processes are precisely controlled by PWM signals, ensuring the rapid response and stable operation of the entire system.

[0103] This invention reduces energy waste through efficient recovery and recycling of residual electricity, while avoiding equipment damage caused by spark discharge, thus lowering equipment maintenance and operating costs and improving the system's economic efficiency.

[0104] This application provides a circuit for recovering and utilizing residual electricity on the bus after spark discharge. By efficiently recovering, storing, and recycling the residual electricity on the bus after spark discharge, it effectively solves the problems of bus voltage rise, untimely consumption of residual electricity, and system response delay in the prior art. First, the circuit quickly transfers excess energy from the bus filter capacitor C0 to the storage capacitor after sparking, preventing a rapid rise in bus voltage caused by continuous power supply from the filter inductor L and reverse charging of inductive loads. This prevents secondary breakdown, arcing, and other damage to the equipment caused by bus overvoltage, ensuring the stable operation of the electrostatic precipitator. Second, the residual electricity recovery and storage control circuit monitors and adjusts the bus voltage in real time, using PWM signals to precisely control the residual electricity recovery process and dynamically reduce the bus voltage to the target range, avoiding equipment malfunctions caused by unstable bus voltage. Furthermore, after spark blocking ends, the residual electricity recycling control circuit gradually releases the stored energy to the bus, avoiding sudden rises or fluctuations in bus voltage and realizing the recycling of residual electricity, reducing energy waste and improving energy utilization efficiency. This invention also utilizes a unified controller to coordinate and manage the real-time acquisition of spark signals, bus voltage signals, and residual electricity storage signals, dynamically adjusting the residual electricity recovery and release process to ensure rapid system response and voltage stability. In summary, this invention solves the problem of bus voltage rise after spark discharge while achieving efficient utilization of residual electricity and dynamic stable control of bus voltage, comprehensively improving the operating efficiency and reliability of electrostatic precipitators. It effectively overcomes the limitations of existing technologies and possesses significant technological advancements and practical application value.

[0105] like Figure 3As shown, in one possible embodiment, the residual power recovery and storage circuit includes a first MOSFET Q1, a second MOSFET Q2, a first diode D1, a first capacitor Ch, and a first reactor L1.

[0106] The first terminal of the first MOSFET Q1 is connected to the first output terminal of the residual power recovery and storage circuit, the second terminal of the first MOSFET Q1 is connected to the second output terminal of the rectifier voltage regulation module, and the third terminal of the first MOSFET Q1 is connected to the first terminal of the first diode D1 and the first terminal of the first reactor L1, respectively.

[0107] The first terminal of the second MOSFET Q2 is connected to the first output terminal of the controller, the second terminal of the second MOSFET Q2 is connected to the second terminal of the first diode D1 and the first terminal of the first capacitor Ch, and the third terminal of the second MOSFET Q2 is connected to the second terminal of the filter inductor L.

[0108] The second terminal of the first reactor L1 is connected to the second terminal of the filter inductor L, and the second terminal of the first capacitor Ch is connected to the second output terminal of the rectifier voltage regulation module.

[0109] It should be noted that by collecting the real-time voltage values ​​at points A (first target connection terminal) and B (second target connection terminal), the residual power recovery and storage control circuit promptly collects the increased bus voltage caused by the delayed shutdown of the rectifier voltage regulation section and the continued power supply of the filter inductor L after the spark occurs, as well as the increased bus voltage caused by the freewheeling reverse charging due to the sudden disconnection of the inductive load. This ensures the stability of the bus voltage. Furthermore, through this control circuit, the bus voltage can be reduced to the ideal preset voltage value, preventing secondary breakdown and "arc" phenomena when the downstream load is reconnected without wasting electrical energy. When the spark lockout time ends, the inverter module is turned on, and the residual power recycling control circuit supplies the energy of capacitor Ch in the residual power recovery and storage circuit to the bus until the energy in the residual power recovery circuit can no longer support the bus voltage. The rectifier voltage regulation section is then turned on in time to ensure the stability of the bus voltage, thereby realizing the recovery and recycling of residual power on the bus after the spark is controlled.

[0110] The residual power recovery and storage circuit is an H-type circuit composed of two NMOS transistors Q1 and Q2, a diode D1, a capacitor Ch, and an inductor L1. When there is no spark, Q1 is off, and Q2 remains on. The storage capacitor Ch is connected in parallel with the bus filter capacitor C1, serving as the bus filter after rectification. When a spark occurs, Q2 is turned off, and Q1 is turned on. The electrical energy in the filter capacitor C1 is converted into magnetic energy in L1. Then, Q1 is turned off, and the magnetic energy in L1 is converted back into electrical energy by the diode D1 and stored in the storage capacitor Ch. This process of turning Q1 on and off at a fixed frequency (according to...) The resonant frequency formula (the specific switching frequency is determined by the values ​​of L1 and C1) reduces the voltage on the bus filter capacitor C1, i.e., the bus voltage, to the ideal preset value, and then turns off the Q1 transistor, realizing the transfer of residual electricity on the bus after the spark occurs to the storage capacitor Ch; after the spark lockout time ends, the rectifier voltage regulation module is not turned on temporarily, but the switching of the Q2 transistor is controlled at a fixed frequency with a gradually increasing duty cycle, so that the electricity in the storage capacitor Ch is gradually charged to the bus, realizing the recycling of residual electricity after the spark occurs; when the voltage of Ch can no longer support the bus voltage, the rectifier voltage regulation section is turned on in time to ensure the stability of the bus voltage.

[0111] like Figure 4 As shown, in one possible embodiment, the residual power recovery and storage control circuit includes a first voltage sampling storage circuit, a first voltage sampling tracking control circuit, and a second voltage sampling tracking control circuit.

[0112] The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and storage circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and storage circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively.

[0113] The third input terminal of the first voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling tracking control circuit is connected to the first terminal of the first MOS transistor Q1.

[0114] The third input terminal of the second voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling tracking control circuit is connected to the third output terminal of the first voltage sampling tracking control circuit, the first output terminal of the second voltage sampling tracking control circuit is connected to the second input terminal of the first voltage sampling storage circuit, and the second output terminal of the second voltage sampling tracking control circuit is connected to the third input terminal of the first voltage sampling storage circuit.

[0115] The first target connection terminal is the connection terminal between the second terminal of the first reactor L1 and the second terminal of the filter inductor L.

[0116] like Figure 4 As shown, in one possible embodiment, the first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2, and a second transistor VT2;

[0117] The first low-pass filter includes a third resistor R3 and a first capacitor C1. The first end of the third resistor R3 is connected to the first target connection terminal, and the second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input terminal of the first operational amplifier U1, respectively.

[0118] The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling tracking control circuit, and the first input terminal of the second voltage sampling tracking control circuit, respectively; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1;

[0119] The second terminal of the first transistor VT1 is connected to the first terminal of the fifth resistor R5, the first terminal of the second capacitor C2, and the non-inverting input terminal of the second operational amplifier U2, respectively; the third terminal of the first transistor VT1 is connected to the first output terminal of the second voltage sampling tracking control circuit.

[0120] The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling tracking control circuit and the second input terminal of the second voltage sampling tracking control circuit, respectively.

[0121] The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are grounded;

[0122] The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

[0123] like Figure 4 As shown, in one possible embodiment, the first voltage sampling tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6, and a second AND gate U7;

[0124] The non-inverting input of the third operational amplifier U3 is connected to the first terminals of the sixth resistor R6 and the seventh resistor R7, respectively. The inverting input of the third operational amplifier U3 is connected to the first terminals of the eighth resistor R8 and the ninth resistor R9, respectively. The output of the third operational amplifier U3 is connected to the second terminals of the ninth resistor R9 and the eleventh resistor R11, respectively. The second terminal of the sixth resistor R6 is connected to the output of the second operational amplifier U2, and the second terminal of the seventh resistor R7 is grounded. The second terminal of the eighth resistor R8 is connected to the first terminal of the adjustable resistor RP2, and the second terminal of the adjustable resistor RP2 is connected to the 5V voltage output terminal. The third terminal of the adjustable resistor RP2 is connected to the first terminal of the twelfth resistor R12, and the second terminal of the twelfth resistor R12 is grounded.

[0125] The non-inverting input of the first comparator U4 is connected to the second terminal of the eleventh resistor R11 and the first terminal of the third capacitor C3, respectively. The inverting input of the first comparator U4 is connected to the first terminal of the tenth resistor R10, respectively. The output of the first comparator U4 is connected to the first terminal of the thirteenth resistor R13 and the first terminal of the first inverter U5, respectively. The second terminal of the third capacitor C3 is grounded. The second terminal of the tenth resistor R10 is electrically connected to the output of the first operational amplifier U1 and the first input of the residual current recycling control circuit, respectively. The second terminal of the thirteenth resistor R13 is connected to the 5V voltage output terminal.

[0126] The second terminal of the first inverter U5 is connected to the first input terminal of the first AND gate U6; the second input terminal of the first AND gate U6 is connected to the first output terminal of the controller, and the first output terminal of the controller is used to output a spark generation signal; the output terminal of the first AND gate U6 is connected to the first input terminal of the second AND gate U7.

[0127] The second input terminal of the second AND gate U7 is connected to the second output terminal of the controller, and the second output terminal of the controller is used to output a fixed-frequency PWM1 signal; the output terminal of the second AND gate U7 is connected to the first terminal of the first MOS transistor Q1.

[0128] like Figure 4 As shown, in one possible embodiment, the second voltage sampling tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10, and a second inverter U11;

[0129] The non-inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fifteenth resistor R15, the inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fourteenth resistor R14, and the output of the fourth operational amplifier U8 is connected to the first input of the third AND gate U9 and the first terminal of the sixteenth resistor R16. The second terminal of the fifteenth resistor R15 is connected to the output of the second operational amplifier U2, the second terminal of the fourteenth resistor R14 is connected to the output of the first operational amplifier U1, and the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal.

[0130] The second input terminal of the third AND gate U9 is connected to the third terminal of the first transistor VT1 and the output terminal of the second inverter U11, respectively; the output terminal of the third AND gate U9 is connected to the first input terminal of the first OR gate U10; and the input terminal of the second inverter U11 is connected to the first output terminal of the controller.

[0131] The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6, and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2.

[0132] like Figure 4It can be seen that the bus voltage at point A, after being extracted by the DC voltage sampling board, passes through a low-pass filter composed of resistor R3 and capacitor C1 in the residual power recovery and storage control circuit; it then enters operational amplifiers U1-3, U1-2, and U1-6, which are connected to form follower 1 to enhance the driving capability of the DC voltage sampling signal. The output of follower 1, U1-6, is the real-time bus voltage sampling value at point A (due to the hysteresis of the low-pass filter, the so-called real-time bus voltage value here has a certain delay compared to the actual bus voltage value); the output of follower 1, U1-6, is connected to the collector (C) of transistor VT1 through resistor R4, and the emitter (E) of transistor VT1 is connected to the bus voltage sampling storage. The upper end of capacitor C2 is connected to the base of transistor VT1, which is controlled by a spark signal. When there is no spark, the spark signal is low and is connected to the base (B) of transistor VT1 via inverter U11, keeping transistor VT1 on. The voltage across the bus sampling storage capacitor C2 is the bus voltage. Due to the presence of the front-end low-pass filter (low-pass filter signal lag), this voltage is the bus voltage at the previous moment. When a spark occurs, the base (B) of transistor VT1 is controlled to turn off VT1, and the bus voltage at the moment before the spark is stored in capacitor C2. The upper end of resistor R5 is connected to the storage capacitor C2 and connected to U2-3, and the lower end of resistor R5 is connected to the collector (C) of transistor VT2. Electrode connections are formed in parallel with capacitor C2 to create a controllable discharge circuit; operational amplifier U2-3 is connected to the emitter of transistor VT1, the upper end of resistor R5, and the upper end of storage capacitor C2; operational amplifiers U2-2 and U2-6 are connected to form follower 2 to enhance drive capability and anti-interference capability; the output of follower 2 through U2-6 is connected to U3-3 through resistors R6 and the upper end of resistor R7, the lower end of resistor R7 is grounded, one end of resistors R8 and R9 is connected to U3-2, and the other end of resistor R9 is connected to U3-6; resistors R6, R7, R8, and R9, together with amplifier U3, form a subtractor; adjustable resistor RP2 is connected to resistor R12 and connected to the other end of resistor R8. The terminals form a step-down differential circuit, and the step-down differential value is autonomously adjusted by the adjustable resistor RP2. The bus voltage stored in C2 and the step-down differential circuit pass through the subtractor circuit to obtain the ideal preset target bus voltage value. The output terminal of U3-6 is connected to comparator U4-5 through resistor R11, and U4-4 is connected to U1-6. Resistors R10 and R11 and operational amplifier U4 form a comparator. The preset target bus voltage value output by the subtractor is compared with the real-time bus voltage value at point A through comparator U4. When the target bus voltage value is less than the real-time bus voltage value, the comparator outputs a low level. When the target voltage value is greater than or equal to the real-time bus voltage value, the comparator outputs a high level.The comparison result is output via U4-2 to the inverter U5 and connected to the input of the AND gate U6. The spark signal output by the CPU is connected to the other input of the AND gate U6. When the spark occurs, if the bus voltage has not yet dropped to the preset target bus voltage value, the output of the AND gate U6 is connected to the input of the AND gate U7 at a high level. The other input of the AND gate U7 is connected to the PWM1 output by the CPU. In this way, the output of the AND gate U7 controls the switching on and off of the Q1 transistor in the residual power recovery and storage circuit using the PWM1 (the frequency of PWM1 is calculated by the reactor L1 and the filter capacitor C1 in the residual power recovery and storage circuit), thereby realizing the residual power recovery and storage function of the bus. Otherwise, the output of the AND gate U6 is connected to the input of the AND gate U7 at a low level; the output of the AND gate U7 stops outputting PWM1 and disconnects the Q1 transistor in the residual power recovery and storage circuit. Additionally, the output of U1-6 of follower 1 is connected to operational amplifier U8-4 via resistor R14, and the output of U2-6 of follower 2 is connected to operational amplifier U8-5 via resistor R15. Resistors R14 and R15, along with operational amplifier U8, form a comparator. When the voltage of storage capacitor C2 of follower 2 is higher than the real-time bus voltage at point A of the front-end follower 1, comparator U8-2 outputs a high level. This high level, along with the output of NOT gate U11 (through which the no-spark signal passes), is connected to the two inputs of AND gate U9. This determines whether the real-time bus voltage is lower than the voltage of storage capacitor C2 in the no-spark state. The output of AND gate U9 is high, and this high level, along with the output of comparator U4-2 (where the bus power supply reaches a preset value after a spark), is connected to the two inputs of OR gate U10. These inputs control the base (B) of transistor VT2 in both spark-free and spark-free states, thereby controlling the voltage in storage capacitor C2 and achieving bus voltage tracking control in both spark-free and spark-free states.

[0133] like Figure 5 As shown, in one possible embodiment, the residual power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit.

[0134] The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0135] The second input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the first voltage sampling tracking control circuit, the third input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling tracking control circuit is connected to the first terminal of the second MOS transistor Q2.

[0136] The second input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the third voltage sampling tracking control circuit, the third input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling tracking control circuit is connected to the second input terminal of the second voltage sampling storage circuit.

[0137] The second target connection terminal is the connection terminal between the second terminal of the second MOS transistor Q2 and the second terminal of the first diode D1.

[0138] like Figure 5 As shown, in one possible embodiment, the second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12;

[0139] The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5. The first end of the twentieth resistor R20 is connected to the second target connection terminal, and the second end of the twentieth resistor R20 is connected to the first end of the fifth capacitor C5 and the non-inverting input terminal of the fifth operational amplifier U12. The second end of the fifth capacitor C5 is grounded.

[0140] The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0141] The second end of the 21st resistor R21 is connected to the first end of the 22nd resistor R22, the first end of the sixth capacitor C6, and the first input terminal of the third voltage sampling and tracking control circuit, respectively; the other end of the 22nd resistor R22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, the third end of the third transistor VT3 is connected to the output terminal of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

[0142] like Figure 5 As shown, in one possible embodiment, the third voltage sampling tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14, and a fourth AND gate U15;

[0143] The non-inverting input of the sixth operational amplifier U13 is connected to the second terminal of the twenty-first resistor R21, the inverting input of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is connected to the first terminal of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit, respectively.

[0144] The non-inverting input of the seventh operational amplifier U14 is connected to the second terminal of the twenty-fourth resistor R24 ​​and the first terminal of the seventh capacitor C7, respectively; the inverting input of the seventh operational amplifier U14 is connected to the first terminal of the twenty-third resistor R23; the output of the seventh operational amplifier U14 is connected to the first input of the fourth AND gate U15; the second terminal of the seventh capacitor C7 is grounded; the second terminal of the twenty-third resistor R23 is connected to the output of the first operational amplifier U1.

[0145] The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

[0146] like Figure 5 As shown, in one possible embodiment, the fourth voltage sampling tracking control circuit includes a second comparator U17, a fifth AND gate U18, and a third inverter U19;

[0147] The non-inverting input of the second comparator U17 is connected to the first terminal of the fifteenth resistor R15; the inverting input of the second comparator U17 is connected to the first terminal of the fourteenth resistor R14; the output of the second comparator U17 is connected to the first terminal of the sixteenth resistor R16 and the first input of the fifth AND gate U18; the second terminal of the fifteenth resistor R15 is connected to the output of the sixth operational amplifier U13; the second terminal of the fourteenth resistor R14 is connected to the output of the fifth operational amplifier U12; and the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal.

[0148] The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3;

[0149] The input terminal of the third inverter U19 is connected to the first output terminal of the controller.

[0150] like Figure 5It can be seen that the voltage at point B, after being extracted by the DC voltage sampling board, passes through the low-pass filter composed of R20 and C5; it then enters operational amplifier U12-3. Operational amplifiers U12-2 and U12-6 are connected to form follower 3, which enhances the signal driving capability of the output of U12-6. The output of follower 3, U11-6, is the real-time voltage value at point B (due to the hysteresis of the low-pass filter, the so-called real-time voltage value here has a certain delay compared with the actual bus voltage value); the output of follower 3, U12-6, is connected to the upper end of storage capacitor C6 through resistor R21, and the lower end of resistor R22 is connected to the collector of transistor VT3 in parallel with storage capacitor C6. A controllable discharge circuit is formed. The upper end of resistor R22 is connected to storage capacitor C6, which is then connected to operational amplifier U13-3. Operational amplifiers U13-2 and U13-6 are connected to form follower 4, which is used to improve the signal driving capability and anti-interference capability at this point. The output of follower 4, U13-6, is the bus voltage stored in storage capacitor C6. Here, the voltage value stored in capacitor C6 and the real-time voltage value at point B output by U12-6 are respectively connected to a comparator composed of resistors R15 and R14 and operational amplifier U17 for comparison. When the bus voltage value stored in capacitor C6 is greater than the real-time voltage value at point B, comparator U17-2 outputs a high level to the input of AND gate U18. When a spark occurs, the spark signal outputs a high level through NOT gate U19 to the other input of AND gate U18. The output of AND gate U18 is connected to the base (B) of transistor VT3, controlling the turn-on of transistor VT3 and discharging the voltage of the bus voltage storage capacitor C6. When the bus voltage value stored in C6 is less than or equal to the real-time voltage value at point B, comparator U17-2 outputs a low level to the input of AND gate U18, which in turn outputs a low level to the base (B) of transistor VT3, controlling the turn-off of transistor VT3. This achieves the purpose of real-time tracking of the voltage at point B when there is no spark. Simultaneously, the voltage value stored in capacitor C6 at the output of follower 4 (U13-6) is passed through a resistor... R24 enters operational amplifier U14-5. The real-time voltage value of the bus at point A in the "residual power recovery control circuit" enters operational amplifier U13-4 through resistor R23. Resistors R23, R24, and operational amplifier U13 form a comparator connected to the input of AND gate U15. If the voltage value stored in capacitor C6, i.e., the real-time voltage value at point B, is greater than the real-time voltage value of the bus at point A in the "residual power recovery control circuit", comparator U14-2 outputs a high level. If the voltage value stored in capacitor C6, i.e., the real-time voltage value at point B, is less than or equal to the real-time voltage value of the bus at point A in the "residual power recovery control circuit", U14-2 outputs a low level. This signal is used to determine the status of residual power recycling.The spark lockout signal is connected to the other input of AND gate U15. When the spark lockout time expires and the load needs to be reconnected, the voltage stored in capacitor C6 will definitely be greater than the real-time bus voltage at point A in the "residual power recovery control circuit". The high-level output of AND gate U15 is then connected to the CPU. The CPU controls PWM2, which automatically increases its duty cycle at a certain frequency, to control the on / off state of transistor Q2 in the "residual power recovery storage circuit". This allows the energy stored in Ch in the "residual power recovery storage circuit" to be re-supplied to the bus for recycling. When the voltage stored in capacitor C6, i.e., the real-time voltage at point B, is less than or equal to the real-time bus voltage at point A in the "residual power recovery control circuit" (i.e., the voltage at point B is the same as the voltage at point A), the rectifier voltage regulation module is activated. This achieves the recycling of residual power after sparking and prevents bus voltage fluctuations, reducing bus voltage ripple.

[0151] This application provides a circuit for recovering residual electricity from a spark-generated busbar, which can be widely used in high-power power supplies in industrial production settings and can be combined with a CPU for use in different power control systems. The functional block diagram is shown below. Figure 6 As shown.

[0152] This invention, based on a residual power recovery and storage circuit, a residual power recovery control circuit, and a residual power recycling control circuit, realizes the recovery and recycling of residual power on the bus after sparking. Because of the presence of the residual power recovery and storage circuit and the residual power recovery control circuit, when a spark occurs, the electrical energy originally charged to the bus is transferred to capacitor Ch at point B via reactor L1, preventing a rise in bus voltage and effectively ensuring the stable operation and lifespan of components in the circuit. Because the residual power recovery control circuit can accurately track the bus voltage and preset an ideal bus voltage reduction range as needed, secondary breakdown does not occur when power is restored after sparking, improving dust collection efficiency. Because the residual power recycling control circuit effectively utilizes the residual power on the bus after sparking, the residual power in the storage circuit is recycled back to the bus when the spark ends, achieving energy saving.

[0153] Specifically, this application provides a residual power recovery and utilization circuit for the bus after sparking. It utilizes a residual power recovery and storage circuit to store the residual power in the bus after sparking, thus solving the problem of voltage rise in the bus after sparking. Furthermore, it utilizes a residual power recovery control circuit to accurately and effectively control the voltage of the bus after sparking; it utilizes a residual power recovery control circuit to accurately track the bus voltage; it utilizes a residual power recycling control circuit to achieve the recycling of residual power; and it utilizes a residual power recycling control circuit to accurately track the voltage of the storage capacitor Ch.

[0154] The above specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0155] The technical features of the above embodiments can be combined in any way (as long as there is no contradiction in the combination of these technical features). For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered to be within the scope of this specification.

[0156] The present invention has been described in a relatively specific and detailed manner above through general description and specific embodiments. It should be noted that, without departing from the concept of the present invention, various modifications and improvements can be made to these specific embodiments, all of which fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A circuit for recovering residual electricity from a spark-generated busbar, characterized in that, The residual electricity recovery circuit is applied to the power supply circuit of the electrostatic precipitator. The power supply circuit includes a rectifier voltage regulation module, a filter inductor L, a bus filter capacitor C0, and a load module. The input terminal of the rectifier voltage regulation module is used to connect to a 380V AC voltage. The first output terminal of the rectifier voltage regulation module is connected to the first terminal of the filter inductor L. The second terminal of the filter inductor L is connected to the first terminal of the bus filter capacitor C0 and the first input terminal of the load module. The second output terminal of the rectifier voltage regulation module and the second terminal of the bus filter capacitor C0 are connected to the second input terminal of the load module. The residual electricity recovery and utilization circuit includes a controller, a residual electricity recovery and storage circuit, a residual electricity recovery and storage control circuit, and a residual electricity recycling control circuit. The first input terminal of the residual power recovery and storage circuit is connected to the second terminal of the filter inductor L; the second input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recovery and storage control circuit; the third input terminal of the residual power recovery and storage circuit is connected to the first output terminal of the residual power recycling control circuit; the first output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recovery and storage control circuit; and the second output terminal of the residual power recovery and storage circuit is connected to the first input terminal of the residual power recycling control circuit. The second input terminal of the residual electricity recovery and storage control circuit is connected to the first output terminal of the controller. The second input terminal of the residual power recycling control circuit is connected to the second output terminal of the controller, and the second output terminal of the residual power recycling control circuit is connected to the first input terminal of the controller; the third output terminal of the controller is connected to the input terminal of the rectifier voltage regulation module.

2. The circuit for recovering residual electricity from a spark-generated busbar according to claim 1, characterized in that, The residual power recovery and storage circuit includes a first MOSFET Q1, a second MOSFET Q2, a first diode D1, a first capacitor Ch, and a first reactor L1; The first terminal of the first MOSFET Q1 is connected to the first output terminal of the residual power recovery and storage circuit, the second terminal of the first MOSFET Q1 is connected to the second output terminal of the rectifier voltage regulation module, and the third terminal of the first MOSFET Q1 is connected to the first terminal of the first diode D1 and the first terminal of the first reactor L1, respectively. The first terminal of the second MOSFET Q2 is connected to the first output terminal of the controller, the second terminal of the second MOSFET Q2 is connected to the second terminal of the first diode D1 and the first terminal of the first capacitor Ch, and the third terminal of the second MOSFET Q2 is connected to the second terminal of the filter inductor L. The second terminal of the first reactor L1 is connected to the second terminal of the filter inductor L, and the second terminal of the first capacitor Ch is connected to the second output terminal of the rectifier voltage regulation module.

3. The circuit for recovering residual electricity from a spark-generated busbar according to claim 2, characterized in that, The residual power recovery and storage control circuit includes a first voltage sampling and storage circuit, a first voltage sampling and tracking control circuit, and a second voltage sampling and tracking control circuit. The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and storage circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and storage circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively. The third input terminal of the first voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling tracking control circuit is connected to the first terminal of the first MOS transistor Q1. The third input terminal of the second voltage sampling tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling tracking control circuit is connected to the third output terminal of the first voltage sampling tracking control circuit, the first output terminal of the second voltage sampling tracking control circuit is connected to the second input terminal of the first voltage sampling storage circuit, and the second output terminal of the second voltage sampling tracking control circuit is connected to the third input terminal of the first voltage sampling storage circuit. The first target connection terminal is the connection terminal between the second terminal of the first reactor L1 and the second terminal of the filter inductor L.

4. The circuit for recovering residual electricity from a spark-generated busbar according to claim 3, characterized in that, The first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2, and a second transistor VT2; The first low-pass filter includes a third resistor R3 and a first capacitor C1. The first end of the third resistor R3 is connected to the first target connection terminal, and the second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input terminal of the first operational amplifier U1, respectively. The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling tracking control circuit, and the first input terminal of the second voltage sampling tracking control circuit, respectively; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1; The second terminal of the first transistor VT1 is connected to the first terminal of the fifth resistor R5, the first terminal of the second capacitor C2, and the non-inverting input terminal of the second operational amplifier U2, respectively; the third terminal of the first transistor VT1 is connected to the first output terminal of the second voltage sampling tracking control circuit. The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling tracking control circuit and the second input terminal of the second voltage sampling tracking control circuit, respectively. The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are grounded; The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

5. A circuit for recovering residual electricity from a spark-generated busbar according to claim 4, characterized in that, The first voltage sampling tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6, and a second AND gate U7; The non-inverting input of the third operational amplifier U3 is connected to the first terminals of the sixth resistor R6 and the seventh resistor R7, respectively. The inverting input of the third operational amplifier U3 is connected to the first terminals of the eighth resistor R8 and the ninth resistor R9, respectively. The output of the third operational amplifier U3 is connected to the second terminals of the ninth resistor R9 and the eleventh resistor R11, respectively. The second terminal of the sixth resistor R6 is connected to the output of the second operational amplifier U2, and the second terminal of the seventh resistor R7 is grounded. The second terminal of the eighth resistor R8 is connected to the first terminal of the adjustable resistor RP2, and the second terminal of the adjustable resistor RP2 is connected to the 5V voltage output terminal. The third terminal of the adjustable resistor RP2 is connected to the first terminal of the twelfth resistor R12, and the second terminal of the twelfth resistor R12 is grounded. The non-inverting input of the first comparator U4 is connected to the second terminal of the eleventh resistor R11 and the first terminal of the third capacitor C3, respectively. The inverting input of the first comparator U4 is connected to the first terminal of the tenth resistor R10, respectively. The output of the first comparator U4 is connected to the first terminal of the thirteenth resistor R13 and the first terminal of the first inverter U5, respectively. The second terminal of the third capacitor C3 is grounded. The second terminal of the tenth resistor R10 is electrically connected to the output of the first operational amplifier U1 and the first input of the residual current recycling control circuit, respectively. The second terminal of the thirteenth resistor R13 is connected to the 5V voltage output terminal. The second terminal of the first inverter U5 is connected to the first input terminal of the first AND gate U6; the second input terminal of the first AND gate U6 is connected to the first output terminal of the controller, and the first output terminal of the controller is used to output a spark generation signal; the output terminal of the first AND gate U6 is connected to the first input terminal of the second AND gate U7. The second input terminal of the second AND gate U7 is connected to the second output terminal of the controller, and the second output terminal of the controller is used to output a fixed-frequency PWM1 signal; the output terminal of the second AND gate U7 is connected to the first terminal of the first MOS transistor Q1.

6. The circuit for recovering residual electricity from a spark-generated busbar according to claim 5, characterized in that, The second voltage sampling tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10, and a second inverter U11; The non-inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fifteenth resistor R15, the inverting input of the fourth operational amplifier U8 is connected to the first terminal of the fourteenth resistor R14, and the output of the fourth operational amplifier U8 is connected to the first input of the third AND gate U9 and the first terminal of the sixteenth resistor R16. The second terminal of the fifteenth resistor R15 is connected to the output of the second operational amplifier U2, the second terminal of the fourteenth resistor R14 is connected to the output of the first operational amplifier U1, and the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal. The second input terminal of the third AND gate U9 is connected to the third terminal of the first transistor VT1 and the output terminal of the second inverter U11, respectively; the output terminal of the third AND gate U9 is connected to the first input terminal of the first OR gate U10; and the input terminal of the second inverter U11 is connected to the first output terminal of the controller. The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6, and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2.

7. The circuit for recovering residual electricity from a spark-generated busbar according to claim 3, characterized in that, The residual power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit. The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively. The second input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the first voltage sampling tracking control circuit, the third input terminal of the third voltage sampling tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling tracking control circuit is connected to the first terminal of the second MOS transistor Q2. The second input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the third voltage sampling tracking control circuit, the third input terminal of the fourth voltage sampling tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling tracking control circuit is connected to the second input terminal of the second voltage sampling storage circuit. The second target connection terminal is the connection terminal between the second terminal of the second MOS transistor Q2 and the second terminal of the first diode D1.

8. A circuit for recovering residual electricity from a spark-generated busbar according to claim 7, characterized in that, The second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12; The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5. The first end of the twentieth resistor R20 is connected to the second target connection terminal, and the second end of the twentieth resistor R20 is connected to the first end of the fifth capacitor C5 and the non-inverting input terminal of the fifth operational amplifier U12. The second end of the fifth capacitor C5 is grounded. The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit, respectively. The second end of the 21st resistor R21 is connected to the first end of the 22nd resistor R22, the first end of the sixth capacitor C6, and the first input terminal of the third voltage sampling and tracking control circuit, respectively; the other end of the 22nd resistor R22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, the third end of the third transistor VT3 is connected to the output terminal of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

9. A circuit for recovering residual electricity from a spark-generated busbar according to claim 8, characterized in that, The third voltage sampling and tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14, and a fourth AND gate U15; The non-inverting input of the sixth operational amplifier U13 is connected to the second terminal of the twenty-first resistor R21, the inverting input of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is connected to the first terminal of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit, respectively. The non-inverting input of the seventh operational amplifier U14 is connected to the second terminal of the twenty-fourth resistor R24 ​​and the first terminal of the seventh capacitor C7, respectively; the inverting input of the seventh operational amplifier U14 is connected to the first terminal of the twenty-third resistor R23; the output of the seventh operational amplifier U14 is connected to the first input of the fourth AND gate U15; the second terminal of the seventh capacitor C7 is grounded; the second terminal of the twenty-third resistor R23 is connected to the output of the first operational amplifier U1. The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

10. A circuit for recovering residual electricity from a spark-generated busbar according to claim 9, characterized in that, The fourth voltage sampling tracking control circuit includes a second comparator U17, a fifth AND gate U18, and a third inverter U19; The non-inverting input of the second comparator U17 is connected to the first terminal of the fifteenth resistor R15; the inverting input of the second comparator U17 is connected to the first terminal of the fourteenth resistor R14; the output of the second comparator U17 is connected to the first terminal of the sixteenth resistor R16 and the first input of the fifth AND gate U18; the second terminal of the fifteenth resistor R15 is connected to the output of the sixth operational amplifier U13; the second terminal of the fourteenth resistor R14 is connected to the output of the fifth operational amplifier U12; the second terminal of the sixteenth resistor R16 is connected to a 5V voltage output terminal. The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3; The input terminal of the third inverter U19 is connected to the first output terminal of the controller.

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