Low-power-consumption RC oscillator

Abstract

The utility model discloses a low-power-consumption RC oscillator. The low-power-consumption RC oscillator comprises a starting circuit, a current source circuit and a core oscillation circuit. The starting circuit is responsible for enabling the whole circuit to successfully reach a designed working point, and is turned off after being started; the current source circuit is responsible for generating a PTAT current; the core oscillation circuit is responsible for generating square wave oscillation. According to the utility model, an AVDD / AVSS dual-power supply architecture and a multipath current mirror structure are adopted, the stability of oscillation frequency is ensured, and meanwhile, the technical bottlenecks of starting time delay, temperature drift, power consumption efficiency compromise and the like of a traditional RC oscillator are effectively solved through the collaborative optimization design of the core oscillation circuit and the buffer output stage; and a novel solution is provided for the power management module of a miniaturized electronic system.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to an ultra-low power oscillator circuit based on a dual power supply architecture. Background Technology

[0002] Given the urgent need for ultra-low power clock sources in cutting-edge applications such as IoT terminals, biomedical implantable devices, and miniaturized wireless sensing nodes, current mainstream RC oscillators generally face a sharp contradiction between subthreshold operating region quiescent current and frequency stability. Under traditional single-supply architectures, the subthreshold leakage current of transistors is typically >5μA, which is difficult to meet the nA-level power consumption requirements of coin cell battery-powered scenarios. On the other hand, adopting a deep cutoff bias strategy will cause significant startup delay (greater than 10ms) and temperature drift (greater than 5000ppm / ℃). Utility Model Content

[0003] This invention provides a low-power RC oscillator that significantly reduces power consumption and startup delay through a multi-current mirror design. The oscillator has a temperature coefficient of 2322 ppm / ℃ over a temperature range of -40℃ to 125℃, and a total output noise of 2.57 mV. This invention features low power consumption, low noise, and low delay, making it suitable for use in button battery-powered circuits.

[0004] The low-power RC oscillator provided by this invention includes a startup circuit, a current source circuit, and a core oscillation circuit. The startup circuit is responsible for ensuring the overall circuit successfully reaches the designed operating point and then shuts off after startup; the current source circuit is responsible for generating a PTAT current; and the core oscillation circuit is responsible for generating a square wave oscillation.

[0005] The startup circuit includes: PMOS transistors M0 and M1; NMOS transistors M2, M3, M4, M5, M6, and M7; the sources of M0 and M1 are connected to the power supply VDD terminal, the gate of M0 is connected to node VBP, the drain of M0 is connected to the drain of M2, the source of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, the source of M4 is connected to the drain of M5, the source of M5 is connected to the drain of M6, and the source of M6 is connected to the drain of M7; the gates of M2, M3, M4, M5, M6, and M7 are interconnected with the drain of M2 and the gate of M1 to the node labeled VStartup_off; the drain of M1 is connected to the node labeled VStart_up.

[0006] The current source circuit includes: PMOS transistors M10 and M11; NMOS transistors M8 and M9 and resistor R0; the sources of M10 and M11 are connected to the power supply voltage VDD, the gates of M10 and M11 and the drains of M8 and M10 are connected to node VBP; the drains of M9 and M11 and the gates of M8 and M9 are connected to node VStart_up; the source of M9 is connected to the power supply VSS terminal; the source of M8 is connected to one end of resistor R0, and the other end of resistor R0 is connected to the power supply VSS terminal.

[0007] The core oscillation circuit includes: PMOS transistors M12 and M13; NMOS transistors M15, M16, and M17; capacitor C0; Schmitt trigger I0; and inverter I1. The sources of M12 and M13 are connected to the power supply VDD; the gates of M12 and M13 are connected to node VBP; the drain of M12 is connected to the drain of M15; the source of M15, the drain of M17, the gate of M17, and the gate of M16 are interconnected; the sources of M16 and M17 are connected to the power supply VSS; the drains of M13 and M16, one end of capacitor C0, and the input of Schmitt trigger I0 are interconnected; the output of Schmitt trigger I0 is connected to the input of inverter I1; the other end of capacitor C0 and the gate of M15 are connected to the output of inverter I1 and serve as the output port of the RC oscillator.

[0008] A resistor can be connected to the tail of the Schmitt trigger to prevent latch-up when it is suddenly turned on.

[0009] Technical features and effects of this utility model:

[0010] By innovatively integrating the Widlar current source module, Schmitt trigger shaping circuit, and adaptive startup control unit, and combining it with the MOSFET configuration strategy in the constant current operating region, low power consumption is achieved.

[0011] By adopting a dual power supply architecture of AVDD / AVSS and a multi-path current mirror structure, while ensuring the stability of the oscillation frequency, the core oscillation circuit and the buffer output stage are designed in a coordinated manner to effectively solve the technical bottlenecks of traditional RC oscillators, such as startup delay, temperature drift and power consumption efficiency trade-offs, providing a new solution for power management modules of miniaturized electronic systems. Attached Figure Description

[0012] Figure 1 This is the circuit schematic diagram of this utility model;

[0013] Figure 2 , Figure 3 The simulation parameter settings and some output results of this utility model are shown below.

[0014] Figure 4 The simulation results of the offset voltage of this utility model;

[0015] Figure 5 The noise results are from the simulation of this utility model. Detailed Implementation

[0016] The technical solution of this utility model will be described in detail below with reference to the accompanying drawings and embodiments to facilitate a better understanding.

[0017] like Figure 1 As shown, initially, the current in the Widlar current source is detected by transistor M0. If the chip enters the parallel point after power-on, resulting in no bias current being generated in the Widlar current source (i.e., VBP is high), then PMOS transistor M0 is in the off state. Therefore, Vstartup_off is low, and PMOS transistor M1 is turned on. Thus, the current generated by transistor M1 is injected into the current source from the VStart_up node.

[0018]

[0019] That is, the VStart_up node voltage gradually increases, causing the NMOS transistor in the Widlar current source to turn on, thereby generating the set PTAT current.

[0020] Secondly, once the current source generates current normally, the PMOS transistor M1 in the startup circuit turns on, mirroring the PTAT current in the Widlar current source. This current flows into an equivalent resistor (composed of NMOS transistors of the same size connected in series, with the overall size W remaining constant, and L being the sum of the L values ​​of all NMOS transistors; the NMOS diode connection is equivalent to a 1 / gm resistance). As a result, the Vstartup_off node voltage gradually increases, thereby turning off the M1 transistor in the startup circuit. Therefore, after startup is completed, the startup circuit will not affect other circuit modules.

[0021] The current source circuit provides bias current for the core oscillation circuit. The basic working principle is as follows: PMOS current mirrors M10 and M11 ensure that the currents in the two branches are equal. Since the NMOS transistors M8 and M9 have different sizes, their VGS are different under the same current conditions. The difference between the two ultimately falls on resistor R0, thereby generating PTAT current. The magnitude of the generated current is:

[0022] A Schmitt trigger can be viewed as an inverter with hysteresis characteristics, which can suppress the influence of noise on the comparison point voltage and has strong anti-interference ability.

[0023] Initially, the capacitor has zero charge, meaning the VNET1 junction voltage is low. Therefore, the OSC_OUT output is low, indicating that NMOS transistor M15 is off. Since M15 is off, the bottom NMOS transistors M17 and M16 are also off, while PMOS transistor M13 remains on. The PTAT current in its mirrored Widlar current source charges the capacitor, causing the VNET1 junction voltage to rise. When the VNET1 junction voltage rises to the Schmitt trigger's toggle point, the OSC_OUT output changes from low to high.

[0024] When the OSC_OUT output is high, NMOS transistor M15 will conduct. After M15 conducts, transistor M12 can mirror the PTAT current in the Widlar current source. This current provides a bias voltage to transistor M16 through diode-connected transistor M17, thus turning on transistor M16. Since transistor M16 is twice the size of transistor M17, and transistor M13 above it can only provide twice the current, transistor M16 will also draw current from the capacitor to meet the following requirements: This means that the voltage at node VNET1 will gradually decrease. When it decreases to the switching threshold voltage of the Schmitt trigger, the output voltage OSC_OUT will change from high level to logic low level again, thus repeating the above process and finally achieving high and low level output of OSC_OUT.

Claims

1. A low-power RC oscillator, comprising a startup circuit, a current source circuit, and a core oscillation circuit, characterized in that: The startup circuit includes: PMOS transistors M0 and M1; NMOS transistors M2, M3, M4, M5, M6, and M7; the sources of M0 and M1 are connected to the power supply VDD terminal, the gate of M0 is connected to node VBP, the drain of M0 is connected to the drain of M2, the source of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, the source of M4 is connected to the drain of M5, the source of M5 is connected to the drain of M6, and the source of M6 is connected to the drain of M7; the gates of M2, M3, M4, M5, M6, and M7, the drain of M2, and the gate of M1 are interconnected with the node labeled VStartup_off; the drain of M1 is connected to the node labeled VStart_up. The current source circuit includes: PMOS transistors M10 and M11; NMOS transistors M8 and M9 and resistor R0; the sources of M10 and M11 are connected to the power supply voltage VDD, the gates of M10 and M11 and the drains of M8 and M10 are connected to node VBP; the drains of M9 and M11 and the gates of M8 and M9 are connected to node VStart_up; the source of M9 is connected to the power supply VSS terminal; the source of M8 is connected to one end of resistor R0, and the other end of resistor R0 is connected to the power supply VSS terminal. The core oscillation circuit includes: PMOS transistors M12 and M13; NMOS transistors M15, M16, and M17; capacitor C0; Schmitt trigger I0; and inverter I1. The sources of M12 and M13 are connected to the power supply VDD; the gates of M12 and M13 are connected to node VBP; the drain of M12 is connected to the drain of M15; the source of M15, the drain of M17, the gate of M17, and the gate of M16 are interconnected; the sources of M16 and M17 are connected to the power supply VSS; the drains of M13 and M16, one end of capacitor C0, and the input of Schmitt trigger I0 are interconnected; the output of Schmitt trigger I0 is connected to the input of inverter I1; the other end of capacitor C0 and the gate of M15 are connected to the output of inverter I1 and serve as the output port of the RC oscillator.

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