Direct current offset suppression circuit and variable gain amplifier
By designing the bias current module and common-mode feedback module in the DC offset suppression circuit, the current utilization rate was improved, the problem of low current utilization efficiency was solved, and the normal operation of the variable gain amplifier was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-05-12
AI Technical Summary
In the existing technology, variable gain amplifiers have the problem of low current utilization efficiency in DC offset suppression circuits, which leads to output saturation and affects the normal operation of subsequent modules.
By designing a DC offset suppression circuit that includes a bias current module, an input stage differential pair module, a feedback input stage differential pair module, and a common-mode feedback module, the current utilization rate is improved, and the output signal is adjusted to the target common-mode signal by the common-mode feedback module, thereby reducing the DC voltage.
It effectively improves current utilization efficiency, reduces the impact of DC offset on the circuit, ensures normal transmission of high-frequency signals, and avoids output saturation.
Smart Images
Figure CN224233655U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuits, and in particular to a DC offset suppression circuit and a variable gain amplifier. Background Technology
[0002] In wireless LAN and global microwave interconnection access receivers, variable gain amplifiers (VGAs) need to provide high gain (e.g., 60dB or even higher). However, the DC offset generated at the mixer output, after being amplified by the VGA, can cause output saturation, affecting the normal operation of subsequent modules. Therefore, DC-offset cancellation (DCOC) technology is required.
[0003] In existing technologies, such as Figure 1 As shown, DC offset suppression can be indirectly achieved by introducing a feedback network of a low-pass filter (LPF) composed of a DC offset subtraction circuit. Figure 2 As shown, in the existing DC offset subtraction circuit, an input differential pair is added as the transconductance stage of the DC offset suppression feedback loop to achieve the superposition of the input stage current and the feedback stage current. However, when the tail current is determined, the current of the input stage differential pair decreases, resulting in a decrease in transconductance and a problem of low current utilization efficiency.
[0004] Therefore, improving the current utilization efficiency of DC offset suppression circuits is an urgent problem to be solved. Utility Model Content
[0005] The purpose of this invention is to provide a DC offset suppression circuit and a variable gain amplifier to overcome the shortcomings of the prior art, thereby improving the current utilization efficiency of the DC offset suppression circuit.
[0006] The solution presented in this application is implemented through the following steps.
[0007] In a first aspect, the present application provides an example of a DC offset suppression circuit, including a low-pass filter circuit and a DC offset subtraction circuit; the DC offset subtraction circuit includes a bias current module, an input stage differential pair module, a feedback input stage differential pair module, and a common-mode feedback module.
[0008] The bias current module is used to provide bias current to the input differential pair module according to the first bias signal;
[0009] The input-level differential pair module is used to convert the received differential input voltage signal into a first differential current signal output to the differential output terminal;
[0010] The feedback input stage differential pair module is used to convert the differential feedback voltage signal output by the low-pass filter circuit into a second differential current signal output to the differential output terminal.
[0011] The common-mode feedback module is used to detect the output signal composed of the first differential current signal and the second differential current signal, and to adjust the output signal to the target common-mode signal.
[0012] According to some examples of this application, the bias current module includes a first NMOS transistor, the source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is used to receive the first bias signal, and the drain of the first NMOS transistor provides the bias current.
[0013] According to some examples of this application, the input stage differential pair module includes a second NMOS transistor and a third NMOS transistor;
[0014] The source of the second NMOS transistor and the source of the third NMOS transistor are connected to the output terminal of the bias current module;
[0015] The gate of the second NMOS transistor is used to receive the inverted input signal in the differential input voltage signal, and the gate of the third NMOS transistor is used to receive the non-inverted input signal in the differential input voltage signal;
[0016] The drain of the second NMOS transistor is connected to the positive output terminal of the differential output terminal, and the drain of the third NMOS transistor is connected to the negative output terminal of the differential output terminal.
[0017] According to some examples of this application, the second NMOS transistor and the third NMOS transistor are transistors with equal channel width-to-length ratios.
[0018] According to some examples of this application, the feedback input stage differential pair module includes a first PMOS transistor and a second PMOS transistor, and the common-mode feedback module includes a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, and a first operational amplifier;
[0019] The gates of the first PMOS transistor and the second PMOS transistor are used to receive the second bias signal;
[0020] The drain of the first PMOS transistor is connected to the positive output terminal of the differential output terminal, and the drain of the second PMOS transistor is connected to the negative output terminal of the differential output terminal.
[0021] The substrate of the first PMOS transistor is used to receive the positive feedback signal in the differential feedback voltage signal;
[0022] The substrate of the second PMOS transistor is used to receive the negative phase feedback signal in the differential feedback voltage signal;
[0023] The source of the first PMOS transistor, the source of the second PMOS transistor, the drain of the third PMOS transistor, and the drain of the fourth PMOS transistor are connected.
[0024] The first end of the first resistor is connected to the positive output terminal, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative output terminal.
[0025] The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor for power supply.
[0026] The gate of the fourth PMOS transistor receives a third bias signal;
[0027] The negative input terminal of the first operational amplifier is used to receive the target common-mode signal, the positive input terminal of the first operational amplifier is connected to the second terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the gate of the third PMOS transistor.
[0028] According to some examples of this application, the first PMOS transistor and the second PMOS transistor are transistors with equal channel width-to-length ratios.
[0029] According to some examples of this application, the resistance values of the first resistor and the second resistor are equal.
[0030] According to some examples of this application, the low-pass filter circuit includes a first resistor, a second resistor, a second operational amplifier, a first capacitor, and a second capacitor;
[0031] The first terminal of the first resistor receives the negative output signal of the variable gain amplifier, and the second terminal of the first resistor is connected to the positive input terminal of the second operational amplifier.
[0032] The first terminal of the second resistor receives the positive output signal of the variable gain amplifier, and the second terminal of the second resistor is connected to the negative input terminal of the second operational amplifier.
[0033] The first terminal of the first capacitor is connected to the non-inverting input terminal of the second operational amplifier, and the second terminal of the first capacitor is connected to the non-inverting output terminal of the second operational amplifier.
[0034] The first end of the second capacitor is connected to the negative input terminal of the second operational amplifier, and the second end of the second capacitor is connected to the negative output terminal of the second operational amplifier.
[0035] Secondly, examples of this application present a variable gain amplifier including the DC offset suppression circuit described in the first aspect above.
[0036] According to some examples of this application, the variable gain amplifier further includes a variable gain amplification unit;
[0037] The differential input terminal of the variable gain amplifier unit is connected to the differential output terminal of the DC offset subtraction circuit in the DC offset suppression circuit, and the differential output terminal of the variable gain amplifier unit is connected to the differential input terminal of the low-pass filter circuit in the DC offset suppression circuit.
[0038] In the DC offset suppression circuit described in the foregoing example of this application, the bias current module provides bias current to the input stage differential pair module. The input stage differential pair module receives and converts the differential input voltage signal into a first differential current signal, which is then output to the differential output terminal. The feedback input stage differential pair module converts the differential feedback voltage signal output from the low-pass filter circuit into a second differential current signal, which is then output to the differential output terminal. In the DC offset suppression circuit provided in this application, the bias current is only used by the input stage differential pair module, which can effectively improve the current utilization rate. Attached Figure Description
[0039] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.
[0040] Figure 1 This is a schematic diagram of a variable gain amplifier with DC offset suppression circuitry in the prior art.
[0041] Figure 2 This is a schematic diagram of the structure of a DC offset subtraction circuit in the prior art;
[0042] Figure 3 This is a schematic diagram of the DC offset suppression circuit in one example of this application;
[0043] Figure 4 This is a schematic diagram of the DC offset subtraction circuit in one example of this application;
[0044] Figure 5 This is a schematic diagram of a variable gain amplifier in one example of this application. Detailed Implementation
[0045] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0046] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0048] In wireless LAN and global microwave interconnection access receivers, variable gain amplifiers (VGAs) need to provide 60dB or even higher gain. The DC offset generated at the mixer output of these receivers is approximately tens of millivolts. This DC offset, after being amplified by the VGA, can cause output saturation, thus affecting the normal operation of subsequent modules. Therefore, DC offset suppression (DCOC) is required. DCOC reduces the impact of low-frequency offset on the circuit without affecting the high-frequency signal, essentially acting as a high-pass filter (HPF). In existing technologies, such as... Figure 1 As shown, the DC offset suppression circuit can indirectly achieve HPF by introducing a low-pass filter (LPF) feedback network with a DC offset subtraction circuit. Figure 2 As shown, in the existing DC offset subtraction circuit, the superposition of the input stage current and the feedback stage current is achieved by adding a pair of input differential pairs as the transconductance stage of the DCOC feedback loop. However, when the tail current is determined, a portion of the current of the NMOS transistor M1 in the circuit is diverted to the current of the NMOS transistor M... 2c and NMOS transistor M2D The DCOC loop feedback input stage, as formed by the circuit, causes current to flow through the NMOS transistor M. 2A and NMOS transistor M 2B The current in the differential input stage decreases, and this decrease in current causes the NMOS transistor M to... 2A and NMOS transistor M 2B The transconductance decreases, which in turn reduces the gain of the DC offset subtraction circuit, which is the amplification stage. Therefore, the DC offset suppression circuit with this DC offset subtraction circuit exhibits lower current utilization efficiency.
[0049] Based on this, such as Figures 3 to 4 As shown, an embodiment of this utility model provides a DC offset suppression circuit, which includes a low-pass filter circuit and a DC offset subtraction circuit. The DC offset subtraction circuit includes a bias current module 110, an input stage differential pair module 120, a feedback input stage differential pair module 130, and a common-mode feedback module.
[0050] Bias current module 110, used to adjust current according to the first bias signal (V BN1 Provide bias current to the input stage differential pair module 120;
[0051] Input-level differential pair module 120 is used to input the received differential input voltage signal (V INN V INP This is converted into the first differential current signal, which is output to the differential output terminal.
[0052] The feedback input stage differential pair module 130 is used to input the differential feedback voltage signal (V) from the low-pass filter circuit. FBP V FBN This is converted into a second differential current signal, which is output to the differential output terminal.
[0053] The common-mode feedback module is used to detect the output signal (V) composed of the first differential current signal and the second differential current signal. OUTP V OUTN ), and adjust the output signal to the target common-mode signal (V). CM ).
[0054] In the DC offset suppression circuit described in the foregoing example of this application, the bias current module 110 provides bias current to the input stage differential pair module 120. The input stage differential pair module 120 receives and converts the differential input voltage signal into a first differential current signal, which is then output to the differential output terminal. The feedback input stage differential pair module 130 converts the differential feedback voltage signal output from the low-pass filter circuit into a second differential current signal, which is then output to the differential output terminal. In the DC offset suppression circuit provided in this application, the bias current is only used by the input stage differential pair module 120, which can effectively improve the current utilization rate. Furthermore, in the circuit provided in this application, the common-mode feedback module makes the output DC voltage of the DC offset subtraction circuit equal to the voltage of the target common-mode signal.
[0055] In one embodiment of this application, the bias current module 110 includes a first NMOS transistor M1, the source of which is grounded, and the gate of which is used to receive a first bias signal V. BN1 The drain of the first NMOS transistor M1 provides the bias current.
[0056] In the circuit of this application, since the source of the first NMOS transistor M1 is grounded, the first bias signal V can be set. BN1 The voltage is set to determine the drain current of the first NMOS transistor M1, so as to provide a stable bias current for the input stage differential pair module 120.
[0057] In one embodiment of this application, the input stage differential pair module 120 includes a second NMOS transistor M. 2A and the third NMOS transistor M 2B ;
[0058] Second NMOS transistor M 2A The source and the third NMOS transistor M 2B The source is connected to the output of the bias current module 110;
[0059] Second NMOS transistor M 2A The gate is used to receive the inverted input signal V in the differential input voltage signal. INN The third NMOS transistor M 2B The gate is used to receive the in-phase input signal V in the differential input voltage signal. INP ;
[0060] Second NMOS transistor M 2A The drain of the third NMOS transistor is connected to the non-inverting output terminal of the differential output terminal. 2B The drain of the differential output is connected to the negative output terminal.
[0061] Specifically, when the bias current module 110 includes a first NMOS transistor M1, the second NMOS transistor M... 2AThe source and the third NMOS transistor M 2B The source is connected to the drain of the first NMOS transistor M1, and all the current of the first NMOS transistor M1 flows into the differential input stage composed of NMOS transistors M2A and M2B, thereby improving the current utilization efficiency of the circuit.
[0062] In one embodiment of this application, the second NMOS transistor M 2A and the third NMOS transistor M 2B These are transistors with equal channel width-to-length ratios.
[0063] Furthermore, the second NMOS transistor M 2A and the third NMOS transistor M 2B The channel width W and channel length L are both equal.
[0064] In one embodiment of this application, the feedback input stage differential pair module 130 includes a first PMOS transistor M 3A Second PMOS transistor M 3B The common-mode feedback module includes a third PMOS transistor M. 4A The fourth PMOS transistor M 4B The first resistor R1, the second resistor R2, and the first operational amplifier OP1;
[0065] First PMOS transistor M 3A The gate and the second PMOS transistor M 3B The gate is used to receive the second bias signal V. BP2 ;
[0066] First PMOS transistor M 3A The drain of the first PMOS transistor is connected to the non-inverting output terminal of the differential output terminal, and the second PMOS transistor M... 3B The drain of the differential output is connected to the negative output terminal;
[0067] First PMOS transistor M 3A The substrate is used to receive the positive feedback signal V in the differential feedback voltage signal. FBP ;
[0068] Second PMOS transistor M 3B The substrate is used to receive the negative phase feedback signal V in the differential feedback voltage signal. FBN ;
[0069] First PMOS transistor M 3A The source of the second PMOS transistor M 3B The source of the third PMOS transistor M 4A The drain of the fourth PMOS transistor M 4B Drain connection;
[0070] The first end of the first resistor R1 is connected to the positive output terminal, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the negative output terminal.
[0071] Third PMOS transistor M 4A The source and the fourth PMOS transistor M 4B The source terminal is connected to the power supply V. DD ;
[0072] Fourth PMOS transistor M 4B The gate receives the third bias signal V BP1 ;
[0073] The negative inverting input of the first operational amplifier OP1 is used to receive the target common-mode signal V. CM The non-inverting input terminal of the first operational amplifier OP1 is connected to the second terminal of the first resistor R1, and the output terminal of the first operational amplifier OP1 is connected to the third PMOS transistor M. 4A The gate.
[0074] In the DC offset suppression circuit provided in this application, the signal V at the output terminal of the DCOC feedback loop is... FBP and V FBN The outputs are respectively sent to the first PMOS transistor M. 3A The second PMOS transistor M 3B The substrate eliminates the need for deep N-well transistors, reducing circuit manufacturing costs. Furthermore, the common-mode feedback module in the DC offset subtraction circuit ensures that the DC voltage at the differential output of the DC offset subtraction circuit equals the target common-mode voltage V. CM .
[0075] In one embodiment of this application, the first PMOS transistor M 3A Second PMOS transistor M 3B These are transistors with equal channel width-to-length ratios.
[0076] Furthermore, the first PMOS transistor M 3A Second PMOS transistor M 3B The channel width W and channel length L are both equal.
[0077] In one embodiment of this application, the resistance values of the first resistor and the second resistor are equal.
[0078] In one embodiment of this application, the low-pass filter circuit includes a first resistor RPR1, a second resistor RPR2, a second operational amplifier OP2, and a first capacitor C. M1 Second capacitor C M2 ;
[0079] The first terminal of the first resistor RPR1 receives the negative output signal V from the variable gain amplifier.OUTAN The second terminal of the first resistor RPR1 is connected to the non-inverting input terminal of the second operational amplifier OP2;
[0080] The first terminal of the second resistor RPR2 receives the inverting output signal V from the variable gain amplifier. OUTAP The second terminal of the second resistor RPR2 is connected to the negative input terminal of the second operational amplifier OP2;
[0081] First capacitor C M1 The first terminal is connected to the non-inverting input terminal of the second operational amplifier OP2, and the first capacitor C M1 The second terminal is connected to the non-inverting output terminal of the second operational amplifier OP2;
[0082] Second capacitor C M2 The first terminal is connected to the negative inverting input terminal of the second operational amplifier OP2, and the second capacitor C M2 The second terminal is connected to the negative output terminal of the second operational amplifier OP2.
[0083] Specifically, the DC offset suppression circuit provided in this application consists of a first resistor RPR1, a second resistor RPR2, a second operational amplifier OP2, and a first capacitor C. M1 Second capacitor C M2 The low-pass filter circuit is used to receive the differential output signal of the variable gain amplifier and generate a differential feedback voltage signal to be output to the DC offset subtraction circuit.
[0084] Based on the same utility model concept, such as Figure 5 As shown in the figure, this utility model embodiment also proposes a variable gain amplifier, including the above-mentioned DC offset suppression circuit.
[0085] In one embodiment of this application, the variable gain amplifier further includes a variable gain amplification unit (i.e., a VGA unit);
[0086] The differential input terminal of the variable gain amplifier unit is connected to the differential output terminal of the DC offset subtraction circuit in the DC offset suppression circuit, and the differential output terminal of the variable gain amplifier unit is connected to the differential input terminal of the low-pass filter circuit in the DC offset suppression circuit.
[0087] In this specification, references to terms such as "some embodiments" or "examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0088] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.
Claims
1. A DC offset suppression circuit, characterized in that, It includes a low-pass filter circuit and a DC offset subtraction circuit; the DC offset subtraction circuit includes a bias current module, an input stage differential pair module, a feedback input stage differential pair module, and a common-mode feedback module; The bias current module is used to provide bias current to the input differential pair module according to the first bias signal; The input-level differential pair module is used to convert the received differential input voltage signal into a first differential current signal output to the differential output terminal; The feedback input stage differential pair module is used to convert the differential feedback voltage signal output by the low-pass filter circuit into a second differential current signal output to the differential output terminal. The common-mode feedback module is used to detect the output signal composed of the first differential current signal and the second differential current signal, and to adjust the output signal to the target common-mode signal.
2. The DC offset suppression circuit according to claim 1, characterized in that, The bias current module includes a first NMOS transistor, the source of which is grounded, the gate of which is used to receive the first bias signal, and the drain of which provides the bias current.
3. The DC offset suppression circuit according to claim 1, wherein the input stage differential pair module includes a second NMOS transistor and a third NMOS transistor; The source of the second NMOS transistor and the source of the third NMOS transistor are connected to the output terminal of the bias current module; The gate of the second NMOS transistor is used to receive the inverted input signal in the differential input voltage signal, and the gate of the third NMOS transistor is used to receive the non-inverted input signal in the differential input voltage signal; The drain of the second NMOS transistor is connected to the positive output terminal of the differential output terminal, and the drain of the third NMOS transistor is connected to the negative output terminal of the differential output terminal.
4. The DC offset suppression circuit according to claim 3, characterized in that, The second NMOS transistor and the third NMOS transistor are transistors with equal channel width-to-length ratios.
5. The DC offset suppression circuit according to claim 1, characterized in that, The feedback input stage differential pair module includes a first PMOS transistor and a second PMOS transistor, and the common-mode feedback module includes a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, and a first operational amplifier; The gates of the first PMOS transistor and the second PMOS transistor are used to receive the second bias signal; The drain of the first PMOS transistor is connected to the positive output terminal of the differential output terminal, and the drain of the second PMOS transistor is connected to the negative output terminal of the differential output terminal. The substrate of the first PMOS transistor is used to receive the positive feedback signal in the differential feedback voltage signal; The substrate of the second PMOS transistor is used to receive the negative phase feedback signal in the differential feedback voltage signal; The source of the first PMOS transistor, the source of the second PMOS transistor, the drain of the third PMOS transistor, and the drain of the fourth PMOS transistor are connected. The first end of the first resistor is connected to the positive output terminal, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative output terminal. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor for power supply. The gate of the fourth PMOS transistor receives a third bias signal; The negative input terminal of the first operational amplifier is used to receive the target common-mode signal, the positive input terminal of the first operational amplifier is connected to the second terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the gate of the third PMOS transistor.
6. The DC offset suppression circuit according to claim 5, characterized in that, The first PMOS transistor and the second PMOS transistor are transistors with equal channel width-to-length ratios.
7. The DC offset suppression circuit according to claim 5, characterized in that, The resistance values of the first resistor and the second resistor are equal.
8. The DC offset suppression circuit according to claim 1, characterized in that, The low-pass filter circuit includes a first resistor, a second resistor, a second operational amplifier, a first capacitor, and a second capacitor; The first terminal of the first resistor receives the negative output signal of the variable gain amplifier, and the second terminal of the first resistor is connected to the positive input terminal of the second operational amplifier. The first terminal of the second resistor receives the positive output signal of the variable gain amplifier, and the second terminal of the second resistor is connected to the negative input terminal of the second operational amplifier. The first terminal of the first capacitor is connected to the non-inverting input terminal of the second operational amplifier, and the second terminal of the first capacitor is connected to the non-inverting output terminal of the second operational amplifier. The first end of the second capacitor is connected to the negative input terminal of the second operational amplifier, and the second end of the second capacitor is connected to the negative output terminal of the second operational amplifier.
9. A variable gain amplifier, characterized in that, Includes the DC offset suppression circuit according to any one of claims 1 to 8.
10. The variable gain amplifier according to claim 9, characterized in that, The variable gain amplifier also includes a variable gain amplification unit; The differential input terminal of the variable gain amplifier unit is connected to the differential output terminal of the DC offset subtraction circuit in the DC offset suppression circuit, and the differential output terminal of the variable gain amplifier unit is connected to the differential input terminal of the low-pass filter circuit in the DC offset suppression circuit.