Chip pin multiplexing circuit, chip and electronic equipment
By using a chip pin multiplexing circuit, enable control, fault detection, and fault recovery configuration are integrated into a single pin, solving the problem of increased chip size and cost in existing technologies and achieving a reduction in PCB area and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN KIWI MICROELECTRONICS TECH CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-05-12
AI Technical Summary
The enable control, fault detection and fault recovery configuration circuits of existing chips require three pins to perform the functions, which leads to an increase in chip size and PCB area, and higher costs.
By using a single pin multiplexing circuit, enable control, fault detection, and fault recovery configuration are integrated into a single pin. Pull-up circuits, pull-down circuits, and dual threshold comparator circuits are used to achieve chip multiplexing, reducing the number of internal components.
This effectively reduces PCB area and pin count, decreases chip package size, and lowers costs.
Smart Images
Figure CN224233677U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronics, specifically but not limited to a chip pin multiplexing circuit, a chip, and an electronic device. Background Technology
[0002] Current existing enable control, fault detection and fault recovery configuration circuits, such as Figure 1 As shown, the EN pin forces the chip to shut down its output when an external level is pulled low, and enables the chip's output when an external level is high. The FAULT pin pulls up its internal open-drain NMOS structure through an external resistor. When a fault is detected, the open-drain NMOS structure turns on, and the FAULT pin is forcibly pulled down. The external MCU detects the falling edge of the FAULT pin to determine whether a fault has occurred. After the fault is cleared, the RCIN pin is charged to the Schmitt trigger threshold through an external RC network to re-enable the output.
[0003] Application scenarios for enable control, fault detection, and fault recovery configuration circuits, such as Figure 2 As shown, this chip integrates a three-phase high-voltage half-bridge driver, dead time, UVLO, overcurrent protection OCP, and an externally adjustable protection clearing circuit. A single chip requires three pins to implement enable control, fault detection, and fault recovery functions, and the internal components are redundant. For example, the FAULT and RCIN pins are each connected to an open-drain NMOS structure, and the RCIN and EN pins are each connected to a Schmitt trigger. This not only increases the chip size and PCB area but also the chip cost.
[0004] In view of this, there is a need to provide a new structure or control method in order to solve at least some of the above problems. Utility Model Content
[0005] In response to at least one or more problems in the background art, this utility model proposes a chip pin multiplexing circuit. By multiplexing the same pin, enable control, fault detection and fault recovery configuration are integrated into a single pin, reducing the number of internal components, effectively reducing the occupied PCB area and the number of pins, reducing the chip package size, and effectively reducing costs.
[0006] According to one aspect of the present invention, a chip pin multiplexing circuit includes:
[0007] The multiplexed pin has one end coupled to the pull-up circuit, pull-down circuit and third detection circuit, and the other end coupled to the external MCU.
[0008] A pull-up circuit, one end of which is coupled to the multiplexed pin and the other end is connected to the internal voltage, is used to provide a weak pull-up level;
[0009] A pull-down circuit, one end of which is coupled to the multiplexed pin and the other end is grounded, and the control terminal is connected to a fault signal to provide a low level based on the fault signal;
[0010] A dual-threshold comparison circuit has a built-in preset dual threshold. Its input is coupled to the multiplexed pin, and its output is coupled to an output control circuit. It is used to output a control signal based on the level of the multiplexed pin and the dual threshold.
[0011] Optionally, the pull-up circuit includes a pull-up resistor, one end of which is coupled to the multiplexed pin and the other end of which is coupled to the internal voltage.
[0012] Optionally, the pull-up resistor has a resistance of 2MΩ ± 25%.
[0013] Optionally, the internal voltage is 2.1 to 3.5V.
[0014] Optionally, the pull-down circuit includes: a switching transistor, the drain of which is coupled to the multiplexed pin, the source of which is grounded, and the gate of which is coupled to a fault signal detection circuit, for being turned on based on a first state of a fault signal and turned off based on a second state of a fault signal.
[0015] Optionally, the fault signal detection circuit includes an OR gate, whose first input terminal is connected to an undervoltage fault signal, its second input terminal is connected to a short-circuit fault signal, and its output terminal is coupled to the gate of the switching transistor.
[0016] Optionally, the switching transistor is an NMOS transistor.
[0017] Optionally, the dual threshold comparison circuit includes a Schmitt trigger, whose input is coupled to the multiplexed pin and whose output is coupled to an output control circuit, for outputting a control signal based on the level of the multiplexed pin.
[0018] Optionally, the first threshold voltage of the Schmitt trigger is 2.1V±5%, the second threshold voltage is 1.0V±5%, and the hysteresis voltage window is ≥1.1V±0.05V.
[0019] According to another aspect of the present invention, a chip includes any of the above-described chip pin multiplexing circuits.
[0020] According to another aspect of the present invention, an electronic device includes the aforementioned chip.
[0021] The chip pin multiplexing circuit, chip, and electronic device proposed in this utility model integrate enable control, fault detection, and fault recovery configuration into a single pin by reusing the same pin. This reduces the number of internal components, effectively reduces the occupied PCB area and the number of pins, reduces the chip package size, and effectively reduces costs. Attached Figure Description
[0022] The accompanying drawings are provided to further illustrate the present invention and, together with the description, serve to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0023] Figure 1 A schematic diagram of the circuit structure for existing enable control, fault detection, and fault recovery configurations is shown.
[0024] Figure 2 This diagram illustrates an external application of an existing enable control, fault detection, and fault recovery configuration.
[0025] Figure 3 A schematic diagram of the chip pin multiplexing circuit structure of this utility model is shown;
[0026] Figure 4 A schematic diagram of an embodiment of the present invention is shown;
[0027] Figure 5 A schematic diagram of another embodiment of the present invention is shown;
[0028] Figure 6 A schematic diagram of yet another embodiment of the present invention is shown. Detailed Implementation
[0029] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.
[0030] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of the same or similar prior art with some technical features in the embodiments are also within the scope of the description and protection of this utility model.
[0031] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more.
[0032] This utility model proposes a chip pin multiplexing circuit, such as Figure 3As shown, it includes multiplexed pins EN / FLT, pull-up circuits, pull-down circuits, and dual threshold comparator circuits, wherein:
[0033] One end of the multiplexed pin EN / FLT is coupled to the pull-up circuit, pull-down circuit and third detection circuit, and the other end is coupled to the external MCU.
[0034] One end of the pull-up circuit is coupled to the multiplexed pin EN / FLT, and the other end is connected to the internal voltage to provide a weak pull-up level.
[0035] One end of the pull-down circuit is coupled to the multiplexed pin EN / FLT, and the other end is grounded. The control terminal is connected to a fault signal to provide a low level based on the fault signal.
[0036] The dual threshold comparison circuit has a built-in preset dual threshold. Its input is coupled to the multiplexed pin EN / FLT, and its output is coupled to the output control circuit. It is used to output a control signal based on the level of the multiplexed pin EN / FLT and the dual threshold.
[0037] In one embodiment, the pull-up circuit includes a pull-up resistor R1, one end of which is coupled to the multiplexed pin EN / FLT, and the other end is coupled to the internal voltage. Specifically, the resistance of the pull-up resistor R1 is 2MΩ. Specifically, the internal voltage is 3.3V. In a specific implementation, by default, the pull-up circuit sets the multiplexed pin EN / FLT to a pull-up level of 3.3V, at which point the chip is in an enabled state; such as Figure 4 As shown, when the SD signal of the external MCU actively pulls down the voltage of the multiplexed pin EN / FLT, the pull-up level of 3.3V is overridden, and the chip's output is forcibly shut down. When the SD signal of the external MCU returns to a high level, because the external capacitor C has an nF capacitance and the MCU has a strong output capability, the chip's response to restore output is extremely fast. In another specific embodiment, after the chip fault is cleared, the pull-up circuit charges the multiplexed pin EN / FLT through an external RC network.
[0038] In another embodiment, the pull-down circuit includes a switching transistor M1. The drain of the switching transistor M1 is coupled to the multiplexed pin EN / FLT, the source is grounded, and the gate is coupled to a fault signal detection circuit for turning on based on a first state of a fault signal and turning off based on a second state of a fault signal. The first state of the fault signal indicates that the chip has a fault, and the second state indicates that the chip does not have a fault. Specifically, the switching transistor M1 is an NMOS transistor. In other embodiments, the switching transistor M1 can be other switching elements such as NPN. Preferably, the fault signal detection circuit includes an OR gate, with the first input terminal connected to an undervoltage fault signal UVLO, the second input terminal connected to a short-circuit fault signal OCP, and the output terminal coupled to the gate of the switching transistor M1. In a specific embodiment, such as... Figure 5 As shown, when the chip detects an undervoltage fault signal UVLO or a short-circuit fault signal OCP, the NMOS transistor is controlled to change from the off state to the on state, forcibly pulling the voltage of the multiplexed pin EN / FLT low to GND, forming a clear low-level signal. The charge of the external capacitor C is quickly drained, and the chip's output is forcibly shut off. Using an NMOS transistor ensures that the pin level returns to zero quickly and stably, avoiding level ambiguity caused by leakage current. The external MCU can identify the chip's fault information by detecting the falling edge of the multiplexed pin EN / FLT.
[0039] In yet another embodiment, the dual threshold comparison circuit includes a Schmitt trigger, such as... Figure 6 As shown, the input of the Schmitt trigger is coupled to the multiplexed pin EN / FLT, and the output is coupled to an output control circuit for outputting a control signal based on the level of the multiplexed pin EN / FLT. Specifically, the high threshold voltage of the Schmitt trigger is 2.1V, and the low threshold voltage is 1.0V. In one specific embodiment, as... Figure 6 As shown, after the fault is cleared, the chip does not immediately resume output. Instead, a recovery time is specified by connecting an external RC circuit to the multiplexed pin EN / FLT. After the fault is cleared, the NMOS transistor is turned off. At this time, the external capacitor C begins to charge exponentially through the power supply voltage VCC and the internal 3.3V weak pull-up voltage until the voltage of the external capacitor C reaches the high-level threshold of 2.1V set by the Schmitt trigger. The Schmitt trigger then outputs an enable signal, and the chip output is turned back on. Before the voltage of the external capacitor C rises to the high-level threshold of 2.1V, the Schmitt trigger outputs a low level, and the chip output remains off. Here, a fault recovery time is defined by combining the internal Schmitt trigger with the external RC circuit. Before the voltage of the multiplexed pin EN / FLT rises to 2.1V, the chip output remains off, which can avoid repeated triggering of faults (such as short-circuit faults), thereby ensuring the safe and reliable operation of the chip.
[0040] This utility model also proposes a chip that includes the above-mentioned chip pin multiplexing circuit.
[0041] This invention also proposes an electronic device comprising the aforementioned chip.
[0042] The chip pin multiplexing circuit, chip, and electronic device proposed in this utility model integrate enable control, fault detection, and fault recovery configuration into a single pin by reusing the same pin. This reduces the number of internal components, effectively reduces the occupied PCB area and the number of pins, reduces the chip package size, and effectively reduces costs.
[0043] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.
[0044] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages described in the specification may not be apparent in actual experimental examples due to uncertainties in specific conditions or parameters or other factors, and such descriptions are not intended to limit the scope of the utility model. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalent components of the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the utility model.
Claims
1. A chip pin multiplexing circuit, characterized in that, include: The multiplexed pin has one end coupled to the pull-up circuit, pull-down circuit and third detection circuit, and the other end coupled to the external MCU. A pull-up circuit, one end of which is coupled to the multiplexed pin and the other end is connected to the internal voltage, is used to provide a weak pull-up level; A pull-down circuit, one end of which is coupled to the multiplexed pin and the other end is grounded, and the control terminal is connected to a fault signal to provide a low level based on the fault signal; A dual-threshold comparison circuit has a built-in preset dual threshold. Its input is coupled to the multiplexed pin, and its output is coupled to an output control circuit. It is used to output a control signal based on the level of the multiplexed pin and the dual threshold.
2. The chip pin multiplexing circuit according to claim 1, characterized in that, The pull-up circuit includes: A pull-up resistor, one end of which is coupled to the multiplexed pin, and the other end of which is coupled to the internal voltage.
3. The chip pin multiplexing circuit according to claim 2, characterized in that, The pull-up resistor has a resistance of 2MΩ ± 25%.
4. The chip pin multiplexing circuit according to claim 1 or 2, characterized in that, The internal voltage is 2.1 to 3.5V.
5. The chip pin multiplexing circuit according to claim 1, characterized in that, The pull-down circuit includes: The switching transistor has its drain coupled to the multiplexed pin, its source grounded, and its gate coupled to the fault signal detection circuit. It is used to turn on based on a first state of the fault signal and turn off based on a second state of the fault signal.
6. The chip pin multiplexing circuit according to claim 5, characterized in that, The fault signal detection circuit includes: The OR gate has an undervoltage fault signal connected to its first input terminal, a short-circuit fault signal connected to its second input terminal, and its output terminal coupled to the gate of the switching transistor.
7. The chip pin multiplexing circuit according to claim 5, characterized in that, The switching transistor is an NMOS transistor.
8. The chip pin multiplexing circuit according to claim 1, characterized in that, The dual threshold comparison circuit includes: A Schmitt trigger, whose input is coupled to the multiplexed pin and whose output is coupled to an output control circuit, is used to output a control signal based on the level of the multiplexed pin.
9. The chip pin multiplexing circuit according to claim 8, characterized in that, The first threshold voltage of the Schmitt trigger is 2.1V±5%, the second threshold voltage is 1.0V±5%, and the hysteresis voltage window is ≥1.1V±0.05V.
10. A chip comprising the chip pin multiplexing circuit according to any one of claims 1-9.
11. An electronic device comprising the chip of claim 10.